xref: /linux/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/{G2L,V2L} SMARC SOM common parts
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
10#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
11
12/* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
13#define EMMC	1
14
15/*
16 * To enable uSD card on CN3,
17 * SW1[2] should be at position 3/ON.
18 * Disable eMMC by setting "#define EMMC	0" above.
19 */
20#define SDHI	(!EMMC)
21
22/ {
23	aliases {
24		ethernet0 = &eth0;
25		ethernet1 = &eth1;
26	};
27
28	chosen {
29		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
30	};
31
32	memory@48000000 {
33		device_type = "memory";
34		/* first 128MB is reserved for secure area. */
35		reg = <0x0 0x48000000 0x0 0x78000000>;
36	};
37
38	reg_1p8v: regulator-1p8v {
39		compatible = "regulator-fixed";
40		regulator-name = "fixed-1.8V";
41		regulator-min-microvolt = <1800000>;
42		regulator-max-microvolt = <1800000>;
43		regulator-boot-on;
44		regulator-always-on;
45	};
46
47	reg_3p3v: regulator-3p3v {
48		compatible = "regulator-fixed";
49		regulator-name = "fixed-3.3V";
50		regulator-min-microvolt = <3300000>;
51		regulator-max-microvolt = <3300000>;
52		regulator-boot-on;
53		regulator-always-on;
54	};
55
56	reg_1p1v: regulator-vdd-core {
57		compatible = "regulator-fixed";
58		regulator-name = "fixed-1.1V";
59		regulator-min-microvolt = <1100000>;
60		regulator-max-microvolt = <1100000>;
61		regulator-boot-on;
62		regulator-always-on;
63	};
64
65	vccq_sdhi0: regulator-vccq-sdhi0 {
66		compatible = "regulator-gpio";
67
68		regulator-name = "SDHI0 VccQ";
69		regulator-min-microvolt = <1800000>;
70		regulator-max-microvolt = <3300000>;
71		states = <3300000 1>, <1800000 0>;
72		regulator-boot-on;
73		gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
74		regulator-always-on;
75	};
76
77	/* 32.768kHz crystal */
78	x2: x2-clock {
79		compatible = "fixed-clock";
80		#clock-cells = <0>;
81		clock-frequency = <32768>;
82	};
83};
84
85&adc {
86	pinctrl-0 = <&adc_pins>;
87	pinctrl-names = "default";
88	status = "okay";
89
90	/delete-node/ channel@6;
91	/delete-node/ channel@7;
92};
93
94&eth0 {
95	pinctrl-0 = <&eth0_pins>;
96	pinctrl-names = "default";
97	phy-handle = <&phy0>;
98	phy-mode = "rgmii-id";
99	status = "okay";
100
101	phy0: ethernet-phy@7 {
102		compatible = "ethernet-phy-id0022.1640",
103			     "ethernet-phy-ieee802.3-c22";
104		reg = <7>;
105		interrupts-extended = <&irqc RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
106		rxc-skew-psec = <2400>;
107		txc-skew-psec = <2400>;
108		rxdv-skew-psec = <0>;
109		txen-skew-psec = <0>;
110		rxd0-skew-psec = <0>;
111		rxd1-skew-psec = <0>;
112		rxd2-skew-psec = <0>;
113		rxd3-skew-psec = <0>;
114		txd0-skew-psec = <0>;
115		txd1-skew-psec = <0>;
116		txd2-skew-psec = <0>;
117		txd3-skew-psec = <0>;
118	};
119};
120
121&eth1 {
122	pinctrl-0 = <&eth1_pins>;
123	pinctrl-names = "default";
124	phy-handle = <&phy1>;
125	phy-mode = "rgmii-id";
126	status = "okay";
127
128	phy1: ethernet-phy@7 {
129		compatible = "ethernet-phy-id0022.1640",
130			     "ethernet-phy-ieee802.3-c22";
131		reg = <7>;
132		interrupts-extended = <&irqc RZG2L_IRQ3 IRQ_TYPE_LEVEL_LOW>;
133		rxc-skew-psec = <2400>;
134		txc-skew-psec = <2400>;
135		rxdv-skew-psec = <0>;
136		txen-skew-psec = <0>;
137		rxd0-skew-psec = <0>;
138		rxd1-skew-psec = <0>;
139		rxd2-skew-psec = <0>;
140		rxd3-skew-psec = <0>;
141		txd0-skew-psec = <0>;
142		txd1-skew-psec = <0>;
143		txd2-skew-psec = <0>;
144		txd3-skew-psec = <0>;
145	};
146};
147
148&extal_clk {
149	clock-frequency = <24000000>;
150};
151
152&gpu {
153	mali-supply = <&reg_1p1v>;
154};
155
156&i2c3 {
157	raa215300: pmic@12 {
158		compatible = "renesas,raa215300";
159		reg = <0x12>, <0x6f>;
160		reg-names = "main", "rtc";
161
162		clocks = <&x2>;
163		clock-names = "xin";
164	};
165};
166
167&ostm1 {
168	status = "okay";
169};
170
171&ostm2 {
172	status = "okay";
173};
174
175&pinctrl {
176	adc_pins: adc {
177		pinmux = <RZG2L_PORT_PINMUX(9, 0, 2)>; /* ADC_TRG */
178	};
179
180	eth0_pins: eth0 {
181		txc {
182			pinmux = <RZG2L_PORT_PINMUX(20, 0, 1)>; /* ET0_TXC */
183			power-source = <1800>;
184			output-enable;
185		};
186
187		mux {
188			pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
189				 <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
190				 <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
191				 <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
192				 <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
193				 <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
194				 <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
195				 <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
196				 <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
197				 <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
198				 <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
199				 <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
200				 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
201				 <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
202			power-source = <1800>;
203		};
204
205		irq {
206			pinmux = <RZG2L_PORT_PINMUX(1, 0, 1)>;  /* IRQ2 */
207		};
208	};
209
210	eth1_pins: eth1 {
211		txc {
212			pinmux = <RZG2L_PORT_PINMUX(29, 0, 1)>; /* ET1_TXC */
213			power-source = <1800>;
214			output-enable;
215		};
216
217		mux {
218			pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
219				 <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
220				 <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
221				 <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
222				 <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
223				 <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
224				 <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
225				 <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
226				 <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
227				 <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
228				 <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
229				 <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
230				 <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
231				 <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
232			power-source = <1800>;
233		};
234
235		irq {
236			pinmux = <RZG2L_PORT_PINMUX(1, 1, 1)>;  /* IRQ3 */
237		};
238	};
239
240	gpio-sd0-pwr-en-hog {
241		gpio-hog;
242		gpios = <RZG2L_GPIO(4, 1) GPIO_ACTIVE_HIGH>;
243		output-high;
244		line-name = "gpio_sd0_pwr_en";
245	};
246
247	qspi0_pins: qspi0 {
248		qspi0-data {
249			pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
250			power-source = <1800>;
251		};
252
253		qspi0-ctrl {
254			pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
255			power-source = <1800>;
256		};
257	};
258
259	/*
260	 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
261	 * The below switch logic can be used to select the device between
262	 * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
263	 * SW1[2] should be at position 2/OFF to enable 64 GB eMMC
264	 * SW1[2] should be at position 3/ON to enable uSD card CN3
265	 */
266	sd0-dev-sel-hog {
267		gpio-hog;
268		gpios = <RZG2L_GPIO(41, 1) GPIO_ACTIVE_HIGH>;
269		output-high;
270		line-name = "sd0_dev_sel";
271	};
272
273	sdhi0_emmc_pins: sd0emmc {
274		sd0_emmc_data {
275			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
276			       "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
277			power-source = <1800>;
278		};
279
280		sd0_emmc_ctrl {
281			pins = "SD0_CLK", "SD0_CMD";
282			power-source = <1800>;
283		};
284
285		sd0_emmc_rst {
286			pins = "SD0_RST#";
287			power-source = <1800>;
288		};
289	};
290
291	sdhi0_pins: sd0 {
292		sd0_data {
293			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
294			power-source = <3300>;
295		};
296
297		sd0_ctrl {
298			pins = "SD0_CLK", "SD0_CMD";
299			power-source = <3300>;
300		};
301
302		sd0_mux {
303			pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
304		};
305	};
306
307	sdhi0_pins_uhs: sd0_uhs {
308		sd0_data_uhs {
309			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
310			power-source = <1800>;
311		};
312
313		sd0_ctrl_uhs {
314			pins = "SD0_CLK", "SD0_CMD";
315			power-source = <1800>;
316		};
317
318		sd0_mux_uhs {
319			pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
320		};
321	};
322};
323
324&sbc {
325	pinctrl-0 = <&qspi0_pins>;
326	pinctrl-names = "default";
327	status = "okay";
328
329	flash@0 {
330		compatible = "micron,mt25qu512a", "jedec,spi-nor";
331		reg = <0>;
332		m25p,fast-read;
333		spi-max-frequency = <50000000>;
334		spi-rx-bus-width = <4>;
335		spi-tx-bus-width = <4>;
336
337		partitions {
338			compatible = "fixed-partitions";
339			#address-cells = <1>;
340			#size-cells = <1>;
341
342			partition@0 {
343				label = "bl2";
344				reg = <0x00000000 0x0001d000>;
345			};
346
347			partition@1d000 { /* fip is at offset 0x200 */
348				label = "fip";
349				reg = <0x0001d000 0x1fe3000>;
350			};
351
352			partition@2000000 {
353				label = "user";
354				reg = <0x2000000 0x2000000>;
355			};
356		};
357	};
358};
359
360#if SDHI
361&sdhi0 {
362	pinctrl-0 = <&sdhi0_pins>;
363	pinctrl-1 = <&sdhi0_pins_uhs>;
364	pinctrl-names = "default", "state_uhs";
365
366	vmmc-supply = <&reg_3p3v>;
367	vqmmc-supply = <&vccq_sdhi0>;
368	bus-width = <4>;
369	sd-uhs-sdr50;
370	sd-uhs-sdr104;
371	status = "okay";
372};
373#endif
374
375#if EMMC
376&sdhi0 {
377	pinctrl-0 = <&sdhi0_emmc_pins>;
378	pinctrl-1 = <&sdhi0_emmc_pins>;
379	pinctrl-names = "default", "state_uhs";
380
381	vmmc-supply = <&reg_3p3v>;
382	vqmmc-supply = <&reg_1p8v>;
383	bus-width = <8>;
384	mmc-hs200-1_8v;
385	non-removable;
386	fixed-emmc-driver-type = <1>;
387	status = "okay";
388};
389#endif
390
391&wdt0 {
392	status = "okay";
393	timeout-sec = <60>;
394};
395
396&wdt1 {
397	status = "okay";
398	timeout-sec = <60>;
399};
400