1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/V2H(P) SoC 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g057-cpg.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "renesas,r9a09g057"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_extal_clk: audio-clk { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by the board */ 20 clock-frequency = <0>; 21 }; 22 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 cpu0: cpu@0 { 28 compatible = "arm,cortex-a55"; 29 reg = <0>; 30 device_type = "cpu"; 31 next-level-cache = <&L3_CA55>; 32 enable-method = "psci"; 33 }; 34 35 cpu1: cpu@100 { 36 compatible = "arm,cortex-a55"; 37 reg = <0x100>; 38 device_type = "cpu"; 39 next-level-cache = <&L3_CA55>; 40 enable-method = "psci"; 41 }; 42 43 cpu2: cpu@200 { 44 compatible = "arm,cortex-a55"; 45 reg = <0x200>; 46 device_type = "cpu"; 47 next-level-cache = <&L3_CA55>; 48 enable-method = "psci"; 49 }; 50 51 cpu3: cpu@300 { 52 compatible = "arm,cortex-a55"; 53 reg = <0x300>; 54 device_type = "cpu"; 55 next-level-cache = <&L3_CA55>; 56 enable-method = "psci"; 57 }; 58 59 L3_CA55: cache-controller-0 { 60 compatible = "cache"; 61 cache-unified; 62 cache-size = <0x100000>; 63 cache-level = <3>; 64 }; 65 }; 66 67 psci { 68 compatible = "arm,psci-1.0", "arm,psci-0.2"; 69 method = "smc"; 70 }; 71 72 qextal_clk: qextal-clk { 73 compatible = "fixed-clock"; 74 #clock-cells = <0>; 75 /* This value must be overridden by the board */ 76 clock-frequency = <0>; 77 }; 78 79 rtxin_clk: rtxin-clk { 80 compatible = "fixed-clock"; 81 #clock-cells = <0>; 82 /* This value must be overridden by the board */ 83 clock-frequency = <0>; 84 }; 85 86 soc: soc { 87 compatible = "simple-bus"; 88 interrupt-parent = <&gic>; 89 #address-cells = <2>; 90 #size-cells = <2>; 91 ranges; 92 93 icu: interrupt-controller@10400000 { 94 compatible = "renesas,r9a09g057-icu"; 95 reg = <0 0x10400000 0 0x10000>; 96 #interrupt-cells = <2>; 97 #address-cells = <0>; 98 interrupt-controller; 99 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, 149 <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, 150 <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 151 <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 152 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; 157 interrupt-names = "nmi", 158 "port_irq0", "port_irq1", "port_irq2", 159 "port_irq3", "port_irq4", "port_irq5", 160 "port_irq6", "port_irq7", "port_irq8", 161 "port_irq9", "port_irq10", "port_irq11", 162 "port_irq12", "port_irq13", "port_irq14", 163 "port_irq15", 164 "tint0", "tint1", "tint2", "tint3", 165 "tint4", "tint5", "tint6", "tint7", 166 "tint8", "tint9", "tint10", "tint11", 167 "tint12", "tint13", "tint14", "tint15", 168 "tint16", "tint17", "tint18", "tint19", 169 "tint20", "tint21", "tint22", "tint23", 170 "tint24", "tint25", "tint26", "tint27", 171 "tint28", "tint29", "tint30", "tint31", 172 "int-ca55-0", "int-ca55-1", 173 "int-ca55-2", "int-ca55-3", 174 "icu-error-ca55", 175 "gpt-u0-gtciada", "gpt-u0-gtciadb", 176 "gpt-u1-gtciada", "gpt-u1-gtciadb"; 177 clocks = <&cpg CPG_MOD 0x5>; 178 power-domains = <&cpg>; 179 resets = <&cpg 0x36>; 180 }; 181 182 pinctrl: pinctrl@10410000 { 183 compatible = "renesas,r9a09g057-pinctrl"; 184 reg = <0 0x10410000 0 0x10000>; 185 clocks = <&cpg CPG_CORE R9A09G057_IOTOP_0_SHCLK>; 186 gpio-controller; 187 #gpio-cells = <2>; 188 gpio-ranges = <&pinctrl 0 0 96>; 189 #interrupt-cells = <2>; 190 interrupt-controller; 191 interrupt-parent = <&icu>; 192 power-domains = <&cpg>; 193 resets = <&cpg 0xa5>, <&cpg 0xa6>; 194 }; 195 196 cpg: clock-controller@10420000 { 197 compatible = "renesas,r9a09g057-cpg"; 198 reg = <0 0x10420000 0 0x10000>; 199 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; 200 clock-names = "audio_extal", "rtxin", "qextal"; 201 #clock-cells = <2>; 202 #reset-cells = <1>; 203 #power-domain-cells = <0>; 204 }; 205 206 sys: system-controller@10430000 { 207 compatible = "renesas,r9a09g057-sys"; 208 reg = <0 0x10430000 0 0x10000>; 209 clocks = <&cpg CPG_CORE R9A09G057_SYS_0_PCLK>; 210 resets = <&cpg 0x30>; 211 status = "disabled"; 212 }; 213 214 ostm0: timer@11800000 { 215 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 216 reg = <0x0 0x11800000 0x0 0x1000>; 217 interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>; 218 clocks = <&cpg CPG_MOD 0x43>; 219 resets = <&cpg 0x6d>; 220 power-domains = <&cpg>; 221 status = "disabled"; 222 }; 223 224 ostm1: timer@11801000 { 225 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 226 reg = <0x0 0x11801000 0x0 0x1000>; 227 interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>; 228 clocks = <&cpg CPG_MOD 0x44>; 229 resets = <&cpg 0x6e>; 230 power-domains = <&cpg>; 231 status = "disabled"; 232 }; 233 234 ostm2: timer@14000000 { 235 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 236 reg = <0x0 0x14000000 0x0 0x1000>; 237 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>; 238 clocks = <&cpg CPG_MOD 0x45>; 239 resets = <&cpg 0x6f>; 240 power-domains = <&cpg>; 241 status = "disabled"; 242 }; 243 244 ostm3: timer@14001000 { 245 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 246 reg = <0x0 0x14001000 0x0 0x1000>; 247 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>; 248 clocks = <&cpg CPG_MOD 0x46>; 249 resets = <&cpg 0x70>; 250 power-domains = <&cpg>; 251 status = "disabled"; 252 }; 253 254 ostm4: timer@12c00000 { 255 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 256 reg = <0x0 0x12c00000 0x0 0x1000>; 257 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 258 clocks = <&cpg CPG_MOD 0x47>; 259 resets = <&cpg 0x71>; 260 power-domains = <&cpg>; 261 status = "disabled"; 262 }; 263 264 ostm5: timer@12c01000 { 265 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 266 reg = <0x0 0x12c01000 0x0 0x1000>; 267 interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 268 clocks = <&cpg CPG_MOD 0x48>; 269 resets = <&cpg 0x72>; 270 power-domains = <&cpg>; 271 status = "disabled"; 272 }; 273 274 ostm6: timer@12c02000 { 275 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 276 reg = <0x0 0x12c02000 0x0 0x1000>; 277 interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; 278 clocks = <&cpg CPG_MOD 0x49>; 279 resets = <&cpg 0x73>; 280 power-domains = <&cpg>; 281 status = "disabled"; 282 }; 283 284 ostm7: timer@12c03000 { 285 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 286 reg = <0x0 0x12c03000 0x0 0x1000>; 287 interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>; 288 clocks = <&cpg CPG_MOD 0x4a>; 289 resets = <&cpg 0x74>; 290 power-domains = <&cpg>; 291 status = "disabled"; 292 }; 293 294 wdt0: watchdog@11c00400 { 295 compatible = "renesas,r9a09g057-wdt"; 296 reg = <0 0x11c00400 0 0x400>; 297 clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>; 298 clock-names = "pclk", "oscclk"; 299 resets = <&cpg 0x75>; 300 power-domains = <&cpg>; 301 status = "disabled"; 302 }; 303 304 wdt1: watchdog@14400000 { 305 compatible = "renesas,r9a09g057-wdt"; 306 reg = <0 0x14400000 0 0x400>; 307 clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; 308 clock-names = "pclk", "oscclk"; 309 resets = <&cpg 0x76>; 310 power-domains = <&cpg>; 311 status = "disabled"; 312 }; 313 314 wdt2: watchdog@13000000 { 315 compatible = "renesas,r9a09g057-wdt"; 316 reg = <0 0x13000000 0 0x400>; 317 clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>; 318 clock-names = "pclk", "oscclk"; 319 resets = <&cpg 0x77>; 320 power-domains = <&cpg>; 321 status = "disabled"; 322 }; 323 324 wdt3: watchdog@13000400 { 325 compatible = "renesas,r9a09g057-wdt"; 326 reg = <0 0x13000400 0 0x400>; 327 clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>; 328 clock-names = "pclk", "oscclk"; 329 resets = <&cpg 0x78>; 330 power-domains = <&cpg>; 331 status = "disabled"; 332 }; 333 334 scif: serial@11c01400 { 335 compatible = "renesas,scif-r9a09g057"; 336 reg = <0 0x11c01400 0 0x400>; 337 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, 345 <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; 346 interrupt-names = "eri", "rxi", "txi", "bri", "dri", 347 "tei", "tei-dri", "rxi-edge", "txi-edge"; 348 clocks = <&cpg CPG_MOD 0x8f>; 349 clock-names = "fck"; 350 power-domains = <&cpg>; 351 resets = <&cpg 0x95>; 352 status = "disabled"; 353 }; 354 355 i2c0: i2c@14400400 { 356 compatible = "renesas,riic-r9a09g057"; 357 reg = <0 0x14400400 0 0x400>; 358 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, 360 <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>, 361 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 366 interrupt-names = "tei", "ri", "ti", "spi", "sti", 367 "naki", "ali", "tmoi"; 368 clocks = <&cpg CPG_MOD 0x94>; 369 resets = <&cpg 0x98>; 370 power-domains = <&cpg>; 371 #address-cells = <1>; 372 #size-cells = <0>; 373 status = "disabled"; 374 }; 375 376 i2c1: i2c@14400800 { 377 compatible = "renesas,riic-r9a09g057"; 378 reg = <0 0x14400800 0 0x400>; 379 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>, 381 <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, 382 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 387 interrupt-names = "tei", "ri", "ti", "spi", "sti", 388 "naki", "ali", "tmoi"; 389 clocks = <&cpg CPG_MOD 0x95>; 390 resets = <&cpg 0x99>; 391 power-domains = <&cpg>; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 status = "disabled"; 395 }; 396 397 i2c2: i2c@14400c00 { 398 compatible = "renesas,riic-r9a09g057"; 399 reg = <0 0x14400c00 0 0x400>; 400 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>, 402 <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>, 403 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 405 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 408 interrupt-names = "tei", "ri", "ti", "spi", "sti", 409 "naki", "ali", "tmoi"; 410 clocks = <&cpg CPG_MOD 0x96>; 411 resets = <&cpg 0x9a>; 412 power-domains = <&cpg>; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 status = "disabled"; 416 }; 417 418 i2c3: i2c@14401000 { 419 compatible = "renesas,riic-r9a09g057"; 420 reg = <0 0x14401000 0 0x400>; 421 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>, 423 <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>, 424 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 429 interrupt-names = "tei", "ri", "ti", "spi", "sti", 430 "naki", "ali", "tmoi"; 431 clocks = <&cpg CPG_MOD 0x97>; 432 resets = <&cpg 0x9b>; 433 power-domains = <&cpg>; 434 #address-cells = <1>; 435 #size-cells = <0>; 436 status = "disabled"; 437 }; 438 439 i2c4: i2c@14401400 { 440 compatible = "renesas,riic-r9a09g057"; 441 reg = <0 0x14401400 0 0x400>; 442 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>, 444 <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>, 445 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 450 interrupt-names = "tei", "ri", "ti", "spi", "sti", 451 "naki", "ali", "tmoi"; 452 clocks = <&cpg CPG_MOD 0x98>; 453 resets = <&cpg 0x9c>; 454 power-domains = <&cpg>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 status = "disabled"; 458 }; 459 460 i2c5: i2c@14401800 { 461 compatible = "renesas,riic-r9a09g057"; 462 reg = <0 0x14401800 0 0x400>; 463 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>, 465 <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>, 466 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 471 interrupt-names = "tei", "ri", "ti", "spi", "sti", 472 "naki", "ali", "tmoi"; 473 clocks = <&cpg CPG_MOD 0x99>; 474 resets = <&cpg 0x9d>; 475 power-domains = <&cpg>; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 status = "disabled"; 479 }; 480 481 i2c6: i2c@14401c00 { 482 compatible = "renesas,riic-r9a09g057"; 483 reg = <0 0x14401c00 0 0x400>; 484 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>, 486 <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, 487 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 492 interrupt-names = "tei", "ri", "ti", "spi", "sti", 493 "naki", "ali", "tmoi"; 494 clocks = <&cpg CPG_MOD 0x9a>; 495 resets = <&cpg 0x9e>; 496 power-domains = <&cpg>; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 status = "disabled"; 500 }; 501 502 i2c7: i2c@14402000 { 503 compatible = "renesas,riic-r9a09g057"; 504 reg = <0 0x14402000 0 0x400>; 505 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>, 507 <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>, 508 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 513 interrupt-names = "tei", "ri", "ti", "spi", "sti", 514 "naki", "ali", "tmoi"; 515 clocks = <&cpg CPG_MOD 0x9b>; 516 resets = <&cpg 0x9f>; 517 power-domains = <&cpg>; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 status = "disabled"; 521 }; 522 523 i2c8: i2c@11c01000 { 524 compatible = "renesas,riic-r9a09g057"; 525 reg = <0 0x11c01000 0 0x400>; 526 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>, 528 <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>, 529 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 534 interrupt-names = "tei", "ri", "ti", "spi", "sti", 535 "naki", "ali", "tmoi"; 536 clocks = <&cpg CPG_MOD 0x93>; 537 resets = <&cpg 0xa0>; 538 power-domains = <&cpg>; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 status = "disabled"; 542 }; 543 544 gic: interrupt-controller@14900000 { 545 compatible = "arm,gic-v3"; 546 reg = <0x0 0x14900000 0 0x20000>, 547 <0x0 0x14940000 0 0x80000>; 548 #interrupt-cells = <3>; 549 #address-cells = <0>; 550 interrupt-controller; 551 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 552 }; 553 554 sdhi0: mmc@15c00000 { 555 compatible = "renesas,sdhi-r9a09g057"; 556 reg = <0x0 0x15c00000 0 0x10000>; 557 interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, 560 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; 561 clock-names = "core", "clkh", "cd", "aclk"; 562 resets = <&cpg 0xa7>; 563 power-domains = <&cpg>; 564 status = "disabled"; 565 }; 566 567 sdhi1: mmc@15c10000 { 568 compatible = "renesas,sdhi-r9a09g057"; 569 reg = <0x0 0x15c10000 0 0x10000>; 570 interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, 573 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; 574 clock-names = "core", "clkh", "cd", "aclk"; 575 resets = <&cpg 0xa8>; 576 power-domains = <&cpg>; 577 status = "disabled"; 578 }; 579 580 sdhi2: mmc@15c20000 { 581 compatible = "renesas,sdhi-r9a09g057"; 582 reg = <0x0 0x15c20000 0 0x10000>; 583 interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, 586 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; 587 clock-names = "core", "clkh", "cd", "aclk"; 588 resets = <&cpg 0xa9>; 589 power-domains = <&cpg>; 590 status = "disabled"; 591 }; 592 }; 593 594 timer { 595 compatible = "arm,armv8-timer"; 596 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 597 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 598 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 599 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 600 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 601 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 602 }; 603}; 604