1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/V2H(P) SoC 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g057-cpg.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "renesas,r9a09g057"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_extal_clk: audio-clk { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by the board */ 20 clock-frequency = <0>; 21 }; 22 23 /* 24 * The default cluster table is based on the assumption that the PLLCA55 clock 25 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to 26 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be 27 * clocked to 1.8GHz as well). The table below should be overridden in the board 28 * DTS based on the PLLCA55 clock frequency. 29 */ 30 cluster0_opp: opp-table-0 { 31 compatible = "operating-points-v2"; 32 33 opp-1700000000 { 34 opp-hz = /bits/ 64 <1700000000>; 35 opp-microvolt = <900000>; 36 clock-latency-ns = <300000>; 37 }; 38 opp-850000000 { 39 opp-hz = /bits/ 64 <850000000>; 40 opp-microvolt = <800000>; 41 clock-latency-ns = <300000>; 42 }; 43 opp-425000000 { 44 opp-hz = /bits/ 64 <425000000>; 45 opp-microvolt = <800000>; 46 clock-latency-ns = <300000>; 47 }; 48 opp-212500000 { 49 opp-hz = /bits/ 64 <212500000>; 50 opp-microvolt = <800000>; 51 clock-latency-ns = <300000>; 52 opp-suspend; 53 }; 54 }; 55 56 cpus { 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 cpu0: cpu@0 { 61 compatible = "arm,cortex-a55"; 62 reg = <0>; 63 device_type = "cpu"; 64 next-level-cache = <&L3_CA55>; 65 enable-method = "psci"; 66 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>; 67 operating-points-v2 = <&cluster0_opp>; 68 }; 69 70 cpu1: cpu@100 { 71 compatible = "arm,cortex-a55"; 72 reg = <0x100>; 73 device_type = "cpu"; 74 next-level-cache = <&L3_CA55>; 75 enable-method = "psci"; 76 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>; 77 operating-points-v2 = <&cluster0_opp>; 78 }; 79 80 cpu2: cpu@200 { 81 compatible = "arm,cortex-a55"; 82 reg = <0x200>; 83 device_type = "cpu"; 84 next-level-cache = <&L3_CA55>; 85 enable-method = "psci"; 86 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>; 87 operating-points-v2 = <&cluster0_opp>; 88 }; 89 90 cpu3: cpu@300 { 91 compatible = "arm,cortex-a55"; 92 reg = <0x300>; 93 device_type = "cpu"; 94 next-level-cache = <&L3_CA55>; 95 enable-method = "psci"; 96 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>; 97 operating-points-v2 = <&cluster0_opp>; 98 }; 99 100 L3_CA55: cache-controller-0 { 101 compatible = "cache"; 102 cache-unified; 103 cache-size = <0x100000>; 104 cache-level = <3>; 105 }; 106 }; 107 108 gpu_opp_table: opp-table-1 { 109 compatible = "operating-points-v2"; 110 111 opp-630000000 { 112 opp-hz = /bits/ 64 <630000000>; 113 opp-microvolt = <800000>; 114 }; 115 116 opp-315000000 { 117 opp-hz = /bits/ 64 <315000000>; 118 opp-microvolt = <800000>; 119 }; 120 121 opp-157500000 { 122 opp-hz = /bits/ 64 <157500000>; 123 opp-microvolt = <800000>; 124 }; 125 126 opp-78750000 { 127 opp-hz = /bits/ 64 <78750000>; 128 opp-microvolt = <800000>; 129 }; 130 131 opp-19687500 { 132 opp-hz = /bits/ 64 <19687500>; 133 opp-microvolt = <800000>; 134 }; 135 }; 136 137 psci { 138 compatible = "arm,psci-1.0", "arm,psci-0.2"; 139 method = "smc"; 140 }; 141 142 qextal_clk: qextal-clk { 143 compatible = "fixed-clock"; 144 #clock-cells = <0>; 145 /* This value must be overridden by the board */ 146 clock-frequency = <0>; 147 }; 148 149 rtxin_clk: rtxin-clk { 150 compatible = "fixed-clock"; 151 #clock-cells = <0>; 152 /* This value must be overridden by the board */ 153 clock-frequency = <0>; 154 }; 155 156 soc: soc { 157 compatible = "simple-bus"; 158 interrupt-parent = <&gic>; 159 #address-cells = <2>; 160 #size-cells = <2>; 161 ranges; 162 163 icu: interrupt-controller@10400000 { 164 compatible = "renesas,r9a09g057-icu"; 165 reg = <0 0x10400000 0 0x10000>; 166 #interrupt-cells = <2>; 167 #address-cells = <0>; 168 interrupt-controller; 169 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, 219 <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, 220 <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 221 <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 222 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; 227 interrupt-names = "nmi", 228 "port_irq0", "port_irq1", "port_irq2", 229 "port_irq3", "port_irq4", "port_irq5", 230 "port_irq6", "port_irq7", "port_irq8", 231 "port_irq9", "port_irq10", "port_irq11", 232 "port_irq12", "port_irq13", "port_irq14", 233 "port_irq15", 234 "tint0", "tint1", "tint2", "tint3", 235 "tint4", "tint5", "tint6", "tint7", 236 "tint8", "tint9", "tint10", "tint11", 237 "tint12", "tint13", "tint14", "tint15", 238 "tint16", "tint17", "tint18", "tint19", 239 "tint20", "tint21", "tint22", "tint23", 240 "tint24", "tint25", "tint26", "tint27", 241 "tint28", "tint29", "tint30", "tint31", 242 "int-ca55-0", "int-ca55-1", 243 "int-ca55-2", "int-ca55-3", 244 "icu-error-ca55", 245 "gpt-u0-gtciada", "gpt-u0-gtciadb", 246 "gpt-u1-gtciada", "gpt-u1-gtciadb"; 247 clocks = <&cpg CPG_MOD 0x5>; 248 power-domains = <&cpg>; 249 resets = <&cpg 0x36>; 250 }; 251 252 pinctrl: pinctrl@10410000 { 253 compatible = "renesas,r9a09g057-pinctrl"; 254 reg = <0 0x10410000 0 0x10000>; 255 clocks = <&cpg CPG_CORE R9A09G057_IOTOP_0_SHCLK>; 256 gpio-controller; 257 #gpio-cells = <2>; 258 gpio-ranges = <&pinctrl 0 0 96>; 259 #interrupt-cells = <2>; 260 interrupt-controller; 261 interrupt-parent = <&icu>; 262 power-domains = <&cpg>; 263 resets = <&cpg 0xa5>, <&cpg 0xa6>; 264 }; 265 266 cpg: clock-controller@10420000 { 267 compatible = "renesas,r9a09g057-cpg"; 268 reg = <0 0x10420000 0 0x10000>; 269 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; 270 clock-names = "audio_extal", "rtxin", "qextal"; 271 #clock-cells = <2>; 272 #reset-cells = <1>; 273 #power-domain-cells = <0>; 274 }; 275 276 sys: system-controller@10430000 { 277 compatible = "renesas,r9a09g057-sys"; 278 reg = <0 0x10430000 0 0x10000>; 279 clocks = <&cpg CPG_CORE R9A09G057_SYS_0_PCLK>; 280 resets = <&cpg 0x30>; 281 }; 282 283 dmac0: dma-controller@11400000 { 284 compatible = "renesas,r9a09g057-dmac"; 285 reg = <0 0x11400000 0 0x10000>; 286 interrupts = <GIC_SPI 499 IRQ_TYPE_EDGE_RISING>, 287 <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, 288 <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>, 289 <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>, 290 <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>, 291 <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>, 292 <GIC_SPI 94 IRQ_TYPE_EDGE_RISING>, 293 <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>, 294 <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>, 295 <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>, 296 <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>, 297 <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>, 298 <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, 299 <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>, 300 <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>, 301 <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>, 302 <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>; 303 interrupt-names = "error", 304 "ch0", "ch1", "ch2", "ch3", 305 "ch4", "ch5", "ch6", "ch7", 306 "ch8", "ch9", "ch10", "ch11", 307 "ch12", "ch13", "ch14", "ch15"; 308 clocks = <&cpg CPG_MOD 0x0>; 309 power-domains = <&cpg>; 310 resets = <&cpg 0x31>; 311 #dma-cells = <1>; 312 dma-channels = <16>; 313 renesas,icu = <&icu 4>; 314 }; 315 316 dmac1: dma-controller@14830000 { 317 compatible = "renesas,r9a09g057-dmac"; 318 reg = <0 0x14830000 0 0x10000>; 319 interrupts = <GIC_SPI 495 IRQ_TYPE_EDGE_RISING>, 320 <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, 321 <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, 322 <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, 323 <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, 324 <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>, 325 <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 326 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, 327 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 328 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 329 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 330 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 331 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 332 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 333 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 334 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, 335 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>; 336 interrupt-names = "error", 337 "ch0", "ch1", "ch2", "ch3", 338 "ch4", "ch5", "ch6", "ch7", 339 "ch8", "ch9", "ch10", "ch11", 340 "ch12", "ch13", "ch14", "ch15"; 341 clocks = <&cpg CPG_MOD 0x1>; 342 power-domains = <&cpg>; 343 resets = <&cpg 0x32>; 344 #dma-cells = <1>; 345 dma-channels = <16>; 346 renesas,icu = <&icu 0>; 347 }; 348 349 dmac2: dma-controller@14840000 { 350 compatible = "renesas,r9a09g057-dmac"; 351 reg = <0 0x14840000 0 0x10000>; 352 interrupts = <GIC_SPI 496 IRQ_TYPE_EDGE_RISING>, 353 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 354 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, 355 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, 356 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 357 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, 358 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, 359 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, 360 <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, 361 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, 362 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, 363 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 364 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 365 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, 366 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, 367 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 368 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>; 369 interrupt-names = "error", 370 "ch0", "ch1", "ch2", "ch3", 371 "ch4", "ch5", "ch6", "ch7", 372 "ch8", "ch9", "ch10", "ch11", 373 "ch12", "ch13", "ch14", "ch15"; 374 clocks = <&cpg CPG_MOD 0x2>; 375 power-domains = <&cpg>; 376 resets = <&cpg 0x33>; 377 #dma-cells = <1>; 378 dma-channels = <16>; 379 renesas,icu = <&icu 1>; 380 }; 381 382 dmac3: dma-controller@12000000 { 383 compatible = "renesas,r9a09g057-dmac"; 384 reg = <0 0x12000000 0 0x10000>; 385 interrupts = <GIC_SPI 497 IRQ_TYPE_EDGE_RISING>, 386 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, 387 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, 388 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, 389 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, 390 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, 391 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, 392 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, 393 <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>, 394 <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>, 395 <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, 396 <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, 397 <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>, 398 <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>, 399 <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>, 400 <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>, 401 <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; 402 interrupt-names = "error", 403 "ch0", "ch1", "ch2", "ch3", 404 "ch4", "ch5", "ch6", "ch7", 405 "ch8", "ch9", "ch10", "ch11", 406 "ch12", "ch13", "ch14", "ch15"; 407 clocks = <&cpg CPG_MOD 0x3>; 408 power-domains = <&cpg>; 409 resets = <&cpg 0x34>; 410 #dma-cells = <1>; 411 dma-channels = <16>; 412 renesas,icu = <&icu 2>; 413 }; 414 415 dmac4: dma-controller@12010000 { 416 compatible = "renesas,r9a09g057-dmac"; 417 reg = <0 0x12010000 0 0x10000>; 418 interrupts = <GIC_SPI 498 IRQ_TYPE_EDGE_RISING>, 419 <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, 420 <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, 421 <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, 422 <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, 423 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, 424 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 425 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 426 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 427 <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>, 428 <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>, 429 <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>, 430 <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>, 431 <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>, 432 <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>, 433 <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>, 434 <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 435 interrupt-names = "error", 436 "ch0", "ch1", "ch2", "ch3", 437 "ch4", "ch5", "ch6", "ch7", 438 "ch8", "ch9", "ch10", "ch11", 439 "ch12", "ch13", "ch14", "ch15"; 440 clocks = <&cpg CPG_MOD 0x4>; 441 power-domains = <&cpg>; 442 resets = <&cpg 0x35>; 443 #dma-cells = <1>; 444 dma-channels = <16>; 445 renesas,icu = <&icu 3>; 446 }; 447 448 ostm0: timer@11800000 { 449 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 450 reg = <0x0 0x11800000 0x0 0x1000>; 451 interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>; 452 clocks = <&cpg CPG_MOD 0x43>; 453 resets = <&cpg 0x6d>; 454 power-domains = <&cpg>; 455 status = "disabled"; 456 }; 457 458 ostm1: timer@11801000 { 459 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 460 reg = <0x0 0x11801000 0x0 0x1000>; 461 interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>; 462 clocks = <&cpg CPG_MOD 0x44>; 463 resets = <&cpg 0x6e>; 464 power-domains = <&cpg>; 465 status = "disabled"; 466 }; 467 468 ostm2: timer@14000000 { 469 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 470 reg = <0x0 0x14000000 0x0 0x1000>; 471 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>; 472 clocks = <&cpg CPG_MOD 0x45>; 473 resets = <&cpg 0x6f>; 474 power-domains = <&cpg>; 475 status = "disabled"; 476 }; 477 478 ostm3: timer@14001000 { 479 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 480 reg = <0x0 0x14001000 0x0 0x1000>; 481 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>; 482 clocks = <&cpg CPG_MOD 0x46>; 483 resets = <&cpg 0x70>; 484 power-domains = <&cpg>; 485 status = "disabled"; 486 }; 487 488 ostm4: timer@12c00000 { 489 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 490 reg = <0x0 0x12c00000 0x0 0x1000>; 491 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 492 clocks = <&cpg CPG_MOD 0x47>; 493 resets = <&cpg 0x71>; 494 power-domains = <&cpg>; 495 status = "disabled"; 496 }; 497 498 ostm5: timer@12c01000 { 499 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 500 reg = <0x0 0x12c01000 0x0 0x1000>; 501 interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 502 clocks = <&cpg CPG_MOD 0x48>; 503 resets = <&cpg 0x72>; 504 power-domains = <&cpg>; 505 status = "disabled"; 506 }; 507 508 ostm6: timer@12c02000 { 509 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 510 reg = <0x0 0x12c02000 0x0 0x1000>; 511 interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; 512 clocks = <&cpg CPG_MOD 0x49>; 513 resets = <&cpg 0x73>; 514 power-domains = <&cpg>; 515 status = "disabled"; 516 }; 517 518 ostm7: timer@12c03000 { 519 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 520 reg = <0x0 0x12c03000 0x0 0x1000>; 521 interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>; 522 clocks = <&cpg CPG_MOD 0x4a>; 523 resets = <&cpg 0x74>; 524 power-domains = <&cpg>; 525 status = "disabled"; 526 }; 527 528 wdt0: watchdog@11c00400 { 529 compatible = "renesas,r9a09g057-wdt"; 530 reg = <0 0x11c00400 0 0x400>; 531 clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>; 532 clock-names = "pclk", "oscclk"; 533 resets = <&cpg 0x75>; 534 power-domains = <&cpg>; 535 status = "disabled"; 536 }; 537 538 wdt1: watchdog@14400000 { 539 compatible = "renesas,r9a09g057-wdt"; 540 reg = <0 0x14400000 0 0x400>; 541 clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; 542 clock-names = "pclk", "oscclk"; 543 resets = <&cpg 0x76>; 544 power-domains = <&cpg>; 545 status = "disabled"; 546 }; 547 548 wdt2: watchdog@13000000 { 549 compatible = "renesas,r9a09g057-wdt"; 550 reg = <0 0x13000000 0 0x400>; 551 clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>; 552 clock-names = "pclk", "oscclk"; 553 resets = <&cpg 0x77>; 554 power-domains = <&cpg>; 555 status = "disabled"; 556 }; 557 558 wdt3: watchdog@13000400 { 559 compatible = "renesas,r9a09g057-wdt"; 560 reg = <0 0x13000400 0 0x400>; 561 clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>; 562 clock-names = "pclk", "oscclk"; 563 resets = <&cpg 0x78>; 564 power-domains = <&cpg>; 565 status = "disabled"; 566 }; 567 568 scif: serial@11c01400 { 569 compatible = "renesas,scif-r9a09g057"; 570 reg = <0 0x11c01400 0 0x400>; 571 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, 579 <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; 580 interrupt-names = "eri", "rxi", "txi", "bri", "dri", 581 "tei", "tei-dri", "rxi-edge", "txi-edge"; 582 clocks = <&cpg CPG_MOD 0x8f>; 583 clock-names = "fck"; 584 power-domains = <&cpg>; 585 resets = <&cpg 0x95>; 586 status = "disabled"; 587 }; 588 589 i2c0: i2c@14400400 { 590 compatible = "renesas,riic-r9a09g057"; 591 reg = <0 0x14400400 0 0x400>; 592 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, 594 <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>, 595 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 600 interrupt-names = "tei", "ri", "ti", "spi", "sti", 601 "naki", "ali", "tmoi"; 602 clocks = <&cpg CPG_MOD 0x94>; 603 resets = <&cpg 0x98>; 604 power-domains = <&cpg>; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 status = "disabled"; 608 }; 609 610 i2c1: i2c@14400800 { 611 compatible = "renesas,riic-r9a09g057"; 612 reg = <0 0x14400800 0 0x400>; 613 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>, 615 <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, 616 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 621 interrupt-names = "tei", "ri", "ti", "spi", "sti", 622 "naki", "ali", "tmoi"; 623 clocks = <&cpg CPG_MOD 0x95>; 624 resets = <&cpg 0x99>; 625 power-domains = <&cpg>; 626 #address-cells = <1>; 627 #size-cells = <0>; 628 status = "disabled"; 629 }; 630 631 i2c2: i2c@14400c00 { 632 compatible = "renesas,riic-r9a09g057"; 633 reg = <0 0x14400c00 0 0x400>; 634 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>, 636 <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>, 637 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 642 interrupt-names = "tei", "ri", "ti", "spi", "sti", 643 "naki", "ali", "tmoi"; 644 clocks = <&cpg CPG_MOD 0x96>; 645 resets = <&cpg 0x9a>; 646 power-domains = <&cpg>; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 status = "disabled"; 650 }; 651 652 i2c3: i2c@14401000 { 653 compatible = "renesas,riic-r9a09g057"; 654 reg = <0 0x14401000 0 0x400>; 655 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>, 657 <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>, 658 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 663 interrupt-names = "tei", "ri", "ti", "spi", "sti", 664 "naki", "ali", "tmoi"; 665 clocks = <&cpg CPG_MOD 0x97>; 666 resets = <&cpg 0x9b>; 667 power-domains = <&cpg>; 668 #address-cells = <1>; 669 #size-cells = <0>; 670 status = "disabled"; 671 }; 672 673 i2c4: i2c@14401400 { 674 compatible = "renesas,riic-r9a09g057"; 675 reg = <0 0x14401400 0 0x400>; 676 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>, 678 <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>, 679 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 684 interrupt-names = "tei", "ri", "ti", "spi", "sti", 685 "naki", "ali", "tmoi"; 686 clocks = <&cpg CPG_MOD 0x98>; 687 resets = <&cpg 0x9c>; 688 power-domains = <&cpg>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 status = "disabled"; 692 }; 693 694 i2c5: i2c@14401800 { 695 compatible = "renesas,riic-r9a09g057"; 696 reg = <0 0x14401800 0 0x400>; 697 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>, 699 <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>, 700 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 705 interrupt-names = "tei", "ri", "ti", "spi", "sti", 706 "naki", "ali", "tmoi"; 707 clocks = <&cpg CPG_MOD 0x99>; 708 resets = <&cpg 0x9d>; 709 power-domains = <&cpg>; 710 #address-cells = <1>; 711 #size-cells = <0>; 712 status = "disabled"; 713 }; 714 715 i2c6: i2c@14401c00 { 716 compatible = "renesas,riic-r9a09g057"; 717 reg = <0 0x14401c00 0 0x400>; 718 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>, 720 <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, 721 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 726 interrupt-names = "tei", "ri", "ti", "spi", "sti", 727 "naki", "ali", "tmoi"; 728 clocks = <&cpg CPG_MOD 0x9a>; 729 resets = <&cpg 0x9e>; 730 power-domains = <&cpg>; 731 #address-cells = <1>; 732 #size-cells = <0>; 733 status = "disabled"; 734 }; 735 736 i2c7: i2c@14402000 { 737 compatible = "renesas,riic-r9a09g057"; 738 reg = <0 0x14402000 0 0x400>; 739 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>, 741 <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>, 742 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 747 interrupt-names = "tei", "ri", "ti", "spi", "sti", 748 "naki", "ali", "tmoi"; 749 clocks = <&cpg CPG_MOD 0x9b>; 750 resets = <&cpg 0x9f>; 751 power-domains = <&cpg>; 752 #address-cells = <1>; 753 #size-cells = <0>; 754 status = "disabled"; 755 }; 756 757 i2c8: i2c@11c01000 { 758 compatible = "renesas,riic-r9a09g057"; 759 reg = <0 0x11c01000 0 0x400>; 760 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>, 762 <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>, 763 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 768 interrupt-names = "tei", "ri", "ti", "spi", "sti", 769 "naki", "ali", "tmoi"; 770 clocks = <&cpg CPG_MOD 0x93>; 771 resets = <&cpg 0xa0>; 772 power-domains = <&cpg>; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 status = "disabled"; 776 }; 777 778 gpu: gpu@14850000 { 779 compatible = "renesas,r9a09g057-mali", 780 "arm,mali-bifrost"; 781 reg = <0x0 0x14850000 0x0 0x10000>; 782 interrupts = <GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>; 786 interrupt-names = "job", "mmu", "gpu", "event"; 787 clocks = <&cpg CPG_MOD 0xf0>, 788 <&cpg CPG_MOD 0xf1>, 789 <&cpg CPG_MOD 0xf2>; 790 clock-names = "gpu", "bus", "bus_ace"; 791 power-domains = <&cpg>; 792 resets = <&cpg 0xdd>, 793 <&cpg 0xde>, 794 <&cpg 0xdf>; 795 reset-names = "rst", "axi_rst", "ace_rst"; 796 operating-points-v2 = <&gpu_opp_table>; 797 status = "disabled"; 798 }; 799 800 gic: interrupt-controller@14900000 { 801 compatible = "arm,gic-v3"; 802 reg = <0x0 0x14900000 0 0x20000>, 803 <0x0 0x14940000 0 0x80000>; 804 #interrupt-cells = <3>; 805 #address-cells = <0>; 806 interrupt-controller; 807 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 808 }; 809 810 sdhi0: mmc@15c00000 { 811 compatible = "renesas,sdhi-r9a09g057"; 812 reg = <0x0 0x15c00000 0 0x10000>; 813 interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>; 815 clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, 816 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; 817 clock-names = "core", "clkh", "cd", "aclk"; 818 resets = <&cpg 0xa7>; 819 power-domains = <&cpg>; 820 status = "disabled"; 821 822 sdhi0_vqmmc: vqmmc-regulator { 823 regulator-name = "SDHI0-VQMMC"; 824 regulator-min-microvolt = <1800000>; 825 regulator-max-microvolt = <3300000>; 826 status = "disabled"; 827 }; 828 }; 829 830 sdhi1: mmc@15c10000 { 831 compatible = "renesas,sdhi-r9a09g057"; 832 reg = <0x0 0x15c10000 0 0x10000>; 833 interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, 836 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; 837 clock-names = "core", "clkh", "cd", "aclk"; 838 resets = <&cpg 0xa8>; 839 power-domains = <&cpg>; 840 status = "disabled"; 841 842 sdhi1_vqmmc: vqmmc-regulator { 843 regulator-name = "SDHI1-VQMMC"; 844 regulator-min-microvolt = <1800000>; 845 regulator-max-microvolt = <3300000>; 846 status = "disabled"; 847 }; 848 }; 849 850 sdhi2: mmc@15c20000 { 851 compatible = "renesas,sdhi-r9a09g057"; 852 reg = <0x0 0x15c20000 0 0x10000>; 853 interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, 856 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; 857 clock-names = "core", "clkh", "cd", "aclk"; 858 resets = <&cpg 0xa9>; 859 power-domains = <&cpg>; 860 status = "disabled"; 861 862 sdhi2_vqmmc: vqmmc-regulator { 863 regulator-name = "SDHI2-VQMMC"; 864 regulator-min-microvolt = <1800000>; 865 regulator-max-microvolt = <3300000>; 866 status = "disabled"; 867 }; 868 }; 869 }; 870 871 timer { 872 compatible = "arm,armv8-timer"; 873 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 874 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 875 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 876 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 877 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 878 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 879 }; 880}; 881