1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/V2H(P) SoC 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g057-cpg.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "renesas,r9a09g057"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_extal_clk: audio-clk { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by the board */ 20 clock-frequency = <0>; 21 }; 22 23 /* 24 * The default cluster table is based on the assumption that the PLLCA55 clock 25 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to 26 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be 27 * clocked to 1.8GHz as well). The table below should be overridden in the board 28 * DTS based on the PLLCA55 clock frequency. 29 */ 30 cluster0_opp: opp-table-0 { 31 compatible = "operating-points-v2"; 32 33 opp-1700000000 { 34 opp-hz = /bits/ 64 <1700000000>; 35 opp-microvolt = <900000>; 36 clock-latency-ns = <300000>; 37 }; 38 opp-850000000 { 39 opp-hz = /bits/ 64 <850000000>; 40 opp-microvolt = <800000>; 41 clock-latency-ns = <300000>; 42 }; 43 opp-425000000 { 44 opp-hz = /bits/ 64 <425000000>; 45 opp-microvolt = <800000>; 46 clock-latency-ns = <300000>; 47 }; 48 opp-212500000 { 49 opp-hz = /bits/ 64 <212500000>; 50 opp-microvolt = <800000>; 51 clock-latency-ns = <300000>; 52 opp-suspend; 53 }; 54 }; 55 56 cpus { 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 cpu0: cpu@0 { 61 compatible = "arm,cortex-a55"; 62 reg = <0>; 63 device_type = "cpu"; 64 next-level-cache = <&L3_CA55>; 65 enable-method = "psci"; 66 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>; 67 operating-points-v2 = <&cluster0_opp>; 68 }; 69 70 cpu1: cpu@100 { 71 compatible = "arm,cortex-a55"; 72 reg = <0x100>; 73 device_type = "cpu"; 74 next-level-cache = <&L3_CA55>; 75 enable-method = "psci"; 76 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>; 77 operating-points-v2 = <&cluster0_opp>; 78 }; 79 80 cpu2: cpu@200 { 81 compatible = "arm,cortex-a55"; 82 reg = <0x200>; 83 device_type = "cpu"; 84 next-level-cache = <&L3_CA55>; 85 enable-method = "psci"; 86 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>; 87 operating-points-v2 = <&cluster0_opp>; 88 }; 89 90 cpu3: cpu@300 { 91 compatible = "arm,cortex-a55"; 92 reg = <0x300>; 93 device_type = "cpu"; 94 next-level-cache = <&L3_CA55>; 95 enable-method = "psci"; 96 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>; 97 operating-points-v2 = <&cluster0_opp>; 98 }; 99 100 L3_CA55: cache-controller-0 { 101 compatible = "cache"; 102 cache-unified; 103 cache-size = <0x100000>; 104 cache-level = <3>; 105 }; 106 }; 107 108 psci { 109 compatible = "arm,psci-1.0", "arm,psci-0.2"; 110 method = "smc"; 111 }; 112 113 qextal_clk: qextal-clk { 114 compatible = "fixed-clock"; 115 #clock-cells = <0>; 116 /* This value must be overridden by the board */ 117 clock-frequency = <0>; 118 }; 119 120 rtxin_clk: rtxin-clk { 121 compatible = "fixed-clock"; 122 #clock-cells = <0>; 123 /* This value must be overridden by the board */ 124 clock-frequency = <0>; 125 }; 126 127 soc: soc { 128 compatible = "simple-bus"; 129 interrupt-parent = <&gic>; 130 #address-cells = <2>; 131 #size-cells = <2>; 132 ranges; 133 134 icu: interrupt-controller@10400000 { 135 compatible = "renesas,r9a09g057-icu"; 136 reg = <0 0x10400000 0 0x10000>; 137 #interrupt-cells = <2>; 138 #address-cells = <0>; 139 interrupt-controller; 140 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, 190 <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, 191 <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 192 <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 193 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; 198 interrupt-names = "nmi", 199 "port_irq0", "port_irq1", "port_irq2", 200 "port_irq3", "port_irq4", "port_irq5", 201 "port_irq6", "port_irq7", "port_irq8", 202 "port_irq9", "port_irq10", "port_irq11", 203 "port_irq12", "port_irq13", "port_irq14", 204 "port_irq15", 205 "tint0", "tint1", "tint2", "tint3", 206 "tint4", "tint5", "tint6", "tint7", 207 "tint8", "tint9", "tint10", "tint11", 208 "tint12", "tint13", "tint14", "tint15", 209 "tint16", "tint17", "tint18", "tint19", 210 "tint20", "tint21", "tint22", "tint23", 211 "tint24", "tint25", "tint26", "tint27", 212 "tint28", "tint29", "tint30", "tint31", 213 "int-ca55-0", "int-ca55-1", 214 "int-ca55-2", "int-ca55-3", 215 "icu-error-ca55", 216 "gpt-u0-gtciada", "gpt-u0-gtciadb", 217 "gpt-u1-gtciada", "gpt-u1-gtciadb"; 218 clocks = <&cpg CPG_MOD 0x5>; 219 power-domains = <&cpg>; 220 resets = <&cpg 0x36>; 221 }; 222 223 pinctrl: pinctrl@10410000 { 224 compatible = "renesas,r9a09g057-pinctrl"; 225 reg = <0 0x10410000 0 0x10000>; 226 clocks = <&cpg CPG_CORE R9A09G057_IOTOP_0_SHCLK>; 227 gpio-controller; 228 #gpio-cells = <2>; 229 gpio-ranges = <&pinctrl 0 0 96>; 230 #interrupt-cells = <2>; 231 interrupt-controller; 232 interrupt-parent = <&icu>; 233 power-domains = <&cpg>; 234 resets = <&cpg 0xa5>, <&cpg 0xa6>; 235 }; 236 237 cpg: clock-controller@10420000 { 238 compatible = "renesas,r9a09g057-cpg"; 239 reg = <0 0x10420000 0 0x10000>; 240 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; 241 clock-names = "audio_extal", "rtxin", "qextal"; 242 #clock-cells = <2>; 243 #reset-cells = <1>; 244 #power-domain-cells = <0>; 245 }; 246 247 sys: system-controller@10430000 { 248 compatible = "renesas,r9a09g057-sys"; 249 reg = <0 0x10430000 0 0x10000>; 250 clocks = <&cpg CPG_CORE R9A09G057_SYS_0_PCLK>; 251 resets = <&cpg 0x30>; 252 status = "disabled"; 253 }; 254 255 ostm0: timer@11800000 { 256 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 257 reg = <0x0 0x11800000 0x0 0x1000>; 258 interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>; 259 clocks = <&cpg CPG_MOD 0x43>; 260 resets = <&cpg 0x6d>; 261 power-domains = <&cpg>; 262 status = "disabled"; 263 }; 264 265 ostm1: timer@11801000 { 266 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 267 reg = <0x0 0x11801000 0x0 0x1000>; 268 interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>; 269 clocks = <&cpg CPG_MOD 0x44>; 270 resets = <&cpg 0x6e>; 271 power-domains = <&cpg>; 272 status = "disabled"; 273 }; 274 275 ostm2: timer@14000000 { 276 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 277 reg = <0x0 0x14000000 0x0 0x1000>; 278 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>; 279 clocks = <&cpg CPG_MOD 0x45>; 280 resets = <&cpg 0x6f>; 281 power-domains = <&cpg>; 282 status = "disabled"; 283 }; 284 285 ostm3: timer@14001000 { 286 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 287 reg = <0x0 0x14001000 0x0 0x1000>; 288 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>; 289 clocks = <&cpg CPG_MOD 0x46>; 290 resets = <&cpg 0x70>; 291 power-domains = <&cpg>; 292 status = "disabled"; 293 }; 294 295 ostm4: timer@12c00000 { 296 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 297 reg = <0x0 0x12c00000 0x0 0x1000>; 298 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 299 clocks = <&cpg CPG_MOD 0x47>; 300 resets = <&cpg 0x71>; 301 power-domains = <&cpg>; 302 status = "disabled"; 303 }; 304 305 ostm5: timer@12c01000 { 306 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 307 reg = <0x0 0x12c01000 0x0 0x1000>; 308 interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 309 clocks = <&cpg CPG_MOD 0x48>; 310 resets = <&cpg 0x72>; 311 power-domains = <&cpg>; 312 status = "disabled"; 313 }; 314 315 ostm6: timer@12c02000 { 316 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 317 reg = <0x0 0x12c02000 0x0 0x1000>; 318 interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; 319 clocks = <&cpg CPG_MOD 0x49>; 320 resets = <&cpg 0x73>; 321 power-domains = <&cpg>; 322 status = "disabled"; 323 }; 324 325 ostm7: timer@12c03000 { 326 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 327 reg = <0x0 0x12c03000 0x0 0x1000>; 328 interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>; 329 clocks = <&cpg CPG_MOD 0x4a>; 330 resets = <&cpg 0x74>; 331 power-domains = <&cpg>; 332 status = "disabled"; 333 }; 334 335 wdt0: watchdog@11c00400 { 336 compatible = "renesas,r9a09g057-wdt"; 337 reg = <0 0x11c00400 0 0x400>; 338 clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>; 339 clock-names = "pclk", "oscclk"; 340 resets = <&cpg 0x75>; 341 power-domains = <&cpg>; 342 status = "disabled"; 343 }; 344 345 wdt1: watchdog@14400000 { 346 compatible = "renesas,r9a09g057-wdt"; 347 reg = <0 0x14400000 0 0x400>; 348 clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; 349 clock-names = "pclk", "oscclk"; 350 resets = <&cpg 0x76>; 351 power-domains = <&cpg>; 352 status = "disabled"; 353 }; 354 355 wdt2: watchdog@13000000 { 356 compatible = "renesas,r9a09g057-wdt"; 357 reg = <0 0x13000000 0 0x400>; 358 clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>; 359 clock-names = "pclk", "oscclk"; 360 resets = <&cpg 0x77>; 361 power-domains = <&cpg>; 362 status = "disabled"; 363 }; 364 365 wdt3: watchdog@13000400 { 366 compatible = "renesas,r9a09g057-wdt"; 367 reg = <0 0x13000400 0 0x400>; 368 clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>; 369 clock-names = "pclk", "oscclk"; 370 resets = <&cpg 0x78>; 371 power-domains = <&cpg>; 372 status = "disabled"; 373 }; 374 375 scif: serial@11c01400 { 376 compatible = "renesas,scif-r9a09g057"; 377 reg = <0 0x11c01400 0 0x400>; 378 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, 386 <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; 387 interrupt-names = "eri", "rxi", "txi", "bri", "dri", 388 "tei", "tei-dri", "rxi-edge", "txi-edge"; 389 clocks = <&cpg CPG_MOD 0x8f>; 390 clock-names = "fck"; 391 power-domains = <&cpg>; 392 resets = <&cpg 0x95>; 393 status = "disabled"; 394 }; 395 396 i2c0: i2c@14400400 { 397 compatible = "renesas,riic-r9a09g057"; 398 reg = <0 0x14400400 0 0x400>; 399 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, 401 <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>, 402 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 405 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 407 interrupt-names = "tei", "ri", "ti", "spi", "sti", 408 "naki", "ali", "tmoi"; 409 clocks = <&cpg CPG_MOD 0x94>; 410 resets = <&cpg 0x98>; 411 power-domains = <&cpg>; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 status = "disabled"; 415 }; 416 417 i2c1: i2c@14400800 { 418 compatible = "renesas,riic-r9a09g057"; 419 reg = <0 0x14400800 0 0x400>; 420 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>, 422 <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, 423 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 428 interrupt-names = "tei", "ri", "ti", "spi", "sti", 429 "naki", "ali", "tmoi"; 430 clocks = <&cpg CPG_MOD 0x95>; 431 resets = <&cpg 0x99>; 432 power-domains = <&cpg>; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 status = "disabled"; 436 }; 437 438 i2c2: i2c@14400c00 { 439 compatible = "renesas,riic-r9a09g057"; 440 reg = <0 0x14400c00 0 0x400>; 441 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>, 443 <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>, 444 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 449 interrupt-names = "tei", "ri", "ti", "spi", "sti", 450 "naki", "ali", "tmoi"; 451 clocks = <&cpg CPG_MOD 0x96>; 452 resets = <&cpg 0x9a>; 453 power-domains = <&cpg>; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 status = "disabled"; 457 }; 458 459 i2c3: i2c@14401000 { 460 compatible = "renesas,riic-r9a09g057"; 461 reg = <0 0x14401000 0 0x400>; 462 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>, 464 <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>, 465 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 470 interrupt-names = "tei", "ri", "ti", "spi", "sti", 471 "naki", "ali", "tmoi"; 472 clocks = <&cpg CPG_MOD 0x97>; 473 resets = <&cpg 0x9b>; 474 power-domains = <&cpg>; 475 #address-cells = <1>; 476 #size-cells = <0>; 477 status = "disabled"; 478 }; 479 480 i2c4: i2c@14401400 { 481 compatible = "renesas,riic-r9a09g057"; 482 reg = <0 0x14401400 0 0x400>; 483 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>, 485 <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>, 486 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 491 interrupt-names = "tei", "ri", "ti", "spi", "sti", 492 "naki", "ali", "tmoi"; 493 clocks = <&cpg CPG_MOD 0x98>; 494 resets = <&cpg 0x9c>; 495 power-domains = <&cpg>; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 status = "disabled"; 499 }; 500 501 i2c5: i2c@14401800 { 502 compatible = "renesas,riic-r9a09g057"; 503 reg = <0 0x14401800 0 0x400>; 504 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>, 506 <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>, 507 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 512 interrupt-names = "tei", "ri", "ti", "spi", "sti", 513 "naki", "ali", "tmoi"; 514 clocks = <&cpg CPG_MOD 0x99>; 515 resets = <&cpg 0x9d>; 516 power-domains = <&cpg>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 status = "disabled"; 520 }; 521 522 i2c6: i2c@14401c00 { 523 compatible = "renesas,riic-r9a09g057"; 524 reg = <0 0x14401c00 0 0x400>; 525 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>, 527 <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, 528 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 533 interrupt-names = "tei", "ri", "ti", "spi", "sti", 534 "naki", "ali", "tmoi"; 535 clocks = <&cpg CPG_MOD 0x9a>; 536 resets = <&cpg 0x9e>; 537 power-domains = <&cpg>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 status = "disabled"; 541 }; 542 543 i2c7: i2c@14402000 { 544 compatible = "renesas,riic-r9a09g057"; 545 reg = <0 0x14402000 0 0x400>; 546 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>, 548 <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>, 549 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 554 interrupt-names = "tei", "ri", "ti", "spi", "sti", 555 "naki", "ali", "tmoi"; 556 clocks = <&cpg CPG_MOD 0x9b>; 557 resets = <&cpg 0x9f>; 558 power-domains = <&cpg>; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 status = "disabled"; 562 }; 563 564 i2c8: i2c@11c01000 { 565 compatible = "renesas,riic-r9a09g057"; 566 reg = <0 0x11c01000 0 0x400>; 567 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>, 569 <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>, 570 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 575 interrupt-names = "tei", "ri", "ti", "spi", "sti", 576 "naki", "ali", "tmoi"; 577 clocks = <&cpg CPG_MOD 0x93>; 578 resets = <&cpg 0xa0>; 579 power-domains = <&cpg>; 580 #address-cells = <1>; 581 #size-cells = <0>; 582 status = "disabled"; 583 }; 584 585 gic: interrupt-controller@14900000 { 586 compatible = "arm,gic-v3"; 587 reg = <0x0 0x14900000 0 0x20000>, 588 <0x0 0x14940000 0 0x80000>; 589 #interrupt-cells = <3>; 590 #address-cells = <0>; 591 interrupt-controller; 592 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 593 }; 594 595 sdhi0: mmc@15c00000 { 596 compatible = "renesas,sdhi-r9a09g057"; 597 reg = <0x0 0x15c00000 0 0x10000>; 598 interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>; 600 clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, 601 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; 602 clock-names = "core", "clkh", "cd", "aclk"; 603 resets = <&cpg 0xa7>; 604 power-domains = <&cpg>; 605 status = "disabled"; 606 }; 607 608 sdhi1: mmc@15c10000 { 609 compatible = "renesas,sdhi-r9a09g057"; 610 reg = <0x0 0x15c10000 0 0x10000>; 611 interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, 614 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; 615 clock-names = "core", "clkh", "cd", "aclk"; 616 resets = <&cpg 0xa8>; 617 power-domains = <&cpg>; 618 status = "disabled"; 619 }; 620 621 sdhi2: mmc@15c20000 { 622 compatible = "renesas,sdhi-r9a09g057"; 623 reg = <0x0 0x15c20000 0 0x10000>; 624 interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, 627 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; 628 clock-names = "core", "clkh", "cd", "aclk"; 629 resets = <&cpg 0xa9>; 630 power-domains = <&cpg>; 631 status = "disabled"; 632 }; 633 }; 634 635 timer { 636 compatible = "arm,armv8-timer"; 637 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 638 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 639 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 640 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 641 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 642 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 643 }; 644}; 645