1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G3E SoC 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g047-cpg.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "renesas,r9a09g047"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_extal_clk: audio-clk { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by the board */ 20 clock-frequency = <0>; 21 }; 22 23 /* 24 * The default cluster table is based on the assumption that the PLLCA55 clock 25 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to 26 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be 27 * clocked to 1.8GHz as well). The table below should be overridden in the board 28 * DTS based on the PLLCA55 clock frequency. 29 */ 30 cluster0_opp: opp-table-0 { 31 compatible = "operating-points-v2"; 32 33 opp-1700000000 { 34 opp-hz = /bits/ 64 <1700000000>; 35 opp-microvolt = <900000>; 36 clock-latency-ns = <300000>; 37 }; 38 opp-850000000 { 39 opp-hz = /bits/ 64 <850000000>; 40 opp-microvolt = <800000>; 41 clock-latency-ns = <300000>; 42 }; 43 opp-425000000 { 44 opp-hz = /bits/ 64 <425000000>; 45 opp-microvolt = <800000>; 46 clock-latency-ns = <300000>; 47 }; 48 opp-212500000 { 49 opp-hz = /bits/ 64 <212500000>; 50 opp-microvolt = <800000>; 51 clock-latency-ns = <300000>; 52 opp-suspend; 53 }; 54 }; 55 56 cpus { 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 cpu0: cpu@0 { 61 compatible = "arm,cortex-a55"; 62 reg = <0>; 63 device_type = "cpu"; 64 next-level-cache = <&L3_CA55>; 65 enable-method = "psci"; 66 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>; 67 operating-points-v2 = <&cluster0_opp>; 68 }; 69 70 cpu1: cpu@100 { 71 compatible = "arm,cortex-a55"; 72 reg = <0x100>; 73 device_type = "cpu"; 74 next-level-cache = <&L3_CA55>; 75 enable-method = "psci"; 76 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>; 77 operating-points-v2 = <&cluster0_opp>; 78 }; 79 80 cpu2: cpu@200 { 81 compatible = "arm,cortex-a55"; 82 reg = <0x200>; 83 device_type = "cpu"; 84 next-level-cache = <&L3_CA55>; 85 enable-method = "psci"; 86 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>; 87 operating-points-v2 = <&cluster0_opp>; 88 }; 89 90 cpu3: cpu@300 { 91 compatible = "arm,cortex-a55"; 92 reg = <0x300>; 93 device_type = "cpu"; 94 next-level-cache = <&L3_CA55>; 95 enable-method = "psci"; 96 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>; 97 operating-points-v2 = <&cluster0_opp>; 98 }; 99 100 L3_CA55: cache-controller-0 { 101 compatible = "cache"; 102 cache-unified; 103 cache-size = <0x100000>; 104 cache-level = <3>; 105 }; 106 }; 107 108 gpu_opp_table: opp-table-1 { 109 compatible = "operating-points-v2"; 110 111 opp-630000000 { 112 opp-hz = /bits/ 64 <630000000>; 113 opp-microvolt = <800000>; 114 }; 115 116 opp-315000000 { 117 opp-hz = /bits/ 64 <315000000>; 118 opp-microvolt = <800000>; 119 }; 120 121 opp-157500000 { 122 opp-hz = /bits/ 64 <157500000>; 123 opp-microvolt = <800000>; 124 }; 125 126 opp-78750000 { 127 opp-hz = /bits/ 64 <78750000>; 128 opp-microvolt = <800000>; 129 }; 130 131 opp-19687500 { 132 opp-hz = /bits/ 64 <19687500>; 133 opp-microvolt = <800000>; 134 }; 135 }; 136 137 psci { 138 compatible = "arm,psci-1.0", "arm,psci-0.2"; 139 method = "smc"; 140 }; 141 142 qextal_clk: qextal-clk { 143 compatible = "fixed-clock"; 144 #clock-cells = <0>; 145 /* This value must be overridden by the board */ 146 clock-frequency = <0>; 147 }; 148 149 rtxin_clk: rtxin-clk { 150 compatible = "fixed-clock"; 151 #clock-cells = <0>; 152 /* This value must be overridden by the board */ 153 clock-frequency = <0>; 154 }; 155 156 soc: soc { 157 compatible = "simple-bus"; 158 interrupt-parent = <&gic>; 159 #address-cells = <2>; 160 #size-cells = <2>; 161 ranges; 162 163 icu: interrupt-controller@10400000 { 164 compatible = "renesas,r9a09g047-icu"; 165 reg = <0 0x10400000 0 0x10000>; 166 #interrupt-cells = <2>; 167 #address-cells = <0>; 168 interrupt-controller; 169 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, 219 <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, 220 <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 221 <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 222 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; 227 interrupt-names = "nmi", 228 "port_irq0", "port_irq1", "port_irq2", 229 "port_irq3", "port_irq4", "port_irq5", 230 "port_irq6", "port_irq7", "port_irq8", 231 "port_irq9", "port_irq10", "port_irq11", 232 "port_irq12", "port_irq13", "port_irq14", 233 "port_irq15", 234 "tint0", "tint1", "tint2", "tint3", 235 "tint4", "tint5", "tint6", "tint7", 236 "tint8", "tint9", "tint10", "tint11", 237 "tint12", "tint13", "tint14", "tint15", 238 "tint16", "tint17", "tint18", "tint19", 239 "tint20", "tint21", "tint22", "tint23", 240 "tint24", "tint25", "tint26", "tint27", 241 "tint28", "tint29", "tint30", "tint31", 242 "int-ca55-0", "int-ca55-1", 243 "int-ca55-2", "int-ca55-3", 244 "icu-error-ca55", 245 "gpt-u0-gtciada", "gpt-u0-gtciadb", 246 "gpt-u1-gtciada", "gpt-u1-gtciadb"; 247 clocks = <&cpg CPG_MOD 0x5>; 248 power-domains = <&cpg>; 249 resets = <&cpg 0x36>; 250 }; 251 252 pinctrl: pinctrl@10410000 { 253 compatible = "renesas,r9a09g047-pinctrl"; 254 reg = <0 0x10410000 0 0x10000>; 255 clocks = <&cpg CPG_CORE R9A09G047_IOTOP_0_SHCLK>; 256 gpio-controller; 257 #gpio-cells = <2>; 258 gpio-ranges = <&pinctrl 0 0 232>; 259 #interrupt-cells = <2>; 260 interrupt-controller; 261 interrupt-parent = <&icu>; 262 power-domains = <&cpg>; 263 resets = <&cpg 0xa5>, <&cpg 0xa6>; 264 }; 265 266 cpg: clock-controller@10420000 { 267 compatible = "renesas,r9a09g047-cpg"; 268 reg = <0 0x10420000 0 0x10000>; 269 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; 270 clock-names = "audio_extal", "rtxin", "qextal"; 271 #clock-cells = <2>; 272 #reset-cells = <1>; 273 #power-domain-cells = <0>; 274 }; 275 276 sys: system-controller@10430000 { 277 compatible = "renesas,r9a09g047-sys"; 278 reg = <0 0x10430000 0 0x10000>; 279 clocks = <&cpg CPG_CORE R9A09G047_SYS_0_PCLK>; 280 resets = <&cpg 0x30>; 281 }; 282 283 xspi: spi@11030000 { 284 compatible = "renesas,r9a09g047-xspi"; 285 reg = <0 0x11030000 0 0x10000>, 286 <0 0x20000000 0 0x10000000>; 287 reg-names = "regs", "dirmap"; 288 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, 289 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>; 290 interrupt-names = "pulse", "err_pulse"; 291 clocks = <&cpg CPG_MOD 0x9f>, 292 <&cpg CPG_MOD 0xa0>, 293 <&cpg CPG_CORE R9A09G047_SPI_CLK_SPI>, 294 <&cpg CPG_MOD 0xa1>; 295 clock-names = "ahb", "axi", "spi", "spix2"; 296 resets = <&cpg 0xa3>, <&cpg 0xa4>; 297 reset-names = "hresetn", "aresetn"; 298 power-domains = <&cpg>; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 status = "disabled"; 302 }; 303 304 scif0: serial@11c01400 { 305 compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057"; 306 reg = <0 0x11c01400 0 0x400>; 307 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, 315 <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; 316 interrupt-names = "eri", "rxi", "txi", "bri", "dri", 317 "tei", "tei-dri", "rxi-edge", "txi-edge"; 318 clocks = <&cpg CPG_MOD 0x8f>; 319 clock-names = "fck"; 320 power-domains = <&cpg>; 321 resets = <&cpg 0x95>; 322 status = "disabled"; 323 }; 324 325 canfd: can@12440000 { 326 compatible = "renesas,r9a09g047-canfd"; 327 reg = <0 0x12440000 0 0x40000>; 328 interrupts = <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 698 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 705 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>; 348 interrupt-names = "g_err", "g_recc", 349 "ch0_err", "ch0_rec", "ch0_trx", 350 "ch1_err", "ch1_rec", "ch1_trx", 351 "ch2_err", "ch2_rec", "ch2_trx", 352 "ch3_err", "ch3_rec", "ch3_trx", 353 "ch4_err", "ch4_rec", "ch4_trx", 354 "ch5_err", "ch5_rec", "ch5_trx"; 355 clocks = <&cpg CPG_MOD 0x9c>, <&cpg CPG_MOD 0x9d>, 356 <&cpg CPG_MOD 0x9e>; 357 clock-names = "fck", "ram_clk", "can_clk"; 358 assigned-clocks = <&cpg CPG_MOD 0x9e>; 359 assigned-clock-rates = <80000000>; 360 resets = <&cpg 0xa1>, <&cpg 0xa2>; 361 reset-names = "rstp_n", "rstc_n"; 362 power-domains = <&cpg>; 363 status = "disabled"; 364 365 channel0 { 366 status = "disabled"; 367 }; 368 channel1 { 369 status = "disabled"; 370 }; 371 channel2 { 372 status = "disabled"; 373 }; 374 channel3 { 375 status = "disabled"; 376 }; 377 channel4 { 378 status = "disabled"; 379 }; 380 channel5 { 381 status = "disabled"; 382 }; 383 }; 384 385 wdt1: watchdog@14400000 { 386 compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; 387 reg = <0 0x14400000 0 0x400>; 388 clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; 389 clock-names = "pclk", "oscclk"; 390 resets = <&cpg 0x76>; 391 power-domains = <&cpg>; 392 status = "disabled"; 393 }; 394 395 wdt2: watchdog@13000000 { 396 compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; 397 reg = <0 0x13000000 0 0x400>; 398 clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>; 399 clock-names = "pclk", "oscclk"; 400 resets = <&cpg 0x77>; 401 power-domains = <&cpg>; 402 status = "disabled"; 403 }; 404 405 wdt3: watchdog@13000400 { 406 compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; 407 reg = <0 0x13000400 0 0x400>; 408 clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>; 409 clock-names = "pclk", "oscclk"; 410 resets = <&cpg 0x78>; 411 power-domains = <&cpg>; 412 status = "disabled"; 413 }; 414 415 i2c0: i2c@14400400 { 416 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 417 reg = <0 0x14400400 0 0x400>; 418 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, 420 <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>, 421 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 426 interrupt-names = "tei", "ri", "ti", "spi", "sti", 427 "naki", "ali", "tmoi"; 428 clocks = <&cpg CPG_MOD 0x94>; 429 resets = <&cpg 0x98>; 430 power-domains = <&cpg>; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 status = "disabled"; 434 }; 435 436 i2c1: i2c@14400800 { 437 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 438 reg = <0 0x14400800 0 0x400>; 439 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>, 441 <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, 442 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 447 interrupt-names = "tei", "ri", "ti", "spi", "sti", 448 "naki", "ali", "tmoi"; 449 clocks = <&cpg CPG_MOD 0x95>; 450 resets = <&cpg 0x99>; 451 power-domains = <&cpg>; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 status = "disabled"; 455 }; 456 457 i2c2: i2c@14400c00 { 458 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 459 reg = <0 0x14400c00 0 0x400>; 460 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>, 462 <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>, 463 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 468 interrupt-names = "tei", "ri", "ti", "spi", "sti", 469 "naki", "ali", "tmoi"; 470 clocks = <&cpg CPG_MOD 0x96>; 471 resets = <&cpg 0x9a>; 472 power-domains = <&cpg>; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 status = "disabled"; 476 }; 477 478 i2c3: i2c@14401000 { 479 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 480 reg = <0 0x14401000 0 0x400>; 481 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>, 483 <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>, 484 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 489 interrupt-names = "tei", "ri", "ti", "spi", "sti", 490 "naki", "ali", "tmoi"; 491 clocks = <&cpg CPG_MOD 0x97>; 492 resets = <&cpg 0x9b>; 493 power-domains = <&cpg>; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 status = "disabled"; 497 }; 498 499 i2c4: i2c@14401400 { 500 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 501 reg = <0 0x14401400 0 0x400>; 502 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>, 504 <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>, 505 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 510 interrupt-names = "tei", "ri", "ti", "spi", "sti", 511 "naki", "ali", "tmoi"; 512 clocks = <&cpg CPG_MOD 0x98>; 513 resets = <&cpg 0x9c>; 514 power-domains = <&cpg>; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 status = "disabled"; 518 }; 519 520 i2c5: i2c@14401800 { 521 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 522 reg = <0 0x14401800 0 0x400>; 523 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>, 525 <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>, 526 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 531 interrupt-names = "tei", "ri", "ti", "spi", "sti", 532 "naki", "ali", "tmoi"; 533 clocks = <&cpg CPG_MOD 0x99>; 534 resets = <&cpg 0x9d>; 535 power-domains = <&cpg>; 536 #address-cells = <1>; 537 #size-cells = <0>; 538 status = "disabled"; 539 }; 540 541 i2c6: i2c@14401c00 { 542 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 543 reg = <0 0x14401c00 0 0x400>; 544 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>, 546 <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, 547 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 552 interrupt-names = "tei", "ri", "ti", "spi", "sti", 553 "naki", "ali", "tmoi"; 554 clocks = <&cpg CPG_MOD 0x9a>; 555 resets = <&cpg 0x9e>; 556 power-domains = <&cpg>; 557 #address-cells = <1>; 558 #size-cells = <0>; 559 status = "disabled"; 560 }; 561 562 i2c7: i2c@14402000 { 563 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 564 reg = <0 0x14402000 0 0x400>; 565 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>, 567 <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>, 568 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 573 interrupt-names = "tei", "ri", "ti", "spi", "sti", 574 "naki", "ali", "tmoi"; 575 clocks = <&cpg CPG_MOD 0x9b>; 576 resets = <&cpg 0x9f>; 577 power-domains = <&cpg>; 578 #address-cells = <1>; 579 #size-cells = <0>; 580 status = "disabled"; 581 }; 582 583 i2c8: i2c@11c01000 { 584 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 585 reg = <0 0x11c01000 0 0x400>; 586 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>, 588 <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>, 589 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 594 interrupt-names = "tei", "ri", "ti", "spi", "sti", 595 "naki", "ali", "tmoi"; 596 clocks = <&cpg CPG_MOD 0x93>; 597 resets = <&cpg 0xa0>; 598 power-domains = <&cpg>; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 status = "disabled"; 602 }; 603 604 gpu: gpu@14850000 { 605 compatible = "renesas,r9a09g047-mali", 606 "arm,mali-bifrost"; 607 reg = <0x0 0x14850000 0x0 0x10000>; 608 interrupts = <GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>; 612 interrupt-names = "job", "mmu", "gpu", "event"; 613 clocks = <&cpg CPG_MOD 0xf0>, 614 <&cpg CPG_MOD 0xf1>, 615 <&cpg CPG_MOD 0xf2>; 616 clock-names = "gpu", "bus", "bus_ace"; 617 power-domains = <&cpg>; 618 resets = <&cpg 0xdd>, <&cpg 0xde>, <&cpg 0xdf>; 619 reset-names = "rst", "axi_rst", "ace_rst"; 620 operating-points-v2 = <&gpu_opp_table>; 621 status = "disabled"; 622 }; 623 624 gic: interrupt-controller@14900000 { 625 compatible = "arm,gic-v3"; 626 reg = <0x0 0x14900000 0 0x20000>, 627 <0x0 0x14940000 0 0x80000>; 628 #interrupt-cells = <3>; 629 #address-cells = <0>; 630 interrupt-controller; 631 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 632 }; 633 634 sdhi0: mmc@15c00000 { 635 compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; 636 reg = <0x0 0x15c00000 0 0x10000>; 637 interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>; 639 clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, 640 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; 641 clock-names = "core", "clkh", "cd", "aclk"; 642 resets = <&cpg 0xa7>; 643 power-domains = <&cpg>; 644 status = "disabled"; 645 646 sdhi0_vqmmc: vqmmc-regulator { 647 regulator-name = "SDHI0-VQMMC"; 648 regulator-min-microvolt = <1800000>; 649 regulator-max-microvolt = <3300000>; 650 status = "disabled"; 651 }; 652 }; 653 654 sdhi1: mmc@15c10000 { 655 compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; 656 reg = <0x0 0x15c10000 0 0x10000>; 657 interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 659 clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, 660 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; 661 clock-names = "core", "clkh", "cd", "aclk"; 662 resets = <&cpg 0xa8>; 663 power-domains = <&cpg>; 664 status = "disabled"; 665 666 sdhi1_vqmmc: vqmmc-regulator { 667 regulator-name = "SDHI1-VQMMC"; 668 regulator-min-microvolt = <1800000>; 669 regulator-max-microvolt = <3300000>; 670 status = "disabled"; 671 }; 672 }; 673 674 sdhi2: mmc@15c20000 { 675 compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; 676 reg = <0x0 0x15c20000 0 0x10000>; 677 interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>; 679 clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, 680 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; 681 clock-names = "core", "clkh", "cd", "aclk"; 682 resets = <&cpg 0xa9>; 683 power-domains = <&cpg>; 684 status = "disabled"; 685 686 sdhi2_vqmmc: vqmmc-regulator { 687 regulator-name = "SDHI2-VQMMC"; 688 regulator-min-microvolt = <1800000>; 689 regulator-max-microvolt = <3300000>; 690 status = "disabled"; 691 }; 692 }; 693 694 eth0: ethernet@15c30000 { 695 compatible = "renesas,r9a09g047-gbeth", "renesas,rzv2h-gbeth", 696 "snps,dwmac-5.20"; 697 reg = <0 0x15c30000 0 0x10000>; 698 clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, 699 <&cpg CPG_CORE R9A09G047_GBETH_0_CLK_PTP_REF_I>, 700 <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, 701 <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; 702 clock-names = "stmmaceth", "pclk", "ptp_ref", 703 "tx", "rx", "tx-180", "rx-180"; 704 interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>; 715 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 716 "rx-queue-0", "rx-queue-1", "rx-queue-2", 717 "rx-queue-3", "tx-queue-0", "tx-queue-1", 718 "tx-queue-2", "tx-queue-3"; 719 resets = <&cpg 0xb0>; 720 power-domains = <&cpg>; 721 snps,multicast-filter-bins = <256>; 722 snps,perfect-filter-entries = <128>; 723 rx-fifo-depth = <8192>; 724 tx-fifo-depth = <8192>; 725 snps,fixed-burst; 726 snps,no-pbl-x8; 727 snps,force_thresh_dma_mode; 728 snps,axi-config = <&stmmac_axi_setup>; 729 snps,mtl-rx-config = <&mtl_rx_setup0>; 730 snps,mtl-tx-config = <&mtl_tx_setup0>; 731 snps,txpbl = <32>; 732 snps,rxpbl = <32>; 733 status = "disabled"; 734 735 mdio0: mdio { 736 compatible = "snps,dwmac-mdio"; 737 #address-cells = <1>; 738 #size-cells = <0>; 739 }; 740 741 mtl_rx_setup0: rx-queues-config { 742 snps,rx-queues-to-use = <4>; 743 snps,rx-sched-sp; 744 745 queue0 { 746 snps,dcb-algorithm; 747 snps,priority = <0x1>; 748 snps,map-to-dma-channel = <0>; 749 }; 750 751 queue1 { 752 snps,dcb-algorithm; 753 snps,priority = <0x2>; 754 snps,map-to-dma-channel = <1>; 755 }; 756 757 queue2 { 758 snps,dcb-algorithm; 759 snps,priority = <0x4>; 760 snps,map-to-dma-channel = <2>; 761 }; 762 763 queue3 { 764 snps,dcb-algorithm; 765 snps,priority = <0x8>; 766 snps,map-to-dma-channel = <3>; 767 }; 768 }; 769 770 mtl_tx_setup0: tx-queues-config { 771 snps,tx-queues-to-use = <4>; 772 773 queue0 { 774 snps,dcb-algorithm; 775 snps,priority = <0x1>; 776 }; 777 778 queue1 { 779 snps,dcb-algorithm; 780 snps,priority = <0x2>; 781 }; 782 783 queue2 { 784 snps,dcb-algorithm; 785 snps,priority = <0x4>; 786 }; 787 788 queue3 { 789 snps,dcb-algorithm; 790 snps,priority = <0x8>; 791 }; 792 }; 793 }; 794 795 eth1: ethernet@15c40000 { 796 compatible = "renesas,r9a09g047-gbeth", "renesas,rzv2h-gbeth", 797 "snps,dwmac-5.20"; 798 reg = <0 0x15c40000 0 0x10000>; 799 clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, 800 <&cpg CPG_CORE R9A09G047_GBETH_1_CLK_PTP_REF_I>, 801 <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, 802 <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; 803 clock-names = "stmmaceth", "pclk", "ptp_ref", 804 "tx", "rx", "tx-180", "rx-180"; 805 interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>; 816 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 817 "rx-queue-0", "rx-queue-1", "rx-queue-2", 818 "rx-queue-3", "tx-queue-0", "tx-queue-1", 819 "tx-queue-2", "tx-queue-3"; 820 resets = <&cpg 0xb1>; 821 power-domains = <&cpg>; 822 snps,multicast-filter-bins = <256>; 823 snps,perfect-filter-entries = <128>; 824 rx-fifo-depth = <8192>; 825 tx-fifo-depth = <8192>; 826 snps,fixed-burst; 827 snps,no-pbl-x8; 828 snps,force_thresh_dma_mode; 829 snps,axi-config = <&stmmac_axi_setup>; 830 snps,mtl-rx-config = <&mtl_rx_setup1>; 831 snps,mtl-tx-config = <&mtl_tx_setup1>; 832 snps,txpbl = <32>; 833 snps,rxpbl = <32>; 834 status = "disabled"; 835 836 mdio1: mdio { 837 compatible = "snps,dwmac-mdio"; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 }; 841 842 mtl_rx_setup1: rx-queues-config { 843 snps,rx-queues-to-use = <4>; 844 snps,rx-sched-sp; 845 846 queue0 { 847 snps,dcb-algorithm; 848 snps,priority = <0x1>; 849 snps,map-to-dma-channel = <0>; 850 }; 851 852 queue1 { 853 snps,dcb-algorithm; 854 snps,priority = <0x2>; 855 snps,map-to-dma-channel = <1>; 856 }; 857 858 queue2 { 859 snps,dcb-algorithm; 860 snps,priority = <0x4>; 861 snps,map-to-dma-channel = <2>; 862 }; 863 864 queue3 { 865 snps,dcb-algorithm; 866 snps,priority = <0x8>; 867 snps,map-to-dma-channel = <3>; 868 }; 869 }; 870 871 mtl_tx_setup1: tx-queues-config { 872 snps,tx-queues-to-use = <4>; 873 874 queue0 { 875 snps,dcb-algorithm; 876 snps,priority = <0x1>; 877 }; 878 879 queue1 { 880 snps,dcb-algorithm; 881 snps,priority = <0x2>; 882 }; 883 884 queue2 { 885 snps,dcb-algorithm; 886 snps,priority = <0x4>; 887 }; 888 889 queue3 { 890 snps,dcb-algorithm; 891 snps,priority = <0x8>; 892 }; 893 }; 894 }; 895 896 cru: video@16000000 { 897 compatible = "renesas,r9a09g047-cru"; 898 reg = <0 0x16000000 0 0x400>; 899 clocks = <&cpg CPG_MOD 0xd3>, 900 <&cpg CPG_MOD 0xd4>, 901 <&cpg CPG_MOD 0xd2>; 902 clock-names = "video", "apb", "axi"; 903 interrupts = <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 840 IRQ_TYPE_EDGE_RISING>, 906 <GIC_SPI 841 IRQ_TYPE_EDGE_RISING>, 907 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>; 908 interrupt-names = "image_conv", "axi_mst_err", 909 "vd_addr_wend", "sd_addr_wend", 910 "vsd_addr_wend"; 911 resets = <&cpg 0xc5>, <&cpg 0xc6>; 912 reset-names = "presetn", "aresetn"; 913 power-domains = <&cpg>; 914 status = "disabled"; 915 916 ports { 917 #address-cells = <1>; 918 #size-cells = <0>; 919 920 port@1 { 921 #address-cells = <1>; 922 #size-cells = <0>; 923 924 reg = <1>; 925 crucsi2: endpoint@0 { 926 reg = <0>; 927 remote-endpoint = <&csi2cru>; 928 }; 929 }; 930 }; 931 }; 932 933 csi2: csi2@16000400 { 934 compatible = "renesas,r9a09g047-csi2", "renesas,r9a09g057-csi2"; 935 reg = <0 0x16000400 0 0xc00>; 936 interrupts = <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>; 937 clocks = <&cpg CPG_MOD 0xd3>, <&cpg CPG_MOD 0xd4>; 938 clock-names = "video", "apb"; 939 resets = <&cpg 0xc5>, <&cpg 0xc7>; 940 reset-names = "presetn", "cmn-rstb"; 941 power-domains = <&cpg>; 942 status = "disabled"; 943 944 ports { 945 #address-cells = <1>; 946 #size-cells = <0>; 947 948 port@0 { 949 reg = <0>; 950 }; 951 952 port@1 { 953 #address-cells = <1>; 954 #size-cells = <0>; 955 reg = <1>; 956 957 csi2cru: endpoint@0 { 958 reg = <0>; 959 remote-endpoint = <&crucsi2>; 960 }; 961 }; 962 }; 963 }; 964 }; 965 966 stmmac_axi_setup: stmmac-axi-config { 967 snps,lpi_en; 968 snps,wr_osr_lmt = <0xf>; 969 snps,rd_osr_lmt = <0xf>; 970 snps,blen = <16 8 4 0 0 0 0>; 971 }; 972 973 timer { 974 compatible = "arm,armv8-timer"; 975 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 976 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 977 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 978 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 979 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 980 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 981 }; 982}; 983