1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G3E SoC 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g047-cpg.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "renesas,r9a09g047"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_extal_clk: audio-clk { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by the board */ 20 clock-frequency = <0>; 21 }; 22 23 /* 24 * The default cluster table is based on the assumption that the PLLCA55 clock 25 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to 26 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be 27 * clocked to 1.8GHz as well). The table below should be overridden in the board 28 * DTS based on the PLLCA55 clock frequency. 29 */ 30 cluster0_opp: opp-table-0 { 31 compatible = "operating-points-v2"; 32 33 opp-1700000000 { 34 opp-hz = /bits/ 64 <1700000000>; 35 opp-microvolt = <900000>; 36 clock-latency-ns = <300000>; 37 }; 38 opp-850000000 { 39 opp-hz = /bits/ 64 <850000000>; 40 opp-microvolt = <800000>; 41 clock-latency-ns = <300000>; 42 }; 43 opp-425000000 { 44 opp-hz = /bits/ 64 <425000000>; 45 opp-microvolt = <800000>; 46 clock-latency-ns = <300000>; 47 }; 48 opp-212500000 { 49 opp-hz = /bits/ 64 <212500000>; 50 opp-microvolt = <800000>; 51 clock-latency-ns = <300000>; 52 opp-suspend; 53 }; 54 }; 55 56 cpus { 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 cpu0: cpu@0 { 61 compatible = "arm,cortex-a55"; 62 reg = <0>; 63 device_type = "cpu"; 64 next-level-cache = <&L3_CA55>; 65 enable-method = "psci"; 66 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>; 67 operating-points-v2 = <&cluster0_opp>; 68 }; 69 70 cpu1: cpu@100 { 71 compatible = "arm,cortex-a55"; 72 reg = <0x100>; 73 device_type = "cpu"; 74 next-level-cache = <&L3_CA55>; 75 enable-method = "psci"; 76 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>; 77 operating-points-v2 = <&cluster0_opp>; 78 }; 79 80 cpu2: cpu@200 { 81 compatible = "arm,cortex-a55"; 82 reg = <0x200>; 83 device_type = "cpu"; 84 next-level-cache = <&L3_CA55>; 85 enable-method = "psci"; 86 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>; 87 operating-points-v2 = <&cluster0_opp>; 88 }; 89 90 cpu3: cpu@300 { 91 compatible = "arm,cortex-a55"; 92 reg = <0x300>; 93 device_type = "cpu"; 94 next-level-cache = <&L3_CA55>; 95 enable-method = "psci"; 96 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>; 97 operating-points-v2 = <&cluster0_opp>; 98 }; 99 100 L3_CA55: cache-controller-0 { 101 compatible = "cache"; 102 cache-unified; 103 cache-size = <0x100000>; 104 cache-level = <3>; 105 }; 106 }; 107 108 gpu_opp_table: opp-table-1 { 109 compatible = "operating-points-v2"; 110 111 opp-630000000 { 112 opp-hz = /bits/ 64 <630000000>; 113 opp-microvolt = <800000>; 114 }; 115 116 opp-315000000 { 117 opp-hz = /bits/ 64 <315000000>; 118 opp-microvolt = <800000>; 119 }; 120 121 opp-157500000 { 122 opp-hz = /bits/ 64 <157500000>; 123 opp-microvolt = <800000>; 124 }; 125 126 opp-78750000 { 127 opp-hz = /bits/ 64 <78750000>; 128 opp-microvolt = <800000>; 129 }; 130 131 opp-19687500 { 132 opp-hz = /bits/ 64 <19687500>; 133 opp-microvolt = <800000>; 134 }; 135 }; 136 137 psci { 138 compatible = "arm,psci-1.0", "arm,psci-0.2"; 139 method = "smc"; 140 }; 141 142 qextal_clk: qextal-clk { 143 compatible = "fixed-clock"; 144 #clock-cells = <0>; 145 /* This value must be overridden by the board */ 146 clock-frequency = <0>; 147 }; 148 149 rtxin_clk: rtxin-clk { 150 compatible = "fixed-clock"; 151 #clock-cells = <0>; 152 /* This value must be overridden by the board */ 153 clock-frequency = <0>; 154 }; 155 156 soc: soc { 157 compatible = "simple-bus"; 158 interrupt-parent = <&gic>; 159 #address-cells = <2>; 160 #size-cells = <2>; 161 ranges; 162 163 icu: interrupt-controller@10400000 { 164 compatible = "renesas,r9a09g047-icu"; 165 reg = <0 0x10400000 0 0x10000>; 166 #interrupt-cells = <2>; 167 #address-cells = <0>; 168 interrupt-controller; 169 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, 219 <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, 220 <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 221 <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 222 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; 227 interrupt-names = "nmi", 228 "port_irq0", "port_irq1", "port_irq2", 229 "port_irq3", "port_irq4", "port_irq5", 230 "port_irq6", "port_irq7", "port_irq8", 231 "port_irq9", "port_irq10", "port_irq11", 232 "port_irq12", "port_irq13", "port_irq14", 233 "port_irq15", 234 "tint0", "tint1", "tint2", "tint3", 235 "tint4", "tint5", "tint6", "tint7", 236 "tint8", "tint9", "tint10", "tint11", 237 "tint12", "tint13", "tint14", "tint15", 238 "tint16", "tint17", "tint18", "tint19", 239 "tint20", "tint21", "tint22", "tint23", 240 "tint24", "tint25", "tint26", "tint27", 241 "tint28", "tint29", "tint30", "tint31", 242 "int-ca55-0", "int-ca55-1", 243 "int-ca55-2", "int-ca55-3", 244 "icu-error-ca55", 245 "gpt-u0-gtciada", "gpt-u0-gtciadb", 246 "gpt-u1-gtciada", "gpt-u1-gtciadb"; 247 clocks = <&cpg CPG_MOD 0x5>; 248 power-domains = <&cpg>; 249 resets = <&cpg 0x36>; 250 }; 251 252 pinctrl: pinctrl@10410000 { 253 compatible = "renesas,r9a09g047-pinctrl"; 254 reg = <0 0x10410000 0 0x10000>; 255 clocks = <&cpg CPG_CORE R9A09G047_IOTOP_0_SHCLK>; 256 gpio-controller; 257 #gpio-cells = <2>; 258 gpio-ranges = <&pinctrl 0 0 232>; 259 #interrupt-cells = <2>; 260 interrupt-controller; 261 interrupt-parent = <&icu>; 262 power-domains = <&cpg>; 263 resets = <&cpg 0xa5>, <&cpg 0xa6>; 264 }; 265 266 cpg: clock-controller@10420000 { 267 compatible = "renesas,r9a09g047-cpg"; 268 reg = <0 0x10420000 0 0x10000>; 269 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; 270 clock-names = "audio_extal", "rtxin", "qextal"; 271 #clock-cells = <2>; 272 #reset-cells = <1>; 273 #power-domain-cells = <0>; 274 }; 275 276 sys: system-controller@10430000 { 277 compatible = "renesas,r9a09g047-sys"; 278 reg = <0 0x10430000 0 0x10000>; 279 clocks = <&cpg CPG_CORE R9A09G047_SYS_0_PCLK>; 280 resets = <&cpg 0x30>; 281 }; 282 283 xspi: spi@11030000 { 284 compatible = "renesas,r9a09g047-xspi"; 285 reg = <0 0x11030000 0 0x10000>, 286 <0 0x20000000 0 0x10000000>; 287 reg-names = "regs", "dirmap"; 288 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, 289 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>; 290 interrupt-names = "pulse", "err_pulse"; 291 clocks = <&cpg CPG_MOD 0x9f>, 292 <&cpg CPG_MOD 0xa0>, 293 <&cpg CPG_CORE R9A09G047_SPI_CLK_SPI>, 294 <&cpg CPG_MOD 0xa1>; 295 clock-names = "ahb", "axi", "spi", "spix2"; 296 resets = <&cpg 0xa3>, <&cpg 0xa4>; 297 reset-names = "hresetn", "aresetn"; 298 power-domains = <&cpg>; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 status = "disabled"; 302 }; 303 304 dmac0: dma-controller@11400000 { 305 compatible = "renesas,r9a09g047-dmac", 306 "renesas,r9a09g057-dmac"; 307 reg = <0 0x11400000 0 0x10000>; 308 interrupts = <GIC_SPI 499 IRQ_TYPE_EDGE_RISING>, 309 <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, 310 <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>, 311 <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>, 312 <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>, 313 <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>, 314 <GIC_SPI 94 IRQ_TYPE_EDGE_RISING>, 315 <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>, 316 <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>, 317 <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>, 318 <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>, 319 <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>, 320 <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, 321 <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>, 322 <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>, 323 <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>, 324 <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>; 325 interrupt-names = "error", 326 "ch0", "ch1", "ch2", "ch3", 327 "ch4", "ch5", "ch6", "ch7", 328 "ch8", "ch9", "ch10", "ch11", 329 "ch12", "ch13", "ch14", "ch15"; 330 clocks = <&cpg CPG_MOD 0x0>; 331 power-domains = <&cpg>; 332 resets = <&cpg 0x31>; 333 #dma-cells = <1>; 334 dma-channels = <16>; 335 renesas,icu = <&icu 4>; 336 }; 337 338 dmac1: dma-controller@14830000 { 339 compatible = "renesas,r9a09g047-dmac", 340 "renesas,r9a09g057-dmac"; 341 reg = <0 0x14830000 0 0x10000>; 342 interrupts = <GIC_SPI 495 IRQ_TYPE_EDGE_RISING>, 343 <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, 344 <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, 345 <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, 346 <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, 347 <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>, 348 <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 349 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, 350 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 351 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 352 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 353 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 354 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 355 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 356 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 357 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, 358 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>; 359 interrupt-names = "error", 360 "ch0", "ch1", "ch2", "ch3", 361 "ch4", "ch5", "ch6", "ch7", 362 "ch8", "ch9", "ch10", "ch11", 363 "ch12", "ch13", "ch14", "ch15"; 364 clocks = <&cpg CPG_MOD 0x1>; 365 power-domains = <&cpg>; 366 resets = <&cpg 0x32>; 367 #dma-cells = <1>; 368 dma-channels = <16>; 369 renesas,icu = <&icu 0>; 370 }; 371 372 dmac2: dma-controller@14840000 { 373 compatible = "renesas,r9a09g047-dmac", 374 "renesas,r9a09g057-dmac"; 375 reg = <0 0x14840000 0 0x10000>; 376 interrupts = <GIC_SPI 496 IRQ_TYPE_EDGE_RISING>, 377 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 378 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, 379 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, 380 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 381 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, 382 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, 383 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, 384 <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, 385 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, 386 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, 387 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 388 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 389 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, 390 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, 391 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 392 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>; 393 interrupt-names = "error", 394 "ch0", "ch1", "ch2", "ch3", 395 "ch4", "ch5", "ch6", "ch7", 396 "ch8", "ch9", "ch10", "ch11", 397 "ch12", "ch13", "ch14", "ch15"; 398 clocks = <&cpg CPG_MOD 0x2>; 399 power-domains = <&cpg>; 400 resets = <&cpg 0x33>; 401 #dma-cells = <1>; 402 dma-channels = <16>; 403 renesas,icu = <&icu 1>; 404 }; 405 406 dmac3: dma-controller@12000000 { 407 compatible = "renesas,r9a09g047-dmac", 408 "renesas,r9a09g057-dmac"; 409 reg = <0 0x12000000 0 0x10000>; 410 interrupts = <GIC_SPI 497 IRQ_TYPE_EDGE_RISING>, 411 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, 412 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, 413 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, 414 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, 415 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, 416 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, 417 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, 418 <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>, 419 <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>, 420 <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, 421 <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, 422 <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>, 423 <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>, 424 <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>, 425 <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>, 426 <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; 427 interrupt-names = "error", 428 "ch0", "ch1", "ch2", "ch3", 429 "ch4", "ch5", "ch6", "ch7", 430 "ch8", "ch9", "ch10", "ch11", 431 "ch12", "ch13", "ch14", "ch15"; 432 clocks = <&cpg CPG_MOD 0x3>; 433 power-domains = <&cpg>; 434 resets = <&cpg 0x34>; 435 #dma-cells = <1>; 436 dma-channels = <16>; 437 renesas,icu = <&icu 2>; 438 }; 439 440 dmac4: dma-controller@12010000 { 441 compatible = "renesas,r9a09g047-dmac", 442 "renesas,r9a09g057-dmac"; 443 reg = <0 0x12010000 0 0x10000>; 444 interrupts = <GIC_SPI 498 IRQ_TYPE_EDGE_RISING>, 445 <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, 446 <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, 447 <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, 448 <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, 449 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, 450 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 451 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 452 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 453 <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>, 454 <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>, 455 <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>, 456 <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>, 457 <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>, 458 <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>, 459 <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>, 460 <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 461 interrupt-names = "error", 462 "ch0", "ch1", "ch2", "ch3", 463 "ch4", "ch5", "ch6", "ch7", 464 "ch8", "ch9", "ch10", "ch11", 465 "ch12", "ch13", "ch14", "ch15"; 466 clocks = <&cpg CPG_MOD 0x4>; 467 power-domains = <&cpg>; 468 resets = <&cpg 0x35>; 469 #dma-cells = <1>; 470 dma-channels = <16>; 471 renesas,icu = <&icu 3>; 472 }; 473 474 scif0: serial@11c01400 { 475 compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057"; 476 reg = <0 0x11c01400 0 0x400>; 477 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, 485 <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; 486 interrupt-names = "eri", "rxi", "txi", "bri", "dri", 487 "tei", "tei-dri", "rxi-edge", "txi-edge"; 488 clocks = <&cpg CPG_MOD 0x8f>; 489 clock-names = "fck"; 490 power-domains = <&cpg>; 491 resets = <&cpg 0x95>; 492 status = "disabled"; 493 }; 494 495 i3c: i3c@12400000 { 496 compatible = "renesas,r9a09g047-i3c"; 497 reg = <0 0x12400000 0 0x10000>; 498 clocks = <&cpg CPG_MOD 0x91>, 499 <&cpg CPG_MOD 0x92>, 500 <&cpg CPG_MOD 0x90>; 501 clock-names = "pclk", "tclk", "pclkrw"; 502 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 677 IRQ_TYPE_EDGE_RISING>, 506 <GIC_SPI 678 IRQ_TYPE_EDGE_RISING>, 507 <GIC_SPI 679 IRQ_TYPE_EDGE_RISING>, 508 <GIC_SPI 680 IRQ_TYPE_EDGE_RISING>, 509 <GIC_SPI 681 IRQ_TYPE_EDGE_RISING>, 510 <GIC_SPI 682 IRQ_TYPE_EDGE_RISING>, 511 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 518 interrupt-names = "ierr", "terr", "abort", "resp", 519 "cmd", "ibi", "rx", "tx", "rcv", 520 "st", "sp", "tend", "nack", "al", 521 "tmo", "wu"; 522 resets = <&cpg 0x96>, <&cpg 0x97>; 523 reset-names = "presetn", "tresetn"; 524 power-domains = <&cpg>; 525 #address-cells = <3>; 526 #size-cells = <0>; 527 status = "disabled"; 528 }; 529 530 canfd: can@12440000 { 531 compatible = "renesas,r9a09g047-canfd"; 532 reg = <0 0x12440000 0 0x40000>; 533 interrupts = <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 698 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 705 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>; 553 interrupt-names = "g_err", "g_recc", 554 "ch0_err", "ch0_rec", "ch0_trx", 555 "ch1_err", "ch1_rec", "ch1_trx", 556 "ch2_err", "ch2_rec", "ch2_trx", 557 "ch3_err", "ch3_rec", "ch3_trx", 558 "ch4_err", "ch4_rec", "ch4_trx", 559 "ch5_err", "ch5_rec", "ch5_trx"; 560 clocks = <&cpg CPG_MOD 0x9c>, <&cpg CPG_MOD 0x9d>, 561 <&cpg CPG_MOD 0x9e>; 562 clock-names = "fck", "ram_clk", "can_clk"; 563 assigned-clocks = <&cpg CPG_MOD 0x9e>; 564 assigned-clock-rates = <80000000>; 565 resets = <&cpg 0xa1>, <&cpg 0xa2>; 566 reset-names = "rstp_n", "rstc_n"; 567 power-domains = <&cpg>; 568 status = "disabled"; 569 570 channel0 { 571 status = "disabled"; 572 }; 573 channel1 { 574 status = "disabled"; 575 }; 576 channel2 { 577 status = "disabled"; 578 }; 579 channel3 { 580 status = "disabled"; 581 }; 582 channel4 { 583 status = "disabled"; 584 }; 585 channel5 { 586 status = "disabled"; 587 }; 588 }; 589 590 wdt1: watchdog@14400000 { 591 compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; 592 reg = <0 0x14400000 0 0x400>; 593 clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; 594 clock-names = "pclk", "oscclk"; 595 resets = <&cpg 0x76>; 596 power-domains = <&cpg>; 597 status = "disabled"; 598 }; 599 600 wdt2: watchdog@13000000 { 601 compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; 602 reg = <0 0x13000000 0 0x400>; 603 clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>; 604 clock-names = "pclk", "oscclk"; 605 resets = <&cpg 0x77>; 606 power-domains = <&cpg>; 607 status = "disabled"; 608 }; 609 610 wdt3: watchdog@13000400 { 611 compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; 612 reg = <0 0x13000400 0 0x400>; 613 clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>; 614 clock-names = "pclk", "oscclk"; 615 resets = <&cpg 0x78>; 616 power-domains = <&cpg>; 617 status = "disabled"; 618 }; 619 620 i2c0: i2c@14400400 { 621 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 622 reg = <0 0x14400400 0 0x400>; 623 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, 625 <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>, 626 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 631 interrupt-names = "tei", "ri", "ti", "spi", "sti", 632 "naki", "ali", "tmoi"; 633 clocks = <&cpg CPG_MOD 0x94>; 634 resets = <&cpg 0x98>; 635 power-domains = <&cpg>; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 status = "disabled"; 639 }; 640 641 i2c1: i2c@14400800 { 642 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 643 reg = <0 0x14400800 0 0x400>; 644 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>, 646 <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, 647 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 652 interrupt-names = "tei", "ri", "ti", "spi", "sti", 653 "naki", "ali", "tmoi"; 654 clocks = <&cpg CPG_MOD 0x95>; 655 resets = <&cpg 0x99>; 656 power-domains = <&cpg>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 status = "disabled"; 660 }; 661 662 i2c2: i2c@14400c00 { 663 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 664 reg = <0 0x14400c00 0 0x400>; 665 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>, 667 <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>, 668 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 673 interrupt-names = "tei", "ri", "ti", "spi", "sti", 674 "naki", "ali", "tmoi"; 675 clocks = <&cpg CPG_MOD 0x96>; 676 resets = <&cpg 0x9a>; 677 power-domains = <&cpg>; 678 #address-cells = <1>; 679 #size-cells = <0>; 680 status = "disabled"; 681 }; 682 683 i2c3: i2c@14401000 { 684 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 685 reg = <0 0x14401000 0 0x400>; 686 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>, 688 <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>, 689 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 694 interrupt-names = "tei", "ri", "ti", "spi", "sti", 695 "naki", "ali", "tmoi"; 696 clocks = <&cpg CPG_MOD 0x97>; 697 resets = <&cpg 0x9b>; 698 power-domains = <&cpg>; 699 #address-cells = <1>; 700 #size-cells = <0>; 701 status = "disabled"; 702 }; 703 704 i2c4: i2c@14401400 { 705 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 706 reg = <0 0x14401400 0 0x400>; 707 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>, 709 <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>, 710 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 715 interrupt-names = "tei", "ri", "ti", "spi", "sti", 716 "naki", "ali", "tmoi"; 717 clocks = <&cpg CPG_MOD 0x98>; 718 resets = <&cpg 0x9c>; 719 power-domains = <&cpg>; 720 #address-cells = <1>; 721 #size-cells = <0>; 722 status = "disabled"; 723 }; 724 725 i2c5: i2c@14401800 { 726 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 727 reg = <0 0x14401800 0 0x400>; 728 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>, 730 <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>, 731 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 736 interrupt-names = "tei", "ri", "ti", "spi", "sti", 737 "naki", "ali", "tmoi"; 738 clocks = <&cpg CPG_MOD 0x99>; 739 resets = <&cpg 0x9d>; 740 power-domains = <&cpg>; 741 #address-cells = <1>; 742 #size-cells = <0>; 743 status = "disabled"; 744 }; 745 746 i2c6: i2c@14401c00 { 747 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 748 reg = <0 0x14401c00 0 0x400>; 749 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>, 751 <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, 752 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 757 interrupt-names = "tei", "ri", "ti", "spi", "sti", 758 "naki", "ali", "tmoi"; 759 clocks = <&cpg CPG_MOD 0x9a>; 760 resets = <&cpg 0x9e>; 761 power-domains = <&cpg>; 762 #address-cells = <1>; 763 #size-cells = <0>; 764 status = "disabled"; 765 }; 766 767 i2c7: i2c@14402000 { 768 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 769 reg = <0 0x14402000 0 0x400>; 770 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>, 772 <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>, 773 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 778 interrupt-names = "tei", "ri", "ti", "spi", "sti", 779 "naki", "ali", "tmoi"; 780 clocks = <&cpg CPG_MOD 0x9b>; 781 resets = <&cpg 0x9f>; 782 power-domains = <&cpg>; 783 #address-cells = <1>; 784 #size-cells = <0>; 785 status = "disabled"; 786 }; 787 788 i2c8: i2c@11c01000 { 789 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 790 reg = <0 0x11c01000 0 0x400>; 791 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>, 793 <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>, 794 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 799 interrupt-names = "tei", "ri", "ti", "spi", "sti", 800 "naki", "ali", "tmoi"; 801 clocks = <&cpg CPG_MOD 0x93>; 802 resets = <&cpg 0xa0>; 803 power-domains = <&cpg>; 804 #address-cells = <1>; 805 #size-cells = <0>; 806 status = "disabled"; 807 }; 808 809 gpu: gpu@14850000 { 810 compatible = "renesas,r9a09g047-mali", 811 "arm,mali-bifrost"; 812 reg = <0x0 0x14850000 0x0 0x10000>; 813 interrupts = <GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>; 817 interrupt-names = "job", "mmu", "gpu", "event"; 818 clocks = <&cpg CPG_MOD 0xf0>, 819 <&cpg CPG_MOD 0xf1>, 820 <&cpg CPG_MOD 0xf2>; 821 clock-names = "gpu", "bus", "bus_ace"; 822 power-domains = <&cpg>; 823 resets = <&cpg 0xdd>, <&cpg 0xde>, <&cpg 0xdf>; 824 reset-names = "rst", "axi_rst", "ace_rst"; 825 operating-points-v2 = <&gpu_opp_table>; 826 status = "disabled"; 827 }; 828 829 gic: interrupt-controller@14900000 { 830 compatible = "arm,gic-v3"; 831 reg = <0x0 0x14900000 0 0x20000>, 832 <0x0 0x14940000 0 0x80000>; 833 #interrupt-cells = <3>; 834 #address-cells = <0>; 835 interrupt-controller; 836 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 837 }; 838 839 sdhi0: mmc@15c00000 { 840 compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; 841 reg = <0x0 0x15c00000 0 0x10000>; 842 interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>; 844 clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, 845 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; 846 clock-names = "core", "clkh", "cd", "aclk"; 847 resets = <&cpg 0xa7>; 848 power-domains = <&cpg>; 849 status = "disabled"; 850 851 sdhi0_vqmmc: vqmmc-regulator { 852 regulator-name = "SDHI0-VQMMC"; 853 regulator-min-microvolt = <1800000>; 854 regulator-max-microvolt = <3300000>; 855 status = "disabled"; 856 }; 857 }; 858 859 sdhi1: mmc@15c10000 { 860 compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; 861 reg = <0x0 0x15c10000 0 0x10000>; 862 interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 864 clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, 865 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; 866 clock-names = "core", "clkh", "cd", "aclk"; 867 resets = <&cpg 0xa8>; 868 power-domains = <&cpg>; 869 status = "disabled"; 870 871 sdhi1_vqmmc: vqmmc-regulator { 872 regulator-name = "SDHI1-VQMMC"; 873 regulator-min-microvolt = <1800000>; 874 regulator-max-microvolt = <3300000>; 875 status = "disabled"; 876 }; 877 }; 878 879 sdhi2: mmc@15c20000 { 880 compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; 881 reg = <0x0 0x15c20000 0 0x10000>; 882 interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>; 884 clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, 885 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; 886 clock-names = "core", "clkh", "cd", "aclk"; 887 resets = <&cpg 0xa9>; 888 power-domains = <&cpg>; 889 status = "disabled"; 890 891 sdhi2_vqmmc: vqmmc-regulator { 892 regulator-name = "SDHI2-VQMMC"; 893 regulator-min-microvolt = <1800000>; 894 regulator-max-microvolt = <3300000>; 895 status = "disabled"; 896 }; 897 }; 898 899 eth0: ethernet@15c30000 { 900 compatible = "renesas,r9a09g047-gbeth", "renesas,rzv2h-gbeth", 901 "snps,dwmac-5.20"; 902 reg = <0 0x15c30000 0 0x10000>; 903 clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, 904 <&cpg CPG_CORE R9A09G047_GBETH_0_CLK_PTP_REF_I>, 905 <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, 906 <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; 907 clock-names = "stmmaceth", "pclk", "ptp_ref", 908 "tx", "rx", "tx-180", "rx-180"; 909 interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 918 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 919 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>; 920 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 921 "rx-queue-0", "rx-queue-1", "rx-queue-2", 922 "rx-queue-3", "tx-queue-0", "tx-queue-1", 923 "tx-queue-2", "tx-queue-3"; 924 resets = <&cpg 0xb0>; 925 power-domains = <&cpg>; 926 snps,multicast-filter-bins = <256>; 927 snps,perfect-filter-entries = <128>; 928 rx-fifo-depth = <8192>; 929 tx-fifo-depth = <8192>; 930 snps,mixed-burst; 931 snps,force_sf_dma_mode; 932 snps,axi-config = <&stmmac_axi_setup>; 933 snps,mtl-rx-config = <&mtl_rx_setup0>; 934 snps,mtl-tx-config = <&mtl_tx_setup0>; 935 snps,txpbl = <32>; 936 snps,rxpbl = <32>; 937 status = "disabled"; 938 939 mdio0: mdio { 940 compatible = "snps,dwmac-mdio"; 941 #address-cells = <1>; 942 #size-cells = <0>; 943 }; 944 945 mtl_rx_setup0: rx-queues-config { 946 snps,rx-queues-to-use = <4>; 947 snps,rx-sched-sp; 948 949 queue0 { 950 snps,dcb-algorithm; 951 snps,priority = <0x1>; 952 snps,map-to-dma-channel = <0>; 953 }; 954 955 queue1 { 956 snps,dcb-algorithm; 957 snps,priority = <0x2>; 958 snps,map-to-dma-channel = <1>; 959 }; 960 961 queue2 { 962 snps,dcb-algorithm; 963 snps,priority = <0x4>; 964 snps,map-to-dma-channel = <2>; 965 }; 966 967 queue3 { 968 snps,dcb-algorithm; 969 snps,priority = <0x8>; 970 snps,map-to-dma-channel = <3>; 971 }; 972 }; 973 974 mtl_tx_setup0: tx-queues-config { 975 snps,tx-queues-to-use = <4>; 976 977 queue0 { 978 snps,dcb-algorithm; 979 snps,priority = <0x1>; 980 }; 981 982 queue1 { 983 snps,dcb-algorithm; 984 snps,priority = <0x2>; 985 }; 986 987 queue2 { 988 snps,dcb-algorithm; 989 snps,priority = <0x4>; 990 }; 991 992 queue3 { 993 snps,dcb-algorithm; 994 snps,priority = <0x8>; 995 }; 996 }; 997 }; 998 999 eth1: ethernet@15c40000 { 1000 compatible = "renesas,r9a09g047-gbeth", "renesas,rzv2h-gbeth", 1001 "snps,dwmac-5.20"; 1002 reg = <0 0x15c40000 0 0x10000>; 1003 clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, 1004 <&cpg CPG_CORE R9A09G047_GBETH_1_CLK_PTP_REF_I>, 1005 <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, 1006 <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; 1007 clock-names = "stmmaceth", "pclk", "ptp_ref", 1008 "tx", "rx", "tx-180", "rx-180"; 1009 interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 1010 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 1011 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 1012 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 1013 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 1014 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 1015 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 1016 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 1017 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1018 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 1019 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>; 1020 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 1021 "rx-queue-0", "rx-queue-1", "rx-queue-2", 1022 "rx-queue-3", "tx-queue-0", "tx-queue-1", 1023 "tx-queue-2", "tx-queue-3"; 1024 resets = <&cpg 0xb1>; 1025 power-domains = <&cpg>; 1026 snps,multicast-filter-bins = <256>; 1027 snps,perfect-filter-entries = <128>; 1028 rx-fifo-depth = <8192>; 1029 tx-fifo-depth = <8192>; 1030 snps,mixed-burst; 1031 snps,force_sf_dma_mode; 1032 snps,axi-config = <&stmmac_axi_setup>; 1033 snps,mtl-rx-config = <&mtl_rx_setup1>; 1034 snps,mtl-tx-config = <&mtl_tx_setup1>; 1035 snps,txpbl = <32>; 1036 snps,rxpbl = <32>; 1037 status = "disabled"; 1038 1039 mdio1: mdio { 1040 compatible = "snps,dwmac-mdio"; 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 }; 1044 1045 mtl_rx_setup1: rx-queues-config { 1046 snps,rx-queues-to-use = <4>; 1047 snps,rx-sched-sp; 1048 1049 queue0 { 1050 snps,dcb-algorithm; 1051 snps,priority = <0x1>; 1052 snps,map-to-dma-channel = <0>; 1053 }; 1054 1055 queue1 { 1056 snps,dcb-algorithm; 1057 snps,priority = <0x2>; 1058 snps,map-to-dma-channel = <1>; 1059 }; 1060 1061 queue2 { 1062 snps,dcb-algorithm; 1063 snps,priority = <0x4>; 1064 snps,map-to-dma-channel = <2>; 1065 }; 1066 1067 queue3 { 1068 snps,dcb-algorithm; 1069 snps,priority = <0x8>; 1070 snps,map-to-dma-channel = <3>; 1071 }; 1072 }; 1073 1074 mtl_tx_setup1: tx-queues-config { 1075 snps,tx-queues-to-use = <4>; 1076 1077 queue0 { 1078 snps,dcb-algorithm; 1079 snps,priority = <0x1>; 1080 }; 1081 1082 queue1 { 1083 snps,dcb-algorithm; 1084 snps,priority = <0x2>; 1085 }; 1086 1087 queue2 { 1088 snps,dcb-algorithm; 1089 snps,priority = <0x4>; 1090 }; 1091 1092 queue3 { 1093 snps,dcb-algorithm; 1094 snps,priority = <0x8>; 1095 }; 1096 }; 1097 }; 1098 1099 cru: video@16000000 { 1100 compatible = "renesas,r9a09g047-cru"; 1101 reg = <0 0x16000000 0 0x400>; 1102 clocks = <&cpg CPG_MOD 0xd3>, 1103 <&cpg CPG_MOD 0xd4>, 1104 <&cpg CPG_MOD 0xd2>; 1105 clock-names = "video", "apb", "axi"; 1106 interrupts = <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 840 IRQ_TYPE_EDGE_RISING>, 1109 <GIC_SPI 841 IRQ_TYPE_EDGE_RISING>, 1110 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>; 1111 interrupt-names = "image_conv", "axi_mst_err", 1112 "vd_addr_wend", "sd_addr_wend", 1113 "vsd_addr_wend"; 1114 resets = <&cpg 0xc5>, <&cpg 0xc6>; 1115 reset-names = "presetn", "aresetn"; 1116 power-domains = <&cpg>; 1117 status = "disabled"; 1118 1119 ports { 1120 #address-cells = <1>; 1121 #size-cells = <0>; 1122 1123 port@1 { 1124 #address-cells = <1>; 1125 #size-cells = <0>; 1126 1127 reg = <1>; 1128 crucsi2: endpoint@0 { 1129 reg = <0>; 1130 remote-endpoint = <&csi2cru>; 1131 }; 1132 }; 1133 }; 1134 }; 1135 1136 csi2: csi2@16000400 { 1137 compatible = "renesas,r9a09g047-csi2", "renesas,r9a09g057-csi2"; 1138 reg = <0 0x16000400 0 0xc00>; 1139 interrupts = <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>; 1140 clocks = <&cpg CPG_MOD 0xd3>, <&cpg CPG_MOD 0xd4>; 1141 clock-names = "video", "apb"; 1142 resets = <&cpg 0xc5>, <&cpg 0xc7>; 1143 reset-names = "presetn", "cmn-rstb"; 1144 power-domains = <&cpg>; 1145 status = "disabled"; 1146 1147 ports { 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 1151 port@0 { 1152 reg = <0>; 1153 }; 1154 1155 port@1 { 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 reg = <1>; 1159 1160 csi2cru: endpoint@0 { 1161 reg = <0>; 1162 remote-endpoint = <&crucsi2>; 1163 }; 1164 }; 1165 }; 1166 }; 1167 }; 1168 1169 stmmac_axi_setup: stmmac-axi-config { 1170 snps,lpi_en; 1171 snps,wr_osr_lmt = <0xf>; 1172 snps,rd_osr_lmt = <0xf>; 1173 snps,blen = <16 8 4 0 0 0 0>; 1174 }; 1175 1176 timer { 1177 compatible = "arm,armv8-timer"; 1178 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1179 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1180 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1181 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 1182 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 1183 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 1184 }; 1185}; 1186