xref: /linux/arch/arm64/boot/dts/renesas/r9a08g045.dtsi (revision 96f30c8f0aa9923aa39b30bcaefeacf88b490231)
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G3S SoC
4 *
5 * Copyright (C) 2023 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/r9a08g045-cpg.h>
10
11/ {
12	compatible = "renesas,r9a08g045";
13	#address-cells = <2>;
14	#size-cells = <2>;
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		cpu0: cpu@0 {
21			compatible = "arm,cortex-a55";
22			reg = <0>;
23			device_type = "cpu";
24			#cooling-cells = <2>;
25			next-level-cache = <&L3_CA55>;
26			enable-method = "psci";
27			clocks = <&cpg CPG_CORE R9A08G045_CLK_I>;
28		};
29
30		L3_CA55: cache-controller-0 {
31			compatible = "cache";
32			cache-level = <3>;
33			cache-unified;
34			cache-size = <0x40000>;
35		};
36	};
37
38	extal_clk: extal-clk {
39		compatible = "fixed-clock";
40		#clock-cells = <0>;
41		/* This value must be overridden by the board. */
42		clock-frequency = <0>;
43	};
44
45	psci {
46		compatible = "arm,psci-1.0", "arm,psci-0.2";
47		method = "smc";
48	};
49
50	soc: soc {
51		compatible = "simple-bus";
52		interrupt-parent = <&gic>;
53		#address-cells = <2>;
54		#size-cells = <2>;
55		ranges;
56
57		scif0: serial@1004b800 {
58			compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
59			reg = <0 0x1004b800 0 0x400>;
60			interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
61				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
62				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
63				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
64				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
65				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
66			interrupt-names = "eri", "rxi", "txi",
67					  "bri", "dri", "tei";
68			clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>;
69			clock-names = "fck";
70			power-domains = <&cpg>;
71			resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>;
72			status = "disabled";
73		};
74
75		cpg: clock-controller@11010000 {
76			compatible = "renesas,r9a08g045-cpg";
77			reg = <0 0x11010000 0 0x10000>;
78			clocks = <&extal_clk>;
79			clock-names = "extal";
80			#clock-cells = <2>;
81			#reset-cells = <1>;
82			#power-domain-cells = <0>;
83		};
84
85		sysc: system-controller@11020000 {
86			compatible = "renesas,r9a08g045-sysc";
87			reg = <0 0x11020000 0 0x10000>;
88			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
89				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
90				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
91				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
92			interrupt-names = "lpm_int", "ca55stbydone_int",
93					  "cm33stbyr_int", "ca55_deny";
94			status = "disabled";
95		};
96
97		pinctrl: pinctrl@11030000 {
98			compatible = "renesas,r9a08g045-pinctrl";
99			reg = <0 0x11030000 0 0x10000>;
100			gpio-controller;
101			#gpio-cells = <2>;
102			interrupt-controller;
103			#interrupt-cells = <2>;
104			interrupt-parent = <&irqc>;
105			gpio-ranges = <&pinctrl 0 0 152>;
106			clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
107			power-domains = <&cpg>;
108			resets = <&cpg R9A08G045_GPIO_RSTN>,
109				 <&cpg R9A08G045_GPIO_PORT_RESETN>,
110				 <&cpg R9A08G045_GPIO_SPARE_RESETN>;
111		};
112
113		irqc: interrupt-controller@11050000 {
114			compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc";
115			#interrupt-cells = <2>;
116			#address-cells = <0>;
117			interrupt-controller;
118			reg = <0 0x11050000 0 0x10000>;
119			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
120				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
121				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
122				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
123				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
124				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
125				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
126				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
127				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
128				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
129				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
130				     <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
131				     <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
132				     <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>,
133				     <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
134				     <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
135				     <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
136				     <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
137				     <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
138				     <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
139				     <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
140				     <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
141				     <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
142				     <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
143				     <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
144				     <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
145				     <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
146				     <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
147				     <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
148				     <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
149				     <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
150				     <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
151				     <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
152				     <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
153				     <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
154				     <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
155				     <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
156				     <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
157				     <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
158				     <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
159				     <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
160				     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
161				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
162				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
163				     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
164			interrupt-names = "nmi",
165					  "irq0", "irq1", "irq2", "irq3",
166					  "irq4", "irq5", "irq6", "irq7",
167					  "tint0", "tint1", "tint2", "tint3",
168					  "tint4", "tint5", "tint6", "tint7",
169					  "tint8", "tint9", "tint10", "tint11",
170					  "tint12", "tint13", "tint14", "tint15",
171					  "tint16", "tint17", "tint18", "tint19",
172					  "tint20", "tint21", "tint22", "tint23",
173					  "tint24", "tint25", "tint26", "tint27",
174					  "tint28", "tint29", "tint30", "tint31",
175					  "bus-err", "ec7tie1-0", "ec7tie2-0",
176					  "ec7tiovf-0";
177			clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
178				 <&cpg CPG_MOD R9A08G045_IA55_PCLK>;
179			clock-names = "clk", "pclk";
180			power-domains = <&cpg>;
181			resets = <&cpg R9A08G045_IA55_RESETN>;
182		};
183
184		sdhi0: mmc@11c00000  {
185			compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
186			reg = <0x0 0x11c00000 0 0x10000>;
187			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
188				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
189			clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>,
190				 <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>,
191				 <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>,
192				 <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>;
193			clock-names = "core", "clkh", "cd", "aclk";
194			resets = <&cpg R9A08G045_SDHI0_IXRST>;
195			power-domains = <&cpg>;
196			status = "disabled";
197		};
198
199		sdhi1: mmc@11c10000 {
200			compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
201			reg = <0x0 0x11c10000 0 0x10000>;
202			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
203				     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
204			clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>,
205				 <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>,
206				 <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>,
207				 <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>;
208			clock-names = "core", "clkh", "cd", "aclk";
209			resets = <&cpg R9A08G045_SDHI1_IXRST>;
210			power-domains = <&cpg>;
211			status = "disabled";
212		};
213
214		sdhi2: mmc@11c20000 {
215			compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
216			reg = <0x0 0x11c20000 0 0x10000>;
217			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
218				     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
219			clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>,
220				 <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>,
221				 <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>,
222				 <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>;
223			clock-names = "core", "clkh", "cd", "aclk";
224			resets = <&cpg R9A08G045_SDHI2_IXRST>;
225			power-domains = <&cpg>;
226			status = "disabled";
227		};
228
229		eth0: ethernet@11c30000 {
230			compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
231			reg = <0 0x11c30000 0 0x10000>;
232			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
233				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
234				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
235			interrupt-names = "mux", "fil", "arp_ns";
236			phy-mode = "rgmii";
237			clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>,
238				 <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>,
239				 <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
240			clock-names = "axi", "chi", "refclk";
241			resets = <&cpg R9A08G045_ETH0_RST_HW_N>;
242			power-domains = <&cpg>;
243			#address-cells = <1>;
244			#size-cells = <0>;
245			status = "disabled";
246		};
247
248		eth1: ethernet@11c40000 {
249			compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
250			reg = <0 0x11c40000 0 0x10000>;
251			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
252				     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
253				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
254			interrupt-names = "mux", "fil", "arp_ns";
255			phy-mode = "rgmii";
256			clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>,
257				 <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>,
258				 <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>;
259			clock-names = "axi", "chi", "refclk";
260			resets = <&cpg R9A08G045_ETH1_RST_HW_N>;
261			power-domains = <&cpg>;
262			#address-cells = <1>;
263			#size-cells = <0>;
264			status = "disabled";
265		};
266
267		gic: interrupt-controller@12400000 {
268			compatible = "arm,gic-v3";
269			#interrupt-cells = <3>;
270			#address-cells = <0>;
271			interrupt-controller;
272			reg = <0x0 0x12400000 0 0x40000>,
273			      <0x0 0x12440000 0 0x60000>;
274			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
275		};
276
277		wdt0: watchdog@12800800 {
278			compatible = "renesas,r9a08g045-wdt", "renesas,rzg2l-wdt";
279			reg = <0 0x12800800 0 0x400>;
280			clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>,
281				 <&cpg CPG_MOD R9A08G045_WDT0_CLK>;
282			clock-names = "pclk", "oscclk";
283			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
284				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
285			interrupt-names = "wdt", "perrout";
286			resets = <&cpg R9A08G045_WDT0_PRESETN>;
287			power-domains = <&cpg>;
288			status = "disabled";
289		};
290	};
291
292	timer {
293		compatible = "arm,armv8-timer";
294		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
295				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
296				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
297				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
298				      <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
299		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
300				  "hyp-virt";
301	};
302};
303