1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G3S SoC 4 * 5 * Copyright (C) 2023 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/r9a08g045-cpg.h> 10#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h> 11 12/ { 13 compatible = "renesas,r9a08g045"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu0: cpu@0 { 22 compatible = "arm,cortex-a55"; 23 reg = <0>; 24 device_type = "cpu"; 25 #cooling-cells = <2>; 26 next-level-cache = <&L3_CA55>; 27 enable-method = "psci"; 28 clocks = <&cpg CPG_CORE R9A08G045_CLK_I>; 29 }; 30 31 L3_CA55: cache-controller-0 { 32 compatible = "cache"; 33 cache-level = <3>; 34 cache-unified; 35 cache-size = <0x40000>; 36 }; 37 }; 38 39 extal_clk: extal-clk { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 /* This value must be overridden by the board. */ 43 clock-frequency = <0>; 44 }; 45 46 psci { 47 compatible = "arm,psci-1.0", "arm,psci-0.2"; 48 method = "smc"; 49 }; 50 51 soc: soc { 52 compatible = "simple-bus"; 53 interrupt-parent = <&gic>; 54 #address-cells = <2>; 55 #size-cells = <2>; 56 ranges; 57 58 scif0: serial@1004b800 { 59 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 60 reg = <0 0x1004b800 0 0x400>; 61 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; 67 interrupt-names = "eri", "rxi", "txi", 68 "bri", "dri", "tei"; 69 clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>; 70 clock-names = "fck"; 71 power-domains = <&cpg>; 72 resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>; 73 status = "disabled"; 74 }; 75 76 rtc: rtc@1004ec00 { 77 compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; 78 reg = <0 0x1004ec00 0 0x400>; 79 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 82 interrupt-names = "alarm", "period", "carry"; 83 clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb VBATTB_VBATTCLK>; 84 clock-names = "bus", "counter"; 85 power-domains = <&cpg>; 86 resets = <&cpg R9A08G045_VBAT_BRESETN>; 87 status = "disabled"; 88 }; 89 90 vbattb: clock-controller@1005c000 { 91 compatible = "renesas,r9a08g045-vbattb"; 92 reg = <0 0x1005c000 0 0x1000>; 93 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 94 clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; 95 clock-names = "bclk", "rtx"; 96 #clock-cells = <1>; 97 power-domains = <&cpg>; 98 resets = <&cpg R9A08G045_VBAT_BRESETN>; 99 status = "disabled"; 100 }; 101 102 i2c0: i2c@10090000 { 103 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; 104 reg = <0 0x10090000 0 0x400>; 105 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, 107 <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 108 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 113 interrupt-names = "tei", "ri", "ti", "spi", "sti", 114 "naki", "ali", "tmoi"; 115 clocks = <&cpg CPG_MOD R9A08G045_I2C0_PCLK>; 116 clock-frequency = <100000>; 117 resets = <&cpg R9A08G045_I2C0_MRST>; 118 power-domains = <&cpg>; 119 #address-cells = <1>; 120 #size-cells = <0>; 121 status = "disabled"; 122 }; 123 124 i2c1: i2c@10090400 { 125 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; 126 reg = <0 0x10090400 0 0x400>; 127 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>, 129 <GIC_SPI 272 IRQ_TYPE_EDGE_RISING>, 130 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; 135 interrupt-names = "tei", "ri", "ti", "spi", "sti", 136 "naki", "ali", "tmoi"; 137 clocks = <&cpg CPG_MOD R9A08G045_I2C1_PCLK>; 138 clock-frequency = <100000>; 139 resets = <&cpg R9A08G045_I2C1_MRST>; 140 power-domains = <&cpg>; 141 #address-cells = <1>; 142 #size-cells = <0>; 143 status = "disabled"; 144 }; 145 146 i2c2: i2c@10090800 { 147 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; 148 reg = <0 0x10090800 0 0x400>; 149 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>, 151 <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>, 152 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 157 interrupt-names = "tei", "ri", "ti", "spi", "sti", 158 "naki", "ali", "tmoi"; 159 clocks = <&cpg CPG_MOD R9A08G045_I2C2_PCLK>; 160 clock-frequency = <100000>; 161 resets = <&cpg R9A08G045_I2C2_MRST>; 162 power-domains = <&cpg>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 status = "disabled"; 166 }; 167 168 i2c3: i2c@10090c00 { 169 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; 170 reg = <0 0x10090c00 0 0x400>; 171 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>, 173 <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>, 174 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 179 interrupt-names = "tei", "ri", "ti", "spi", "sti", 180 "naki", "ali", "tmoi"; 181 clocks = <&cpg CPG_MOD R9A08G045_I2C3_PCLK>; 182 clock-frequency = <100000>; 183 resets = <&cpg R9A08G045_I2C3_MRST>; 184 power-domains = <&cpg>; 185 #address-cells = <1>; 186 #size-cells = <0>; 187 status = "disabled"; 188 }; 189 190 cpg: clock-controller@11010000 { 191 compatible = "renesas,r9a08g045-cpg"; 192 reg = <0 0x11010000 0 0x10000>; 193 clocks = <&extal_clk>; 194 clock-names = "extal"; 195 #clock-cells = <2>; 196 #reset-cells = <1>; 197 #power-domain-cells = <0>; 198 }; 199 200 sysc: system-controller@11020000 { 201 compatible = "renesas,r9a08g045-sysc"; 202 reg = <0 0x11020000 0 0x10000>; 203 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 207 interrupt-names = "lpm_int", "ca55stbydone_int", 208 "cm33stbyr_int", "ca55_deny"; 209 status = "disabled"; 210 }; 211 212 pinctrl: pinctrl@11030000 { 213 compatible = "renesas,r9a08g045-pinctrl"; 214 reg = <0 0x11030000 0 0x10000>; 215 gpio-controller; 216 #gpio-cells = <2>; 217 interrupt-controller; 218 #interrupt-cells = <2>; 219 interrupt-parent = <&irqc>; 220 gpio-ranges = <&pinctrl 0 0 152>; 221 clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>; 222 power-domains = <&cpg>; 223 resets = <&cpg R9A08G045_GPIO_RSTN>, 224 <&cpg R9A08G045_GPIO_PORT_RESETN>, 225 <&cpg R9A08G045_GPIO_SPARE_RESETN>; 226 }; 227 228 irqc: interrupt-controller@11050000 { 229 compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc"; 230 #interrupt-cells = <2>; 231 #address-cells = <0>; 232 interrupt-controller; 233 reg = <0 0x11050000 0 0x10000>; 234 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 279 interrupt-names = "nmi", 280 "irq0", "irq1", "irq2", "irq3", 281 "irq4", "irq5", "irq6", "irq7", 282 "tint0", "tint1", "tint2", "tint3", 283 "tint4", "tint5", "tint6", "tint7", 284 "tint8", "tint9", "tint10", "tint11", 285 "tint12", "tint13", "tint14", "tint15", 286 "tint16", "tint17", "tint18", "tint19", 287 "tint20", "tint21", "tint22", "tint23", 288 "tint24", "tint25", "tint26", "tint27", 289 "tint28", "tint29", "tint30", "tint31", 290 "bus-err", "ec7tie1-0", "ec7tie2-0", 291 "ec7tiovf-0"; 292 clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>, 293 <&cpg CPG_MOD R9A08G045_IA55_PCLK>; 294 clock-names = "clk", "pclk"; 295 power-domains = <&cpg>; 296 resets = <&cpg R9A08G045_IA55_RESETN>; 297 }; 298 299 dmac: dma-controller@11820000 { 300 compatible = "renesas,r9a08g045-dmac", 301 "renesas,rz-dmac"; 302 reg = <0 0x11820000 0 0x10000>, 303 <0 0x11830000 0 0x10000>; 304 interrupts = <GIC_SPI 111 IRQ_TYPE_EDGE_RISING>, 305 <GIC_SPI 112 IRQ_TYPE_EDGE_RISING>, 306 <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>, 307 <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>, 308 <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>, 309 <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>, 310 <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>, 311 <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>, 312 <GIC_SPI 119 IRQ_TYPE_EDGE_RISING>, 313 <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>, 314 <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>, 315 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, 316 <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>, 317 <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, 318 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 319 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 320 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>; 321 interrupt-names = "error", 322 "ch0", "ch1", "ch2", "ch3", 323 "ch4", "ch5", "ch6", "ch7", 324 "ch8", "ch9", "ch10", "ch11", 325 "ch12", "ch13", "ch14", "ch15"; 326 clocks = <&cpg CPG_MOD R9A08G045_DMAC_ACLK>, 327 <&cpg CPG_MOD R9A08G045_DMAC_PCLK>; 328 clock-names = "main", "register"; 329 power-domains = <&cpg>; 330 resets = <&cpg R9A08G045_DMAC_ARESETN>, 331 <&cpg R9A08G045_DMAC_RST_ASYNC>; 332 reset-names = "arst", "rst_async"; 333 #dma-cells = <1>; 334 dma-channels = <16>; 335 }; 336 337 sdhi0: mmc@11c00000 { 338 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi"; 339 reg = <0x0 0x11c00000 0 0x10000>; 340 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>, 343 <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>, 344 <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>, 345 <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>; 346 clock-names = "core", "clkh", "cd", "aclk"; 347 resets = <&cpg R9A08G045_SDHI0_IXRST>; 348 power-domains = <&cpg>; 349 status = "disabled"; 350 }; 351 352 sdhi1: mmc@11c10000 { 353 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi"; 354 reg = <0x0 0x11c10000 0 0x10000>; 355 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>, 358 <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>, 359 <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>, 360 <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>; 361 clock-names = "core", "clkh", "cd", "aclk"; 362 resets = <&cpg R9A08G045_SDHI1_IXRST>; 363 power-domains = <&cpg>; 364 status = "disabled"; 365 }; 366 367 sdhi2: mmc@11c20000 { 368 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi"; 369 reg = <0x0 0x11c20000 0 0x10000>; 370 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>, 373 <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>, 374 <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>, 375 <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>; 376 clock-names = "core", "clkh", "cd", "aclk"; 377 resets = <&cpg R9A08G045_SDHI2_IXRST>; 378 power-domains = <&cpg>; 379 status = "disabled"; 380 }; 381 382 eth0: ethernet@11c30000 { 383 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; 384 reg = <0 0x11c30000 0 0x10000>; 385 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 388 interrupt-names = "mux", "fil", "arp_ns"; 389 phy-mode = "rgmii"; 390 clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>, 391 <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>, 392 <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>; 393 clock-names = "axi", "chi", "refclk"; 394 resets = <&cpg R9A08G045_ETH0_RST_HW_N>; 395 power-domains = <&cpg>; 396 #address-cells = <1>; 397 #size-cells = <0>; 398 status = "disabled"; 399 }; 400 401 eth1: ethernet@11c40000 { 402 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; 403 reg = <0 0x11c40000 0 0x10000>; 404 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 405 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 407 interrupt-names = "mux", "fil", "arp_ns"; 408 phy-mode = "rgmii"; 409 clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>, 410 <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>, 411 <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>; 412 clock-names = "axi", "chi", "refclk"; 413 resets = <&cpg R9A08G045_ETH1_RST_HW_N>; 414 power-domains = <&cpg>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 status = "disabled"; 418 }; 419 420 gic: interrupt-controller@12400000 { 421 compatible = "arm,gic-v3"; 422 #interrupt-cells = <3>; 423 #address-cells = <0>; 424 interrupt-controller; 425 reg = <0x0 0x12400000 0 0x20000>, 426 <0x0 0x12440000 0 0x40000>; 427 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 428 }; 429 430 wdt0: watchdog@12800800 { 431 compatible = "renesas,r9a08g045-wdt", "renesas,rzg2l-wdt"; 432 reg = <0 0x12800800 0 0x400>; 433 clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>, 434 <&cpg CPG_MOD R9A08G045_WDT0_CLK>; 435 clock-names = "pclk", "oscclk"; 436 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 438 interrupt-names = "wdt", "perrout"; 439 resets = <&cpg R9A08G045_WDT0_PRESETN>; 440 power-domains = <&cpg>; 441 status = "disabled"; 442 }; 443 }; 444 445 timer { 446 compatible = "arm,armv8-timer"; 447 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 448 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 449 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 450 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 451 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 452 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", 453 "hyp-virt"; 454 }; 455 456 vbattb_xtal: vbattb-xtal { 457 compatible = "fixed-clock"; 458 #clock-cells = <0>; 459 /* This value must be overridden by the board. */ 460 clock-frequency = <0>; 461 }; 462}; 463