1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G3S SoC 4 * 5 * Copyright (C) 2023 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/r9a08g045-cpg.h> 10#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h> 11 12/ { 13 compatible = "renesas,r9a08g045"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 audio_clk1: audio1-clk { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 /* This value must be overridden by boards that provide it. */ 21 clock-frequency = <0>; 22 }; 23 24 audio_clk2: audio2-clk { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 /* This value must be overridden by boards that provide it. */ 28 clock-frequency = <0>; 29 }; 30 31 cluster0_opp: opp-table-0 { 32 compatible = "operating-points-v2"; 33 opp-shared; 34 35 opp-137500000 { 36 opp-hz = /bits/ 64 <137500000>; 37 opp-microvolt = <940000>; 38 clock-latency-ns = <300000>; 39 }; 40 opp-275000000 { 41 opp-hz = /bits/ 64 <275000000>; 42 opp-microvolt = <940000>; 43 clock-latency-ns = <300000>; 44 }; 45 opp-550000000 { 46 opp-hz = /bits/ 64 <550000000>; 47 opp-microvolt = <940000>; 48 clock-latency-ns = <300000>; 49 }; 50 opp-1100000000 { 51 opp-hz = /bits/ 64 <1100000000>; 52 opp-microvolt = <940000>; 53 clock-latency-ns = <300000>; 54 opp-suspend; 55 }; 56 }; 57 58 cpus { 59 #address-cells = <1>; 60 #size-cells = <0>; 61 62 cpu0: cpu@0 { 63 compatible = "arm,cortex-a55"; 64 reg = <0>; 65 device_type = "cpu"; 66 #cooling-cells = <2>; 67 next-level-cache = <&L3_CA55>; 68 enable-method = "psci"; 69 clocks = <&cpg CPG_CORE R9A08G045_CLK_I>; 70 operating-points-v2 = <&cluster0_opp>; 71 }; 72 73 L3_CA55: cache-controller-0 { 74 compatible = "cache"; 75 cache-level = <3>; 76 cache-unified; 77 cache-size = <0x40000>; 78 }; 79 }; 80 81 extal_clk: extal-clk { 82 compatible = "fixed-clock"; 83 #clock-cells = <0>; 84 /* This value must be overridden by the board. */ 85 clock-frequency = <0>; 86 }; 87 88 psci { 89 compatible = "arm,psci-1.0", "arm,psci-0.2"; 90 method = "smc"; 91 }; 92 93 soc: soc { 94 compatible = "simple-bus"; 95 interrupt-parent = <&gic>; 96 #address-cells = <2>; 97 #size-cells = <2>; 98 ranges; 99 100 scif0: serial@1004b800 { 101 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 102 reg = <0 0x1004b800 0 0x400>; 103 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; 109 interrupt-names = "eri", "rxi", "txi", 110 "bri", "dri", "tei"; 111 clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>; 112 clock-names = "fck"; 113 power-domains = <&cpg>; 114 resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>; 115 status = "disabled"; 116 }; 117 118 scif1: serial@1004bc00 { 119 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 120 reg = <0 0x1004bc00 0 0x400>; 121 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 127 interrupt-names = "eri", "rxi", "txi", 128 "bri", "dri", "tei"; 129 clocks = <&cpg CPG_MOD R9A08G045_SCIF1_CLK_PCK>; 130 clock-names = "fck"; 131 power-domains = <&cpg>; 132 resets = <&cpg R9A08G045_SCIF1_RST_SYSTEM_N>; 133 status = "disabled"; 134 }; 135 136 scif2: serial@1004c000 { 137 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 138 reg = <0 0x1004c000 0 0x400>; 139 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>; 145 interrupt-names = "eri", "rxi", "txi", 146 "bri", "dri", "tei"; 147 clocks = <&cpg CPG_MOD R9A08G045_SCIF2_CLK_PCK>; 148 clock-names = "fck"; 149 power-domains = <&cpg>; 150 resets = <&cpg R9A08G045_SCIF2_RST_SYSTEM_N>; 151 status = "disabled"; 152 }; 153 154 scif3: serial@1004c400 { 155 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 156 reg = <0 0x1004c400 0 0x400>; 157 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 163 interrupt-names = "eri", "rxi", "txi", 164 "bri", "dri", "tei"; 165 clocks = <&cpg CPG_MOD R9A08G045_SCIF3_CLK_PCK>; 166 clock-names = "fck"; 167 power-domains = <&cpg>; 168 resets = <&cpg R9A08G045_SCIF3_RST_SYSTEM_N>; 169 status = "disabled"; 170 }; 171 172 scif4: serial@1004c800 { 173 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 174 reg = <0 0x1004c800 0 0x400>; 175 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 181 interrupt-names = "eri", "rxi", "txi", 182 "bri", "dri", "tei"; 183 clocks = <&cpg CPG_MOD R9A08G045_SCIF4_CLK_PCK>; 184 clock-names = "fck"; 185 power-domains = <&cpg>; 186 resets = <&cpg R9A08G045_SCIF4_RST_SYSTEM_N>; 187 status = "disabled"; 188 }; 189 190 scif5: serial@1004e000 { 191 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 192 reg = <0 0x1004e000 0 0x400>; 193 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 199 interrupt-names = "eri", "rxi", "txi", 200 "bri", "dri", "tei"; 201 clocks = <&cpg CPG_MOD R9A08G045_SCIF5_CLK_PCK>; 202 clock-names = "fck"; 203 power-domains = <&cpg>; 204 resets = <&cpg R9A08G045_SCIF5_RST_SYSTEM_N>; 205 status = "disabled"; 206 }; 207 208 rtc: rtc@1004ec00 { 209 compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; 210 reg = <0 0x1004ec00 0 0x400>; 211 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 214 interrupt-names = "alarm", "period", "carry"; 215 clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb VBATTB_VBATTCLK>; 216 clock-names = "bus", "counter"; 217 power-domains = <&cpg>; 218 resets = <&cpg R9A08G045_VBAT_BRESETN>; 219 status = "disabled"; 220 }; 221 222 adc: adc@10058000 { 223 compatible = "renesas,r9a08g045-adc"; 224 reg = <0 0x10058000 0 0x1000>; 225 interrupts = <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>; 226 clocks = <&cpg CPG_MOD R9A08G045_ADC_ADCLK>, 227 <&cpg CPG_MOD R9A08G045_ADC_PCLK>; 228 clock-names = "adclk", "pclk"; 229 resets = <&cpg R9A08G045_ADC_PRESETN>, 230 <&cpg R9A08G045_ADC_ADRST_N>; 231 reset-names = "presetn", "adrst-n"; 232 power-domains = <&cpg>; 233 #address-cells = <1>; 234 #size-cells = <0>; 235 #io-channel-cells = <1>; 236 status = "disabled"; 237 238 channel@0 { 239 reg = <0>; 240 }; 241 242 channel@1 { 243 reg = <1>; 244 }; 245 246 channel@2 { 247 reg = <2>; 248 }; 249 250 channel@3 { 251 reg = <3>; 252 }; 253 254 channel@4 { 255 reg = <4>; 256 }; 257 258 channel@5 { 259 reg = <5>; 260 }; 261 262 channel@6 { 263 reg = <6>; 264 }; 265 266 channel@7 { 267 reg = <7>; 268 }; 269 270 channel@8 { 271 reg = <8>; 272 }; 273 }; 274 275 i3c: i3c@1005b000 { 276 compatible = "renesas,r9a08g045-i3c"; 277 reg = <0 0x1005b000 0 0x1000>; 278 clocks = <&cpg CPG_MOD R9A08G045_I3C_PCLK>, 279 <&cpg CPG_MOD R9A08G045_I3C_TCLK>; 280 clock-names = "pclk", "tclk"; 281 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>, 285 <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>, 286 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 287 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 288 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 289 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 290 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 298 interrupt-names = "ierr", "terr", "abort", "resp", 299 "cmd", "ibi", "rx", "tx", "rcv", 300 "st", "sp", "tend", "nack", "al", 301 "tmo", "wu", "exit"; 302 resets = <&cpg R9A08G045_I3C_PRESETN>, 303 <&cpg R9A08G045_I3C_TRESETN>; 304 reset-names = "presetn", "tresetn"; 305 power-domains = <&cpg>; 306 #address-cells = <3>; 307 #size-cells = <0>; 308 status = "disabled"; 309 }; 310 311 vbattb: clock-controller@1005c000 { 312 compatible = "renesas,r9a08g045-vbattb"; 313 reg = <0 0x1005c000 0 0x1000>; 314 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; 316 clock-names = "bclk", "rtx"; 317 #clock-cells = <1>; 318 power-domains = <&cpg>; 319 resets = <&cpg R9A08G045_VBAT_BRESETN>; 320 status = "disabled"; 321 }; 322 323 i2c0: i2c@10090000 { 324 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; 325 reg = <0 0x10090000 0 0x400>; 326 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, 328 <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 329 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 334 interrupt-names = "tei", "ri", "ti", "spi", "sti", 335 "naki", "ali", "tmoi"; 336 clocks = <&cpg CPG_MOD R9A08G045_I2C0_PCLK>; 337 clock-frequency = <100000>; 338 resets = <&cpg R9A08G045_I2C0_MRST>; 339 power-domains = <&cpg>; 340 #address-cells = <1>; 341 #size-cells = <0>; 342 status = "disabled"; 343 }; 344 345 i2c1: i2c@10090400 { 346 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; 347 reg = <0 0x10090400 0 0x400>; 348 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>, 350 <GIC_SPI 272 IRQ_TYPE_EDGE_RISING>, 351 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; 356 interrupt-names = "tei", "ri", "ti", "spi", "sti", 357 "naki", "ali", "tmoi"; 358 clocks = <&cpg CPG_MOD R9A08G045_I2C1_PCLK>; 359 clock-frequency = <100000>; 360 resets = <&cpg R9A08G045_I2C1_MRST>; 361 power-domains = <&cpg>; 362 #address-cells = <1>; 363 #size-cells = <0>; 364 status = "disabled"; 365 }; 366 367 i2c2: i2c@10090800 { 368 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; 369 reg = <0 0x10090800 0 0x400>; 370 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>, 372 <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>, 373 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 378 interrupt-names = "tei", "ri", "ti", "spi", "sti", 379 "naki", "ali", "tmoi"; 380 clocks = <&cpg CPG_MOD R9A08G045_I2C2_PCLK>; 381 clock-frequency = <100000>; 382 resets = <&cpg R9A08G045_I2C2_MRST>; 383 power-domains = <&cpg>; 384 #address-cells = <1>; 385 #size-cells = <0>; 386 status = "disabled"; 387 }; 388 389 i2c3: i2c@10090c00 { 390 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; 391 reg = <0 0x10090c00 0 0x400>; 392 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>, 394 <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>, 395 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 400 interrupt-names = "tei", "ri", "ti", "spi", "sti", 401 "naki", "ali", "tmoi"; 402 clocks = <&cpg CPG_MOD R9A08G045_I2C3_PCLK>; 403 clock-frequency = <100000>; 404 resets = <&cpg R9A08G045_I2C3_MRST>; 405 power-domains = <&cpg>; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 status = "disabled"; 409 }; 410 411 ssi0: ssi@100a8000 { 412 compatible = "renesas,r9a08g045-ssi", 413 "renesas,rz-ssi"; 414 reg = <0 0x100a8000 0 0x400>; 415 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, 417 <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>; 418 interrupt-names = "int_req", "dma_rx", "dma_tx"; 419 clocks = <&cpg CPG_MOD R9A08G045_SSI0_PCLK2>, 420 <&cpg CPG_MOD R9A08G045_SSI0_PCLK_SFR>, 421 <&audio_clk1>, <&audio_clk2>; 422 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 423 resets = <&cpg R9A08G045_SSI0_RST_M2_REG>; 424 dmas = <&dmac 0x2665>, <&dmac 0x2666>; 425 dma-names = "tx", "rx"; 426 power-domains = <&cpg>; 427 #sound-dai-cells = <0>; 428 status = "disabled"; 429 }; 430 431 ssi1: ssi@100a8400 { 432 compatible = "renesas,r9a08g045-ssi", 433 "renesas,rz-ssi"; 434 reg = <0 0x100a8400 0 0x400>; 435 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>, 437 <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>; 438 interrupt-names = "int_req", "dma_rx", "dma_tx"; 439 clocks = <&cpg CPG_MOD R9A08G045_SSI1_PCLK2>, 440 <&cpg CPG_MOD R9A08G045_SSI1_PCLK_SFR>, 441 <&audio_clk1>, <&audio_clk2>; 442 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 443 resets = <&cpg R9A08G045_SSI1_RST_M2_REG>; 444 dmas = <&dmac 0x2669>, <&dmac 0x266a>; 445 dma-names = "tx", "rx"; 446 power-domains = <&cpg>; 447 #sound-dai-cells = <0>; 448 status = "disabled"; 449 }; 450 451 ssi2: ssi@100a8800 { 452 compatible = "renesas,r9a08g045-ssi", 453 "renesas,rz-ssi"; 454 reg = <0 0x100a8800 0 0x400>; 455 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>, 457 <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>; 458 interrupt-names = "int_req", "dma_rx", "dma_tx"; 459 clocks = <&cpg CPG_MOD R9A08G045_SSI2_PCLK2>, 460 <&cpg CPG_MOD R9A08G045_SSI2_PCLK_SFR>, 461 <&audio_clk1>, <&audio_clk2>; 462 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 463 resets = <&cpg R9A08G045_SSI2_RST_M2_REG>; 464 dmas = <&dmac 0x266d>, <&dmac 0x266e>; 465 dma-names = "tx", "rx"; 466 power-domains = <&cpg>; 467 #sound-dai-cells = <0>; 468 status = "disabled"; 469 }; 470 471 ssi3: ssi@100a8c00 { 472 compatible = "renesas,r9a08g045-ssi", 473 "renesas,rz-ssi"; 474 reg = <0 0x100a8c00 0 0x400>; 475 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, 477 <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>; 478 interrupt-names = "int_req", "dma_rx", "dma_tx"; 479 clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>, 480 <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>, 481 <&audio_clk1>, <&audio_clk2>; 482 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 483 resets = <&cpg R9A08G045_SSI3_RST_M2_REG>; 484 dmas = <&dmac 0x2671>, <&dmac 0x2672>; 485 dma-names = "tx", "rx"; 486 power-domains = <&cpg>; 487 #sound-dai-cells = <0>; 488 status = "disabled"; 489 }; 490 491 cpg: clock-controller@11010000 { 492 compatible = "renesas,r9a08g045-cpg"; 493 reg = <0 0x11010000 0 0x10000>; 494 clocks = <&extal_clk>; 495 clock-names = "extal"; 496 #clock-cells = <2>; 497 #reset-cells = <1>; 498 #power-domain-cells = <0>; 499 }; 500 501 sysc: system-controller@11020000 { 502 compatible = "renesas,r9a08g045-sysc"; 503 reg = <0 0x11020000 0 0x10000>; 504 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 508 interrupt-names = "lpm_int", "ca55stbydone_int", 509 "cm33stbyr_int", "ca55_deny"; 510 }; 511 512 pinctrl: pinctrl@11030000 { 513 compatible = "renesas,r9a08g045-pinctrl"; 514 reg = <0 0x11030000 0 0x10000>; 515 gpio-controller; 516 #gpio-cells = <2>; 517 interrupt-controller; 518 #interrupt-cells = <2>; 519 interrupt-parent = <&irqc>; 520 gpio-ranges = <&pinctrl 0 0 152>; 521 clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>; 522 power-domains = <&cpg>; 523 resets = <&cpg R9A08G045_GPIO_RSTN>, 524 <&cpg R9A08G045_GPIO_PORT_RESETN>, 525 <&cpg R9A08G045_GPIO_SPARE_RESETN>; 526 }; 527 528 irqc: interrupt-controller@11050000 { 529 compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc"; 530 #interrupt-cells = <2>; 531 #address-cells = <0>; 532 interrupt-controller; 533 reg = <0 0x11050000 0 0x10000>; 534 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 579 interrupt-names = "nmi", 580 "irq0", "irq1", "irq2", "irq3", 581 "irq4", "irq5", "irq6", "irq7", 582 "tint0", "tint1", "tint2", "tint3", 583 "tint4", "tint5", "tint6", "tint7", 584 "tint8", "tint9", "tint10", "tint11", 585 "tint12", "tint13", "tint14", "tint15", 586 "tint16", "tint17", "tint18", "tint19", 587 "tint20", "tint21", "tint22", "tint23", 588 "tint24", "tint25", "tint26", "tint27", 589 "tint28", "tint29", "tint30", "tint31", 590 "bus-err", "ec7tie1-0", "ec7tie2-0", 591 "ec7tiovf-0"; 592 clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>, 593 <&cpg CPG_MOD R9A08G045_IA55_PCLK>; 594 clock-names = "clk", "pclk"; 595 power-domains = <&cpg>; 596 resets = <&cpg R9A08G045_IA55_RESETN>; 597 }; 598 599 dmac: dma-controller@11820000 { 600 compatible = "renesas,r9a08g045-dmac", 601 "renesas,rz-dmac"; 602 reg = <0 0x11820000 0 0x10000>, 603 <0 0x11830000 0 0x10000>; 604 interrupts = <GIC_SPI 111 IRQ_TYPE_EDGE_RISING>, 605 <GIC_SPI 112 IRQ_TYPE_EDGE_RISING>, 606 <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>, 607 <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>, 608 <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>, 609 <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>, 610 <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>, 611 <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>, 612 <GIC_SPI 119 IRQ_TYPE_EDGE_RISING>, 613 <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>, 614 <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>, 615 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, 616 <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>, 617 <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, 618 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 619 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 620 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>; 621 interrupt-names = "error", 622 "ch0", "ch1", "ch2", "ch3", 623 "ch4", "ch5", "ch6", "ch7", 624 "ch8", "ch9", "ch10", "ch11", 625 "ch12", "ch13", "ch14", "ch15"; 626 clocks = <&cpg CPG_MOD R9A08G045_DMAC_ACLK>, 627 <&cpg CPG_MOD R9A08G045_DMAC_PCLK>; 628 clock-names = "main", "register"; 629 power-domains = <&cpg>; 630 resets = <&cpg R9A08G045_DMAC_ARESETN>, 631 <&cpg R9A08G045_DMAC_RST_ASYNC>; 632 reset-names = "arst", "rst_async"; 633 #dma-cells = <1>; 634 dma-channels = <16>; 635 }; 636 637 sdhi0: mmc@11c00000 { 638 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi"; 639 reg = <0x0 0x11c00000 0 0x10000>; 640 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>, 643 <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>, 644 <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>, 645 <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>; 646 clock-names = "core", "clkh", "cd", "aclk"; 647 resets = <&cpg R9A08G045_SDHI0_IXRST>; 648 power-domains = <&cpg>; 649 status = "disabled"; 650 }; 651 652 sdhi1: mmc@11c10000 { 653 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi"; 654 reg = <0x0 0x11c10000 0 0x10000>; 655 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 657 clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>, 658 <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>, 659 <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>, 660 <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>; 661 clock-names = "core", "clkh", "cd", "aclk"; 662 resets = <&cpg R9A08G045_SDHI1_IXRST>; 663 power-domains = <&cpg>; 664 status = "disabled"; 665 }; 666 667 sdhi2: mmc@11c20000 { 668 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi"; 669 reg = <0x0 0x11c20000 0 0x10000>; 670 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>, 673 <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>, 674 <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>, 675 <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>; 676 clock-names = "core", "clkh", "cd", "aclk"; 677 resets = <&cpg R9A08G045_SDHI2_IXRST>; 678 power-domains = <&cpg>; 679 status = "disabled"; 680 }; 681 682 eth0: ethernet@11c30000 { 683 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; 684 reg = <0 0x11c30000 0 0x10000>; 685 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 688 interrupt-names = "mux", "fil", "arp_ns"; 689 phy-mode = "rgmii"; 690 clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>, 691 <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>, 692 <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>; 693 clock-names = "axi", "chi", "refclk"; 694 resets = <&cpg R9A08G045_ETH0_RST_HW_N>; 695 power-domains = <&cpg>; 696 #address-cells = <1>; 697 #size-cells = <0>; 698 status = "disabled"; 699 }; 700 701 eth1: ethernet@11c40000 { 702 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; 703 reg = <0 0x11c40000 0 0x10000>; 704 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 707 interrupt-names = "mux", "fil", "arp_ns"; 708 phy-mode = "rgmii"; 709 clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>, 710 <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>, 711 <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>; 712 clock-names = "axi", "chi", "refclk"; 713 resets = <&cpg R9A08G045_ETH1_RST_HW_N>; 714 power-domains = <&cpg>; 715 #address-cells = <1>; 716 #size-cells = <0>; 717 status = "disabled"; 718 }; 719 720 gic: interrupt-controller@12400000 { 721 compatible = "arm,gic-v3"; 722 #interrupt-cells = <3>; 723 #address-cells = <0>; 724 interrupt-controller; 725 reg = <0x0 0x12400000 0 0x20000>, 726 <0x0 0x12440000 0 0x40000>; 727 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 728 }; 729 730 wdt0: watchdog@12800800 { 731 compatible = "renesas,r9a08g045-wdt", "renesas,rzg2l-wdt"; 732 reg = <0 0x12800800 0 0x400>; 733 clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>, 734 <&cpg CPG_MOD R9A08G045_WDT0_CLK>; 735 clock-names = "pclk", "oscclk"; 736 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 738 interrupt-names = "wdt", "perrout"; 739 resets = <&cpg R9A08G045_WDT0_PRESETN>; 740 power-domains = <&cpg>; 741 status = "disabled"; 742 }; 743 }; 744 745 timer { 746 compatible = "arm,armv8-timer"; 747 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 748 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 749 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 750 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 751 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 752 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", 753 "hyp-virt"; 754 }; 755 756 vbattb_xtal: vbattb-xtal { 757 compatible = "fixed-clock"; 758 #clock-cells = <0>; 759 /* This value must be overridden by the board. */ 760 clock-frequency = <0>; 761 }; 762}; 763