1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/r9a07g044-cpg.h> 10 11/ { 12 compatible = "renesas,r9a07g044"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_clk1: audio1-clk { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by boards that provide it */ 20 clock-frequency = <0>; 21 }; 22 23 audio_clk2: audio2-clk { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 /* This value must be overridden by boards that provide it */ 27 clock-frequency = <0>; 28 }; 29 30 /* External CAN clock - to be overridden by boards that provide it */ 31 can_clk: can-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ 38 extal_clk: extal-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 /* This value must be overridden by the board */ 42 clock-frequency = <0>; 43 }; 44 45 cluster0_opp: opp-table-0 { 46 compatible = "operating-points-v2"; 47 opp-shared; 48 49 opp-150000000 { 50 opp-hz = /bits/ 64 <150000000>; 51 opp-microvolt = <1100000>; 52 clock-latency-ns = <300000>; 53 }; 54 opp-300000000 { 55 opp-hz = /bits/ 64 <300000000>; 56 opp-microvolt = <1100000>; 57 clock-latency-ns = <300000>; 58 }; 59 opp-600000000 { 60 opp-hz = /bits/ 64 <600000000>; 61 opp-microvolt = <1100000>; 62 clock-latency-ns = <300000>; 63 }; 64 opp-1200000000 { 65 opp-hz = /bits/ 64 <1200000000>; 66 opp-microvolt = <1100000>; 67 clock-latency-ns = <300000>; 68 opp-suspend; 69 }; 70 }; 71 72 cpus { 73 #address-cells = <1>; 74 #size-cells = <0>; 75 76 cpu-map { 77 cluster0 { 78 core0 { 79 cpu = <&cpu0>; 80 }; 81 core1 { 82 cpu = <&cpu1>; 83 }; 84 }; 85 }; 86 87 cpu0: cpu@0 { 88 compatible = "arm,cortex-a55"; 89 reg = <0>; 90 device_type = "cpu"; 91 #cooling-cells = <2>; 92 next-level-cache = <&L3_CA55>; 93 enable-method = "psci"; 94 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>; 95 operating-points-v2 = <&cluster0_opp>; 96 }; 97 98 cpu1: cpu@100 { 99 compatible = "arm,cortex-a55"; 100 reg = <0x100>; 101 device_type = "cpu"; 102 next-level-cache = <&L3_CA55>; 103 enable-method = "psci"; 104 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>; 105 operating-points-v2 = <&cluster0_opp>; 106 }; 107 108 L3_CA55: cache-controller-0 { 109 compatible = "cache"; 110 cache-unified; 111 cache-size = <0x40000>; 112 cache-level = <3>; 113 }; 114 }; 115 116 gpu_opp_table: opp-table-1 { 117 compatible = "operating-points-v2"; 118 119 opp-500000000 { 120 opp-hz = /bits/ 64 <500000000>; 121 opp-microvolt = <1100000>; 122 }; 123 124 opp-400000000 { 125 opp-hz = /bits/ 64 <400000000>; 126 opp-microvolt = <1100000>; 127 }; 128 129 opp-250000000 { 130 opp-hz = /bits/ 64 <250000000>; 131 opp-microvolt = <1100000>; 132 }; 133 134 opp-200000000 { 135 opp-hz = /bits/ 64 <200000000>; 136 opp-microvolt = <1100000>; 137 }; 138 139 opp-125000000 { 140 opp-hz = /bits/ 64 <125000000>; 141 opp-microvolt = <1100000>; 142 }; 143 144 opp-100000000 { 145 opp-hz = /bits/ 64 <100000000>; 146 opp-microvolt = <1100000>; 147 }; 148 149 opp-62500000 { 150 opp-hz = /bits/ 64 <62500000>; 151 opp-microvolt = <1100000>; 152 }; 153 154 opp-50000000 { 155 opp-hz = /bits/ 64 <50000000>; 156 opp-microvolt = <1100000>; 157 }; 158 }; 159 160 pmu { 161 compatible = "arm,cortex-a55-pmu"; 162 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 163 }; 164 165 psci { 166 compatible = "arm,psci-1.0", "arm,psci-0.2"; 167 method = "smc"; 168 }; 169 170 soc: soc { 171 compatible = "simple-bus"; 172 interrupt-parent = <&gic>; 173 #address-cells = <2>; 174 #size-cells = <2>; 175 ranges; 176 177 mtu3: timer@10001200 { 178 compatible = "renesas,r9a07g044-mtu3", 179 "renesas,rz-mtu3"; 180 reg = <0 0x10001200 0 0xb00>; 181 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>, 182 <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>, 183 <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>, 184 <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>, 185 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>, 186 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>, 187 <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>, 188 <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>, 189 <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>, 190 <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>, 191 <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>, 192 <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>, 193 <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>, 194 <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>, 195 <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>, 196 <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>, 197 <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>, 198 <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>, 199 <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>, 200 <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>, 201 <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>, 202 <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>, 203 <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>, 204 <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>, 205 <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>, 206 <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>, 207 <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>, 208 <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>, 209 <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>, 210 <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>, 211 <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>, 212 <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>, 213 <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>, 214 <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>, 215 <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>, 216 <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>, 217 <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>, 218 <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>, 219 <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 220 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 221 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>, 222 <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>, 223 <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>, 224 <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>; 225 interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", 226 "tciv0", "tgie0", "tgif0", 227 "tgia1", "tgib1", "tciv1", "tciu1", 228 "tgia2", "tgib2", "tciv2", "tciu2", 229 "tgia3", "tgib3", "tgic3", "tgid3", 230 "tciv3", 231 "tgia4", "tgib4", "tgic4", "tgid4", 232 "tciv4", 233 "tgiu5", "tgiv5", "tgiw5", 234 "tgia6", "tgib6", "tgic6", "tgid6", 235 "tciv6", 236 "tgia7", "tgib7", "tgic7", "tgid7", 237 "tciv7", 238 "tgia8", "tgib8", "tgic8", "tgid8", 239 "tciv8", "tciu8"; 240 clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>; 241 power-domains = <&cpg>; 242 resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>; 243 #pwm-cells = <2>; 244 status = "disabled"; 245 }; 246 247 gpt: pwm@10048000 { 248 compatible = "renesas,r9a07g044-gpt", 249 "renesas,rzg2l-gpt"; 250 reg = <0 0x10048000 0 0x800>; 251 #pwm-cells = <3>; 252 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>, 253 <GIC_SPI 219 IRQ_TYPE_EDGE_RISING>, 254 <GIC_SPI 220 IRQ_TYPE_EDGE_RISING>, 255 <GIC_SPI 221 IRQ_TYPE_EDGE_RISING>, 256 <GIC_SPI 222 IRQ_TYPE_EDGE_RISING>, 257 <GIC_SPI 223 IRQ_TYPE_EDGE_RISING>, 258 <GIC_SPI 224 IRQ_TYPE_EDGE_RISING>, 259 <GIC_SPI 225 IRQ_TYPE_EDGE_RISING>, 260 <GIC_SPI 226 IRQ_TYPE_EDGE_RISING>, 261 <GIC_SPI 227 IRQ_TYPE_EDGE_RISING>, 262 <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>, 263 <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>, 264 <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>, 265 <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>, 266 <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>, 267 <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>, 268 <GIC_SPI 237 IRQ_TYPE_EDGE_RISING>, 269 <GIC_SPI 238 IRQ_TYPE_EDGE_RISING>, 270 <GIC_SPI 239 IRQ_TYPE_EDGE_RISING>, 271 <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>, 272 <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>, 273 <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>, 274 <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>, 275 <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>, 276 <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>, 277 <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>, 278 <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, 279 <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>, 280 <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>, 281 <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>, 282 <GIC_SPI 257 IRQ_TYPE_EDGE_RISING>, 283 <GIC_SPI 258 IRQ_TYPE_EDGE_RISING>, 284 <GIC_SPI 259 IRQ_TYPE_EDGE_RISING>, 285 <GIC_SPI 260 IRQ_TYPE_EDGE_RISING>, 286 <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>, 287 <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, 288 <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, 289 <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 290 <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 291 <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 292 <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>, 293 <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>, 294 <GIC_SPI 272 IRQ_TYPE_EDGE_RISING>, 295 <GIC_SPI 273 IRQ_TYPE_EDGE_RISING>, 296 <GIC_SPI 274 IRQ_TYPE_EDGE_RISING>, 297 <GIC_SPI 275 IRQ_TYPE_EDGE_RISING>, 298 <GIC_SPI 276 IRQ_TYPE_EDGE_RISING>, 299 <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>, 300 <GIC_SPI 278 IRQ_TYPE_EDGE_RISING>, 301 <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>, 302 <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>, 303 <GIC_SPI 284 IRQ_TYPE_EDGE_RISING>, 304 <GIC_SPI 285 IRQ_TYPE_EDGE_RISING>, 305 <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>, 306 <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>, 307 <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>, 308 <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>, 309 <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>, 310 <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>, 311 <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>, 312 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 313 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 314 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 315 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 316 <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>, 317 <GIC_SPI 301 IRQ_TYPE_EDGE_RISING>, 318 <GIC_SPI 302 IRQ_TYPE_EDGE_RISING>, 319 <GIC_SPI 303 IRQ_TYPE_EDGE_RISING>, 320 <GIC_SPI 304 IRQ_TYPE_EDGE_RISING>, 321 <GIC_SPI 305 IRQ_TYPE_EDGE_RISING>, 322 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 323 <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>, 324 <GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 325 <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>, 326 <GIC_SPI 313 IRQ_TYPE_EDGE_RISING>, 327 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 328 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>, 329 <GIC_SPI 316 IRQ_TYPE_EDGE_RISING>, 330 <GIC_SPI 317 IRQ_TYPE_EDGE_RISING>, 331 <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 332 interrupt-names = "ccmpa0", "ccmpb0", "cmpc0", "cmpd0", 333 "cmpe0", "cmpf0", "adtrga0", "adtrgb0", 334 "ovf0", "unf0", 335 "ccmpa1", "ccmpb1", "cmpc1", "cmpd1", 336 "cmpe1", "cmpf1", "adtrga1", "adtrgb1", 337 "ovf1", "unf1", 338 "ccmpa2", "ccmpb2", "cmpc2", "cmpd2", 339 "cmpe2", "cmpf2", "adtrga2", "adtrgb2", 340 "ovf2", "unf2", 341 "ccmpa3", "ccmpb3", "cmpc3", "cmpd3", 342 "cmpe3", "cmpf3", "adtrga3", "adtrgb3", 343 "ovf3", "unf3", 344 "ccmpa4", "ccmpb4", "cmpc4", "cmpd4", 345 "cmpe4", "cmpf4", "adtrga4", "adtrgb4", 346 "ovf4", "unf4", 347 "ccmpa5", "ccmpb5", "cmpc5", "cmpd5", 348 "cmpe5", "cmpf5", "adtrga5", "adtrgb5", 349 "ovf5", "unf5", 350 "ccmpa6", "ccmpb6", "cmpc6", "cmpd6", 351 "cmpe6", "cmpf6", "adtrga6", "adtrgb6", 352 "ovf6", "unf6", 353 "ccmpa7", "ccmpb7", "cmpc7", "cmpd7", 354 "cmpe7", "cmpf7", "adtrga7", "adtrgb7", 355 "ovf7", "unf7"; 356 clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>; 357 resets = <&cpg R9A07G044_GPT_RST_C>; 358 power-domains = <&cpg>; 359 status = "disabled"; 360 }; 361 362 ssi0: ssi@10049c00 { 363 compatible = "renesas,r9a07g044-ssi", 364 "renesas,rz-ssi"; 365 reg = <0 0x10049c00 0 0x400>; 366 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>, 368 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>; 369 interrupt-names = "int_req", "dma_rx", "dma_tx"; 370 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>, 371 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>, 372 <&audio_clk1>, <&audio_clk2>; 373 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 374 resets = <&cpg R9A07G044_SSI0_RST_M2_REG>; 375 dmas = <&dmac 0x2655>, <&dmac 0x2656>; 376 dma-names = "tx", "rx"; 377 power-domains = <&cpg>; 378 #sound-dai-cells = <0>; 379 status = "disabled"; 380 }; 381 382 ssi1: ssi@1004a000 { 383 compatible = "renesas,r9a07g044-ssi", 384 "renesas,rz-ssi"; 385 reg = <0 0x1004a000 0 0x400>; 386 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>, 388 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>; 389 interrupt-names = "int_req", "dma_rx", "dma_tx"; 390 clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>, 391 <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>, 392 <&audio_clk1>, <&audio_clk2>; 393 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 394 resets = <&cpg R9A07G044_SSI1_RST_M2_REG>; 395 dmas = <&dmac 0x2659>, <&dmac 0x265a>; 396 dma-names = "tx", "rx"; 397 power-domains = <&cpg>; 398 #sound-dai-cells = <0>; 399 status = "disabled"; 400 }; 401 402 ssi2: ssi@1004a400 { 403 compatible = "renesas,r9a07g044-ssi", 404 "renesas,rz-ssi"; 405 reg = <0 0x1004a400 0 0x400>; 406 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>; 408 interrupt-names = "int_req", "dma_rt"; 409 clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>, 410 <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>, 411 <&audio_clk1>, <&audio_clk2>; 412 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 413 resets = <&cpg R9A07G044_SSI2_RST_M2_REG>; 414 dmas = <&dmac 0x265f>; 415 dma-names = "rt"; 416 power-domains = <&cpg>; 417 #sound-dai-cells = <0>; 418 status = "disabled"; 419 }; 420 421 ssi3: ssi@1004a800 { 422 compatible = "renesas,r9a07g044-ssi", 423 "renesas,rz-ssi"; 424 reg = <0 0x1004a800 0 0x400>; 425 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>, 427 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 428 interrupt-names = "int_req", "dma_rx", "dma_tx"; 429 clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>, 430 <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>, 431 <&audio_clk1>, <&audio_clk2>; 432 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 433 resets = <&cpg R9A07G044_SSI3_RST_M2_REG>; 434 dmas = <&dmac 0x2661>, <&dmac 0x2662>; 435 dma-names = "tx", "rx"; 436 power-domains = <&cpg>; 437 #sound-dai-cells = <0>; 438 status = "disabled"; 439 }; 440 441 spi0: spi@1004ac00 { 442 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz"; 443 reg = <0 0x1004ac00 0 0x400>; 444 interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; 447 interrupt-names = "error", "rx", "tx"; 448 clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>; 449 resets = <&cpg R9A07G044_RSPI0_RST>; 450 dmas = <&dmac 0x2e95>, <&dmac 0x2e96>; 451 dma-names = "tx", "rx"; 452 power-domains = <&cpg>; 453 num-cs = <1>; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 status = "disabled"; 457 }; 458 459 spi1: spi@1004b000 { 460 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz"; 461 reg = <0 0x1004b000 0 0x400>; 462 interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; 465 interrupt-names = "error", "rx", "tx"; 466 clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>; 467 resets = <&cpg R9A07G044_RSPI1_RST>; 468 dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>; 469 dma-names = "tx", "rx"; 470 power-domains = <&cpg>; 471 num-cs = <1>; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 status = "disabled"; 475 }; 476 477 spi2: spi@1004b400 { 478 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz"; 479 reg = <0 0x1004b400 0 0x400>; 480 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; 483 interrupt-names = "error", "rx", "tx"; 484 clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>; 485 resets = <&cpg R9A07G044_RSPI2_RST>; 486 dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>; 487 dma-names = "tx", "rx"; 488 power-domains = <&cpg>; 489 num-cs = <1>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 status = "disabled"; 493 }; 494 495 scif0: serial@1004b800 { 496 compatible = "renesas,scif-r9a07g044"; 497 reg = <0 0x1004b800 0 0x400>; 498 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 504 interrupt-names = "eri", "rxi", "txi", 505 "bri", "dri", "tei"; 506 clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>; 507 clock-names = "fck"; 508 power-domains = <&cpg>; 509 resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>; 510 status = "disabled"; 511 }; 512 513 scif1: serial@1004bc00 { 514 compatible = "renesas,scif-r9a07g044"; 515 reg = <0 0x1004bc00 0 0x400>; 516 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 522 interrupt-names = "eri", "rxi", "txi", 523 "bri", "dri", "tei"; 524 clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>; 525 clock-names = "fck"; 526 power-domains = <&cpg>; 527 resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>; 528 status = "disabled"; 529 }; 530 531 scif2: serial@1004c000 { 532 compatible = "renesas,scif-r9a07g044"; 533 reg = <0 0x1004c000 0 0x400>; 534 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; 540 interrupt-names = "eri", "rxi", "txi", 541 "bri", "dri", "tei"; 542 clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>; 543 clock-names = "fck"; 544 power-domains = <&cpg>; 545 resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>; 546 status = "disabled"; 547 }; 548 549 scif3: serial@1004c400 { 550 compatible = "renesas,scif-r9a07g044"; 551 reg = <0 0x1004c400 0 0x400>; 552 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; 558 interrupt-names = "eri", "rxi", "txi", 559 "bri", "dri", "tei"; 560 clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>; 561 clock-names = "fck"; 562 power-domains = <&cpg>; 563 resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>; 564 status = "disabled"; 565 }; 566 567 scif4: serial@1004c800 { 568 compatible = "renesas,scif-r9a07g044"; 569 reg = <0 0x1004c800 0 0x400>; 570 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 576 interrupt-names = "eri", "rxi", "txi", 577 "bri", "dri", "tei"; 578 clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>; 579 clock-names = "fck"; 580 power-domains = <&cpg>; 581 resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>; 582 status = "disabled"; 583 }; 584 585 sci0: serial@1004d000 { 586 compatible = "renesas,r9a07g044-sci", "renesas,sci"; 587 reg = <0 0x1004d000 0 0x400>; 588 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>, 590 <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>, 591 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 592 interrupt-names = "eri", "rxi", "txi", "tei"; 593 clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>; 594 clock-names = "fck"; 595 power-domains = <&cpg>; 596 resets = <&cpg R9A07G044_SCI0_RST>; 597 status = "disabled"; 598 }; 599 600 sci1: serial@1004d400 { 601 compatible = "renesas,r9a07g044-sci", "renesas,sci"; 602 reg = <0 0x1004d400 0 0x400>; 603 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>, 605 <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>, 606 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 607 interrupt-names = "eri", "rxi", "txi", "tei"; 608 clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>; 609 clock-names = "fck"; 610 power-domains = <&cpg>; 611 resets = <&cpg R9A07G044_SCI1_RST>; 612 status = "disabled"; 613 }; 614 615 canfd: can@10050000 { 616 compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd"; 617 reg = <0 0x10050000 0 0x8000>; 618 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; 626 interrupt-names = "g_err", "g_recc", 627 "ch0_err", "ch0_rec", "ch0_trx", 628 "ch1_err", "ch1_rec", "ch1_trx"; 629 clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>, 630 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>, 631 <&can_clk>; 632 clock-names = "fck", "canfd", "can_clk"; 633 assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>; 634 assigned-clock-rates = <50000000>; 635 resets = <&cpg R9A07G044_CANFD_RSTP_N>, 636 <&cpg R9A07G044_CANFD_RSTC_N>; 637 reset-names = "rstp_n", "rstc_n"; 638 power-domains = <&cpg>; 639 status = "disabled"; 640 641 channel0 { 642 status = "disabled"; 643 }; 644 channel1 { 645 status = "disabled"; 646 }; 647 }; 648 649 i2c0: i2c@10058000 { 650 #address-cells = <1>; 651 #size-cells = <0>; 652 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; 653 reg = <0 0x10058000 0 0x400>; 654 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>, 656 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>, 657 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 662 interrupt-names = "tei", "ri", "ti", "spi", "sti", 663 "naki", "ali", "tmoi"; 664 clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>; 665 clock-frequency = <100000>; 666 resets = <&cpg R9A07G044_I2C0_MRST>; 667 power-domains = <&cpg>; 668 status = "disabled"; 669 }; 670 671 i2c1: i2c@10058400 { 672 #address-cells = <1>; 673 #size-cells = <0>; 674 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; 675 reg = <0 0x10058400 0 0x400>; 676 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>, 678 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>, 679 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 684 interrupt-names = "tei", "ri", "ti", "spi", "sti", 685 "naki", "ali", "tmoi"; 686 clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>; 687 clock-frequency = <100000>; 688 resets = <&cpg R9A07G044_I2C1_MRST>; 689 power-domains = <&cpg>; 690 status = "disabled"; 691 }; 692 693 i2c2: i2c@10058800 { 694 #address-cells = <1>; 695 #size-cells = <0>; 696 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; 697 reg = <0 0x10058800 0 0x400>; 698 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 700 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 701 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 706 interrupt-names = "tei", "ri", "ti", "spi", "sti", 707 "naki", "ali", "tmoi"; 708 clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>; 709 clock-frequency = <100000>; 710 resets = <&cpg R9A07G044_I2C2_MRST>; 711 power-domains = <&cpg>; 712 status = "disabled"; 713 }; 714 715 i2c3: i2c@10058c00 { 716 #address-cells = <1>; 717 #size-cells = <0>; 718 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; 719 reg = <0 0x10058c00 0 0x400>; 720 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>, 722 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 723 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 728 interrupt-names = "tei", "ri", "ti", "spi", "sti", 729 "naki", "ali", "tmoi"; 730 clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>; 731 clock-frequency = <100000>; 732 resets = <&cpg R9A07G044_I2C3_MRST>; 733 power-domains = <&cpg>; 734 status = "disabled"; 735 }; 736 737 adc: adc@10059000 { 738 compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc"; 739 reg = <0 0x10059000 0 0x400>; 740 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>; 741 clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>, 742 <&cpg CPG_MOD R9A07G044_ADC_PCLK>; 743 clock-names = "adclk", "pclk"; 744 resets = <&cpg R9A07G044_ADC_PRESETN>, 745 <&cpg R9A07G044_ADC_ADRST_N>; 746 reset-names = "presetn", "adrst-n"; 747 power-domains = <&cpg>; 748 status = "disabled"; 749 750 #address-cells = <1>; 751 #size-cells = <0>; 752 753 channel@0 { 754 reg = <0>; 755 }; 756 channel@1 { 757 reg = <1>; 758 }; 759 channel@2 { 760 reg = <2>; 761 }; 762 channel@3 { 763 reg = <3>; 764 }; 765 channel@4 { 766 reg = <4>; 767 }; 768 channel@5 { 769 reg = <5>; 770 }; 771 channel@6 { 772 reg = <6>; 773 }; 774 channel@7 { 775 reg = <7>; 776 }; 777 }; 778 779 tsu: thermal@10059400 { 780 compatible = "renesas,r9a07g044-tsu", 781 "renesas,rzg2l-tsu"; 782 reg = <0 0x10059400 0 0x400>; 783 clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>; 784 resets = <&cpg R9A07G044_TSU_PRESETN>; 785 power-domains = <&cpg>; 786 #thermal-sensor-cells = <1>; 787 }; 788 789 sbc: spi@10060000 { 790 compatible = "renesas,r9a07g044-rpc-if", 791 "renesas,rzg2l-rpc-if"; 792 reg = <0 0x10060000 0 0x10000>, 793 <0 0x20000000 0 0x10000000>, 794 <0 0x10070000 0 0x10000>; 795 reg-names = "regs", "dirmap", "wbuf"; 796 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 797 clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>, 798 <&cpg CPG_MOD R9A07G044_SPI_CLK>; 799 resets = <&cpg R9A07G044_SPI_RST>; 800 power-domains = <&cpg>; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 status = "disabled"; 804 }; 805 806 cru: video@10830000 { 807 compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru"; 808 reg = <0 0x10830000 0 0x400>; 809 clocks = <&cpg CPG_MOD R9A07G044_CRU_VCLK>, 810 <&cpg CPG_MOD R9A07G044_CRU_PCLK>, 811 <&cpg CPG_MOD R9A07G044_CRU_ACLK>; 812 clock-names = "video", "apb", "axi"; 813 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 816 interrupt-names = "image_conv", "image_conv_err", "axi_mst_err"; 817 resets = <&cpg R9A07G044_CRU_PRESETN>, 818 <&cpg R9A07G044_CRU_ARESETN>; 819 reset-names = "presetn", "aresetn"; 820 power-domains = <&cpg>; 821 status = "disabled"; 822 823 ports { 824 #address-cells = <1>; 825 #size-cells = <0>; 826 827 port@0 { 828 #address-cells = <1>; 829 #size-cells = <0>; 830 831 reg = <0>; 832 cruparallel: endpoint@0 { 833 reg = <0>; 834 }; 835 }; 836 837 port@1 { 838 #address-cells = <1>; 839 #size-cells = <0>; 840 841 reg = <1>; 842 crucsi2: endpoint@0 { 843 reg = <0>; 844 remote-endpoint = <&csi2cru>; 845 }; 846 }; 847 }; 848 }; 849 850 csi2: csi2@10830400 { 851 compatible = "renesas,r9a07g044-csi2", "renesas,rzg2l-csi2"; 852 reg = <0 0x10830400 0 0xfc00>; 853 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&cpg CPG_MOD R9A07G044_CRU_SYSCLK>, 855 <&cpg CPG_MOD R9A07G044_CRU_VCLK>, 856 <&cpg CPG_MOD R9A07G044_CRU_PCLK>; 857 clock-names = "system", "video", "apb"; 858 resets = <&cpg R9A07G044_CRU_PRESETN>, 859 <&cpg R9A07G044_CRU_CMN_RSTB>; 860 reset-names = "presetn", "cmn-rstb"; 861 power-domains = <&cpg>; 862 status = "disabled"; 863 864 ports { 865 #address-cells = <1>; 866 #size-cells = <0>; 867 868 port@0 { 869 reg = <0>; 870 }; 871 872 port@1 { 873 #address-cells = <1>; 874 #size-cells = <0>; 875 reg = <1>; 876 877 csi2cru: endpoint@0 { 878 reg = <0>; 879 remote-endpoint = <&crucsi2>; 880 }; 881 }; 882 }; 883 }; 884 885 dsi: dsi@10850000 { 886 compatible = "renesas,r9a07g044-mipi-dsi", 887 "renesas,rzg2l-mipi-dsi"; 888 reg = <0 0x10850000 0 0x20000>; 889 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 894 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 896 interrupt-names = "seq0", "seq1", "vin1", "rcv", 897 "ferr", "ppi", "debug"; 898 clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>, 899 <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>, 900 <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>, 901 <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>, 902 <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>, 903 <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>; 904 clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk"; 905 resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>, 906 <&cpg R9A07G044_MIPI_DSI_ARESET_N>, 907 <&cpg R9A07G044_MIPI_DSI_PRESET_N>; 908 reset-names = "rst", "arst", "prst"; 909 power-domains = <&cpg>; 910 status = "disabled"; 911 912 ports { 913 #address-cells = <1>; 914 #size-cells = <0>; 915 916 port@0 { 917 reg = <0>; 918 dsi0_in: endpoint { 919 remote-endpoint = <&du_out_dsi>; 920 }; 921 }; 922 923 port@1 { 924 reg = <1>; 925 }; 926 }; 927 }; 928 929 vspd: vsp@10870000 { 930 compatible = "renesas,r9a07g044-vsp2"; 931 reg = <0 0x10870000 0 0x10000>; 932 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 933 clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, 934 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, 935 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; 936 clock-names = "aclk", "pclk", "vclk"; 937 power-domains = <&cpg>; 938 resets = <&cpg R9A07G044_LCDC_RESET_N>; 939 renesas,fcp = <&fcpvd>; 940 }; 941 942 fcpvd: fcp@10880000 { 943 compatible = "renesas,r9a07g044-fcpvd", 944 "renesas,fcpv"; 945 reg = <0 0x10880000 0 0x10000>; 946 clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, 947 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, 948 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; 949 clock-names = "aclk", "pclk", "vclk"; 950 power-domains = <&cpg>; 951 resets = <&cpg R9A07G044_LCDC_RESET_N>; 952 }; 953 954 du: display@10890000 { 955 compatible = "renesas,r9a07g044-du"; 956 reg = <0 0x10890000 0 0x10000>; 957 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 958 clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, 959 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, 960 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; 961 clock-names = "aclk", "pclk", "vclk"; 962 power-domains = <&cpg>; 963 resets = <&cpg R9A07G044_LCDC_RESET_N>; 964 renesas,vsps = <&vspd 0>; 965 status = "disabled"; 966 967 ports { 968 #address-cells = <1>; 969 #size-cells = <0>; 970 971 port@0 { 972 reg = <0>; 973 du_out_dsi: endpoint { 974 remote-endpoint = <&dsi0_in>; 975 }; 976 }; 977 978 port@1 { 979 reg = <1>; 980 }; 981 }; 982 }; 983 984 cpg: clock-controller@11010000 { 985 compatible = "renesas,r9a07g044-cpg"; 986 reg = <0 0x11010000 0 0x10000>; 987 clocks = <&extal_clk>; 988 clock-names = "extal"; 989 #clock-cells = <2>; 990 #reset-cells = <1>; 991 #power-domain-cells = <0>; 992 }; 993 994 sysc: system-controller@11020000 { 995 compatible = "renesas,r9a07g044-sysc"; 996 reg = <0 0x11020000 0 0x10000>; 997 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1001 interrupt-names = "lpm_int", "ca55stbydone_int", 1002 "cm33stbyr_int", "ca55_deny"; 1003 status = "disabled"; 1004 }; 1005 1006 pinctrl: pinctrl@11030000 { 1007 compatible = "renesas,r9a07g044-pinctrl"; 1008 reg = <0 0x11030000 0 0x10000>; 1009 gpio-controller; 1010 #gpio-cells = <2>; 1011 #interrupt-cells = <2>; 1012 interrupt-parent = <&irqc>; 1013 interrupt-controller; 1014 gpio-ranges = <&pinctrl 0 0 392>; 1015 clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>; 1016 power-domains = <&cpg>; 1017 resets = <&cpg R9A07G044_GPIO_RSTN>, 1018 <&cpg R9A07G044_GPIO_PORT_RESETN>, 1019 <&cpg R9A07G044_GPIO_SPARE_RESETN>; 1020 }; 1021 1022 irqc: interrupt-controller@110a0000 { 1023 compatible = "renesas,r9a07g044-irqc", 1024 "renesas,rzg2l-irqc"; 1025 #interrupt-cells = <2>; 1026 #address-cells = <0>; 1027 interrupt-controller; 1028 reg = <0 0x110a0000 0 0x10000>; 1029 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1033 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1034 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1035 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 1036 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1037 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1038 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 1039 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 1040 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 1041 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 1042 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 1043 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 1044 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 1045 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 1046 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 1047 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 1048 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 1049 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 1050 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 1054 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, 1071 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 1072 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 1073 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 1074 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 1075 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 1076 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 1077 interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3", 1078 "irq4", "irq5", "irq6", "irq7", 1079 "tint0", "tint1", "tint2", "tint3", 1080 "tint4", "tint5", "tint6", "tint7", 1081 "tint8", "tint9", "tint10", "tint11", 1082 "tint12", "tint13", "tint14", "tint15", 1083 "tint16", "tint17", "tint18", "tint19", 1084 "tint20", "tint21", "tint22", "tint23", 1085 "tint24", "tint25", "tint26", "tint27", 1086 "tint28", "tint29", "tint30", "tint31", 1087 "bus-err", "ec7tie1-0", "ec7tie2-0", 1088 "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1", 1089 "ec7tiovf-1"; 1090 clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, 1091 <&cpg CPG_MOD R9A07G044_IA55_PCLK>; 1092 clock-names = "clk", "pclk"; 1093 power-domains = <&cpg>; 1094 resets = <&cpg R9A07G044_IA55_RESETN>; 1095 }; 1096 1097 dmac: dma-controller@11820000 { 1098 compatible = "renesas,r9a07g044-dmac", 1099 "renesas,rz-dmac"; 1100 reg = <0 0x11820000 0 0x10000>, 1101 <0 0x11830000 0 0x10000>; 1102 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, 1103 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 1104 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 1105 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 1106 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 1107 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, 1108 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 1109 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, 1110 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, 1111 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 1112 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 1113 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, 1114 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 1115 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, 1116 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 1117 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 1118 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; 1119 interrupt-names = "error", 1120 "ch0", "ch1", "ch2", "ch3", 1121 "ch4", "ch5", "ch6", "ch7", 1122 "ch8", "ch9", "ch10", "ch11", 1123 "ch12", "ch13", "ch14", "ch15"; 1124 clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>, 1125 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>; 1126 clock-names = "main", "register"; 1127 power-domains = <&cpg>; 1128 resets = <&cpg R9A07G044_DMAC_ARESETN>, 1129 <&cpg R9A07G044_DMAC_RST_ASYNC>; 1130 reset-names = "arst", "rst_async"; 1131 #dma-cells = <1>; 1132 dma-channels = <16>; 1133 }; 1134 1135 gpu: gpu@11840000 { 1136 compatible = "renesas,r9a07g044-mali", 1137 "arm,mali-bifrost"; 1138 reg = <0x0 0x11840000 0x0 0x10000>; 1139 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1143 interrupt-names = "job", "mmu", "gpu", "event"; 1144 clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>, 1145 <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>, 1146 <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>; 1147 clock-names = "gpu", "bus", "bus_ace"; 1148 power-domains = <&cpg>; 1149 resets = <&cpg R9A07G044_GPU_RESETN>, 1150 <&cpg R9A07G044_GPU_AXI_RESETN>, 1151 <&cpg R9A07G044_GPU_ACE_RESETN>; 1152 reset-names = "rst", "axi_rst", "ace_rst"; 1153 operating-points-v2 = <&gpu_opp_table>; 1154 }; 1155 1156 gic: interrupt-controller@11900000 { 1157 compatible = "arm,gic-v3"; 1158 #interrupt-cells = <3>; 1159 #address-cells = <0>; 1160 interrupt-controller; 1161 reg = <0x0 0x11900000 0 0x20000>, 1162 <0x0 0x11940000 0 0x40000>; 1163 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 1164 }; 1165 1166 sdhi0: mmc@11c00000 { 1167 compatible = "renesas,sdhi-r9a07g044", 1168 "renesas,rzg2l-sdhi"; 1169 reg = <0x0 0x11c00000 0 0x10000>; 1170 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1172 clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>, 1173 <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>, 1174 <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>, 1175 <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>; 1176 clock-names = "core", "clkh", "cd", "aclk"; 1177 resets = <&cpg R9A07G044_SDHI0_IXRST>; 1178 power-domains = <&cpg>; 1179 status = "disabled"; 1180 }; 1181 1182 sdhi1: mmc@11c10000 { 1183 compatible = "renesas,sdhi-r9a07g044", 1184 "renesas,rzg2l-sdhi"; 1185 reg = <0x0 0x11c10000 0 0x10000>; 1186 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1188 clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>, 1189 <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>, 1190 <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>, 1191 <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>; 1192 clock-names = "core", "clkh", "cd", "aclk"; 1193 resets = <&cpg R9A07G044_SDHI1_IXRST>; 1194 power-domains = <&cpg>; 1195 status = "disabled"; 1196 }; 1197 1198 eth0: ethernet@11c20000 { 1199 compatible = "renesas,r9a07g044-gbeth", 1200 "renesas,rzg2l-gbeth"; 1201 reg = <0 0x11c20000 0 0x10000>; 1202 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1205 interrupt-names = "mux", "fil", "arp_ns"; 1206 phy-mode = "rgmii"; 1207 clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>, 1208 <&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>, 1209 <&cpg CPG_CORE R9A07G044_CLK_HP>; 1210 clock-names = "axi", "chi", "refclk"; 1211 resets = <&cpg R9A07G044_ETH0_RST_HW_N>; 1212 power-domains = <&cpg>; 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 status = "disabled"; 1216 }; 1217 1218 eth1: ethernet@11c30000 { 1219 compatible = "renesas,r9a07g044-gbeth", 1220 "renesas,rzg2l-gbeth"; 1221 reg = <0 0x11c30000 0 0x10000>; 1222 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1225 interrupt-names = "mux", "fil", "arp_ns"; 1226 phy-mode = "rgmii"; 1227 clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>, 1228 <&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>, 1229 <&cpg CPG_CORE R9A07G044_CLK_HP>; 1230 clock-names = "axi", "chi", "refclk"; 1231 resets = <&cpg R9A07G044_ETH1_RST_HW_N>; 1232 power-domains = <&cpg>; 1233 #address-cells = <1>; 1234 #size-cells = <0>; 1235 status = "disabled"; 1236 }; 1237 1238 phyrst: usbphy-ctrl@11c40000 { 1239 compatible = "renesas,r9a07g044-usbphy-ctrl", 1240 "renesas,rzg2l-usbphy-ctrl"; 1241 reg = <0 0x11c40000 0 0x10000>; 1242 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>; 1243 resets = <&cpg R9A07G044_USB_PRESETN>; 1244 power-domains = <&cpg>; 1245 #reset-cells = <1>; 1246 status = "disabled"; 1247 1248 usb0_vbus_otg: regulator-vbus { 1249 regulator-name = "vbus"; 1250 }; 1251 }; 1252 1253 ohci0: usb@11c50000 { 1254 compatible = "generic-ohci"; 1255 reg = <0 0x11c50000 0 0x100>; 1256 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1257 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 1258 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>; 1259 resets = <&phyrst 0>, 1260 <&cpg R9A07G044_USB_U2H0_HRESETN>; 1261 phys = <&usb2_phy0 1>; 1262 phy-names = "usb"; 1263 power-domains = <&cpg>; 1264 status = "disabled"; 1265 }; 1266 1267 ohci1: usb@11c70000 { 1268 compatible = "generic-ohci"; 1269 reg = <0 0x11c70000 0 0x100>; 1270 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1271 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 1272 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>; 1273 resets = <&phyrst 1>, 1274 <&cpg R9A07G044_USB_U2H1_HRESETN>; 1275 phys = <&usb2_phy1 1>; 1276 phy-names = "usb"; 1277 power-domains = <&cpg>; 1278 status = "disabled"; 1279 }; 1280 1281 ehci0: usb@11c50100 { 1282 compatible = "generic-ehci"; 1283 reg = <0 0x11c50100 0 0x100>; 1284 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1285 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 1286 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>; 1287 resets = <&phyrst 0>, 1288 <&cpg R9A07G044_USB_U2H0_HRESETN>; 1289 phys = <&usb2_phy0 2>; 1290 phy-names = "usb"; 1291 companion = <&ohci0>; 1292 power-domains = <&cpg>; 1293 status = "disabled"; 1294 }; 1295 1296 ehci1: usb@11c70100 { 1297 compatible = "generic-ehci"; 1298 reg = <0 0x11c70100 0 0x100>; 1299 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1300 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 1301 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>; 1302 resets = <&phyrst 1>, 1303 <&cpg R9A07G044_USB_U2H1_HRESETN>; 1304 phys = <&usb2_phy1 2>; 1305 phy-names = "usb"; 1306 companion = <&ohci1>; 1307 power-domains = <&cpg>; 1308 status = "disabled"; 1309 }; 1310 1311 usb2_phy0: usb-phy@11c50200 { 1312 compatible = "renesas,usb2-phy-r9a07g044", 1313 "renesas,rzg2l-usb2-phy"; 1314 reg = <0 0x11c50200 0 0x700>; 1315 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1316 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 1317 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>; 1318 resets = <&phyrst 0>; 1319 #phy-cells = <1>; 1320 power-domains = <&cpg>; 1321 status = "disabled"; 1322 }; 1323 1324 usb2_phy1: usb-phy@11c70200 { 1325 compatible = "renesas,usb2-phy-r9a07g044", 1326 "renesas,rzg2l-usb2-phy"; 1327 reg = <0 0x11c70200 0 0x700>; 1328 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1329 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 1330 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>; 1331 resets = <&phyrst 1>; 1332 #phy-cells = <1>; 1333 power-domains = <&cpg>; 1334 status = "disabled"; 1335 }; 1336 1337 hsusb: usb@11c60000 { 1338 compatible = "renesas,usbhs-r9a07g044", 1339 "renesas,rzg2l-usbhs"; 1340 reg = <0 0x11c60000 0 0x10000>; 1341 interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, 1342 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1343 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1344 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1345 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 1346 <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>; 1347 resets = <&phyrst 0>, 1348 <&cpg R9A07G044_USB_U2P_EXL_SYSRST>; 1349 renesas,buswait = <7>; 1350 phys = <&usb2_phy0 3>; 1351 phy-names = "usb"; 1352 power-domains = <&cpg>; 1353 status = "disabled"; 1354 }; 1355 1356 wdt0: watchdog@12800800 { 1357 compatible = "renesas,r9a07g044-wdt", 1358 "renesas,rzg2l-wdt"; 1359 reg = <0 0x12800800 0 0x400>; 1360 clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>, 1361 <&cpg CPG_MOD R9A07G044_WDT0_CLK>; 1362 clock-names = "pclk", "oscclk"; 1363 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1364 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1365 interrupt-names = "wdt", "perrout"; 1366 resets = <&cpg R9A07G044_WDT0_PRESETN>; 1367 power-domains = <&cpg>; 1368 status = "disabled"; 1369 }; 1370 1371 wdt1: watchdog@12800c00 { 1372 compatible = "renesas,r9a07g044-wdt", 1373 "renesas,rzg2l-wdt"; 1374 reg = <0 0x12800C00 0 0x400>; 1375 clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>, 1376 <&cpg CPG_MOD R9A07G044_WDT1_CLK>; 1377 clock-names = "pclk", "oscclk"; 1378 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1380 interrupt-names = "wdt", "perrout"; 1381 resets = <&cpg R9A07G044_WDT1_PRESETN>; 1382 power-domains = <&cpg>; 1383 status = "disabled"; 1384 }; 1385 1386 ostm0: timer@12801000 { 1387 compatible = "renesas,r9a07g044-ostm", 1388 "renesas,ostm"; 1389 reg = <0x0 0x12801000 0x0 0x400>; 1390 interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>; 1391 clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>; 1392 resets = <&cpg R9A07G044_OSTM0_PRESETZ>; 1393 power-domains = <&cpg>; 1394 status = "disabled"; 1395 }; 1396 1397 ostm1: timer@12801400 { 1398 compatible = "renesas,r9a07g044-ostm", 1399 "renesas,ostm"; 1400 reg = <0x0 0x12801400 0x0 0x400>; 1401 interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>; 1402 clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>; 1403 resets = <&cpg R9A07G044_OSTM1_PRESETZ>; 1404 power-domains = <&cpg>; 1405 status = "disabled"; 1406 }; 1407 1408 ostm2: timer@12801800 { 1409 compatible = "renesas,r9a07g044-ostm", 1410 "renesas,ostm"; 1411 reg = <0x0 0x12801800 0x0 0x400>; 1412 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>; 1413 clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>; 1414 resets = <&cpg R9A07G044_OSTM2_PRESETZ>; 1415 power-domains = <&cpg>; 1416 status = "disabled"; 1417 }; 1418 }; 1419 1420 thermal-zones { 1421 cpu-thermal { 1422 polling-delay-passive = <250>; 1423 polling-delay = <1000>; 1424 thermal-sensors = <&tsu 0>; 1425 sustainable-power = <717>; 1426 1427 cooling-maps { 1428 map0 { 1429 trip = <&target>; 1430 cooling-device = <&cpu0 0 2>; 1431 contribution = <1024>; 1432 }; 1433 }; 1434 1435 trips { 1436 sensor_crit: sensor-crit { 1437 temperature = <125000>; 1438 hysteresis = <1000>; 1439 type = "critical"; 1440 }; 1441 1442 target: trip-point { 1443 temperature = <100000>; 1444 hysteresis = <1000>; 1445 type = "passive"; 1446 }; 1447 }; 1448 }; 1449 }; 1450 1451 timer { 1452 compatible = "arm,armv8-timer"; 1453 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1454 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1455 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1456 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 1457 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 1458 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", 1459 "hyp-virt"; 1460 }; 1461}; 1462