xref: /linux/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi (revision 55d0969c451159cff86949b38c39171cab962069) 
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9
10#define SOC_PERIPHERAL_IRQ(nr)		GIC_SPI nr
11
12#include "r9a07g043.dtsi"
13
14/ {
15	cpus {
16		#address-cells = <1>;
17		#size-cells = <0>;
18
19		cpu0: cpu@0 {
20			compatible = "arm,cortex-a55";
21			reg = <0>;
22			device_type = "cpu";
23			#cooling-cells = <2>;
24			next-level-cache = <&L3_CA55>;
25			enable-method = "psci";
26			clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
27			operating-points-v2 = <&cluster0_opp>;
28		};
29
30		L3_CA55: cache-controller-0 {
31			compatible = "cache";
32			cache-unified;
33			cache-size = <0x40000>;
34			cache-level = <3>;
35		};
36	};
37
38	pmu {
39		compatible = "arm,cortex-a55-pmu";
40		interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
41	};
42
43	psci {
44		compatible = "arm,psci-1.0", "arm,psci-0.2";
45		method = "smc";
46	};
47
48	timer {
49		compatible = "arm,armv8-timer";
50		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
51				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
52				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
53				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
54				      <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
55		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
56				  "hyp-virt";
57	};
58};
59
60&soc {
61	interrupt-parent = <&gic>;
62
63	cru: video@10830000 {
64		compatible = "renesas,r9a07g043-cru", "renesas,rzg2l-cru";
65		reg = <0 0x10830000 0 0x400>;
66		clocks = <&cpg CPG_MOD R9A07G043_CRU_VCLK>,
67			 <&cpg CPG_MOD R9A07G043_CRU_PCLK>,
68			 <&cpg CPG_MOD R9A07G043_CRU_ACLK>;
69		clock-names = "video", "apb", "axi";
70		interrupts = <SOC_PERIPHERAL_IRQ(167) IRQ_TYPE_LEVEL_HIGH>,
71			     <SOC_PERIPHERAL_IRQ(168) IRQ_TYPE_LEVEL_HIGH>,
72			     <SOC_PERIPHERAL_IRQ(169) IRQ_TYPE_LEVEL_HIGH>;
73		interrupt-names = "image_conv", "image_conv_err", "axi_mst_err";
74		resets = <&cpg R9A07G043_CRU_PRESETN>,
75			 <&cpg R9A07G043_CRU_ARESETN>;
76		reset-names = "presetn", "aresetn";
77		power-domains = <&cpg>;
78		status = "disabled";
79
80		ports {
81			#address-cells = <1>;
82			#size-cells = <0>;
83
84			port@1 {
85				#address-cells = <1>;
86				#size-cells = <0>;
87
88				reg = <1>;
89				crucsi2: endpoint@0 {
90					reg = <0>;
91					remote-endpoint = <&csi2cru>;
92				};
93			};
94		};
95	};
96
97	csi2: csi2@10830400 {
98		compatible = "renesas,r9a07g043-csi2", "renesas,rzg2l-csi2";
99		reg = <0 0x10830400 0 0xfc00>;
100		interrupts = <SOC_PERIPHERAL_IRQ(166) IRQ_TYPE_LEVEL_HIGH>;
101		clocks = <&cpg CPG_MOD R9A07G043_CRU_SYSCLK>,
102			 <&cpg CPG_MOD R9A07G043_CRU_VCLK>,
103			 <&cpg CPG_MOD R9A07G043_CRU_PCLK>;
104		clock-names = "system", "video", "apb";
105		resets = <&cpg R9A07G043_CRU_PRESETN>,
106			 <&cpg R9A07G043_CRU_CMN_RSTB>;
107		reset-names = "presetn", "cmn-rstb";
108		power-domains = <&cpg>;
109		status = "disabled";
110
111		ports {
112			#address-cells = <1>;
113			#size-cells = <0>;
114
115			port@0 {
116				reg = <0>;
117			};
118
119			port@1 {
120				#address-cells = <1>;
121				#size-cells = <0>;
122				reg = <1>;
123
124				csi2cru: endpoint@0 {
125					reg = <0>;
126					remote-endpoint = <&crucsi2>;
127				};
128			};
129		};
130	};
131
132	vspd: vsp@10870000 {
133		compatible = "renesas,r9a07g043u-vsp2", "renesas,r9a07g044-vsp2";
134		reg = <0 0x10870000 0 0x10000>;
135		interrupts = <SOC_PERIPHERAL_IRQ(149) IRQ_TYPE_LEVEL_HIGH>;
136		clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>,
137			 <&cpg CPG_MOD R9A07G043_LCDC_CLK_P>,
138			 <&cpg CPG_MOD R9A07G043_LCDC_CLK_D>;
139		clock-names = "aclk", "pclk", "vclk";
140		power-domains = <&cpg>;
141		resets = <&cpg R9A07G043_LCDC_RESET_N>;
142		renesas,fcp = <&fcpvd>;
143	};
144
145	fcpvd: fcp@10880000 {
146		compatible = "renesas,r9a07g043u-fcpvd", "renesas,fcpv";
147		reg = <0 0x10880000 0 0x10000>;
148		clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>,
149			 <&cpg CPG_MOD R9A07G043_LCDC_CLK_P>,
150			 <&cpg CPG_MOD R9A07G043_LCDC_CLK_D>;
151		clock-names = "aclk", "pclk", "vclk";
152		power-domains = <&cpg>;
153		resets = <&cpg R9A07G043_LCDC_RESET_N>;
154	};
155
156	du: display@10890000 {
157		compatible = "renesas,r9a07g043u-du";
158		reg = <0 0x10890000 0 0x10000>;
159		interrupts = <SOC_PERIPHERAL_IRQ(152) IRQ_TYPE_LEVEL_HIGH>;
160		clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>,
161			 <&cpg CPG_MOD R9A07G043_LCDC_CLK_P>,
162			 <&cpg CPG_MOD R9A07G043_LCDC_CLK_D>;
163		clock-names = "aclk", "pclk", "vclk";
164		power-domains = <&cpg>;
165		resets = <&cpg R9A07G043_LCDC_RESET_N>;
166		renesas,vsps = <&vspd 0>;
167		status = "disabled";
168
169		ports {
170			#address-cells = <1>;
171			#size-cells = <0>;
172
173			port@0 {
174				reg = <0>;
175				du_out_rgb: endpoint {
176				};
177			};
178		};
179	};
180
181	irqc: interrupt-controller@110a0000 {
182		compatible = "renesas,r9a07g043u-irqc",
183			     "renesas,rzg2l-irqc";
184		reg = <0 0x110a0000 0 0x10000>;
185		#interrupt-cells = <2>;
186		#address-cells = <0>;
187		interrupt-controller;
188		interrupts = <SOC_PERIPHERAL_IRQ(0) IRQ_TYPE_LEVEL_HIGH>,
189			     <SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>,
190			     <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>,
191			     <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>,
192			     <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>,
193			     <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>,
194			     <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>,
195			     <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>,
196			     <SOC_PERIPHERAL_IRQ(8) IRQ_TYPE_LEVEL_HIGH>,
197			     <SOC_PERIPHERAL_IRQ(444) IRQ_TYPE_LEVEL_HIGH>,
198			     <SOC_PERIPHERAL_IRQ(445) IRQ_TYPE_LEVEL_HIGH>,
199			     <SOC_PERIPHERAL_IRQ(446) IRQ_TYPE_LEVEL_HIGH>,
200			     <SOC_PERIPHERAL_IRQ(447) IRQ_TYPE_LEVEL_HIGH>,
201			     <SOC_PERIPHERAL_IRQ(448) IRQ_TYPE_LEVEL_HIGH>,
202			     <SOC_PERIPHERAL_IRQ(449) IRQ_TYPE_LEVEL_HIGH>,
203			     <SOC_PERIPHERAL_IRQ(450) IRQ_TYPE_LEVEL_HIGH>,
204			     <SOC_PERIPHERAL_IRQ(451) IRQ_TYPE_LEVEL_HIGH>,
205			     <SOC_PERIPHERAL_IRQ(452) IRQ_TYPE_LEVEL_HIGH>,
206			     <SOC_PERIPHERAL_IRQ(453) IRQ_TYPE_LEVEL_HIGH>,
207			     <SOC_PERIPHERAL_IRQ(454) IRQ_TYPE_LEVEL_HIGH>,
208			     <SOC_PERIPHERAL_IRQ(455) IRQ_TYPE_LEVEL_HIGH>,
209			     <SOC_PERIPHERAL_IRQ(456) IRQ_TYPE_LEVEL_HIGH>,
210			     <SOC_PERIPHERAL_IRQ(457) IRQ_TYPE_LEVEL_HIGH>,
211			     <SOC_PERIPHERAL_IRQ(458) IRQ_TYPE_LEVEL_HIGH>,
212			     <SOC_PERIPHERAL_IRQ(459) IRQ_TYPE_LEVEL_HIGH>,
213			     <SOC_PERIPHERAL_IRQ(460) IRQ_TYPE_LEVEL_HIGH>,
214			     <SOC_PERIPHERAL_IRQ(461) IRQ_TYPE_LEVEL_HIGH>,
215			     <SOC_PERIPHERAL_IRQ(462) IRQ_TYPE_LEVEL_HIGH>,
216			     <SOC_PERIPHERAL_IRQ(463) IRQ_TYPE_LEVEL_HIGH>,
217			     <SOC_PERIPHERAL_IRQ(464) IRQ_TYPE_LEVEL_HIGH>,
218			     <SOC_PERIPHERAL_IRQ(465) IRQ_TYPE_LEVEL_HIGH>,
219			     <SOC_PERIPHERAL_IRQ(466) IRQ_TYPE_LEVEL_HIGH>,
220			     <SOC_PERIPHERAL_IRQ(467) IRQ_TYPE_LEVEL_HIGH>,
221			     <SOC_PERIPHERAL_IRQ(468) IRQ_TYPE_LEVEL_HIGH>,
222			     <SOC_PERIPHERAL_IRQ(469) IRQ_TYPE_LEVEL_HIGH>,
223			     <SOC_PERIPHERAL_IRQ(470) IRQ_TYPE_LEVEL_HIGH>,
224			     <SOC_PERIPHERAL_IRQ(471) IRQ_TYPE_LEVEL_HIGH>,
225			     <SOC_PERIPHERAL_IRQ(472) IRQ_TYPE_LEVEL_HIGH>,
226			     <SOC_PERIPHERAL_IRQ(473) IRQ_TYPE_LEVEL_HIGH>,
227			     <SOC_PERIPHERAL_IRQ(474) IRQ_TYPE_LEVEL_HIGH>,
228			     <SOC_PERIPHERAL_IRQ(475) IRQ_TYPE_LEVEL_HIGH>,
229			     <SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>,
230			     <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_EDGE_RISING>,
231			     <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_EDGE_RISING>,
232			     <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_EDGE_RISING>,
233			     <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_EDGE_RISING>,
234			     <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_EDGE_RISING>,
235			     <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_EDGE_RISING>;
236		interrupt-names = "nmi",
237				  "irq0", "irq1", "irq2", "irq3",
238				  "irq4", "irq5", "irq6", "irq7",
239				  "tint0", "tint1", "tint2", "tint3",
240				  "tint4", "tint5", "tint6", "tint7",
241				  "tint8", "tint9", "tint10", "tint11",
242				  "tint12", "tint13", "tint14", "tint15",
243				  "tint16", "tint17", "tint18", "tint19",
244				  "tint20", "tint21", "tint22", "tint23",
245				  "tint24", "tint25", "tint26", "tint27",
246				  "tint28", "tint29", "tint30", "tint31",
247				  "bus-err", "ec7tie1-0", "ec7tie2-0",
248				  "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
249				  "ec7tiovf-1";
250		clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>,
251			<&cpg CPG_MOD R9A07G043_IA55_PCLK>;
252		clock-names = "clk", "pclk";
253		power-domains = <&cpg>;
254		resets = <&cpg R9A07G043_IA55_RESETN>;
255	};
256
257	gic: interrupt-controller@11900000 {
258		compatible = "arm,gic-v3";
259		#interrupt-cells = <3>;
260		#address-cells = <0>;
261		interrupt-controller;
262		reg = <0x0 0x11900000 0 0x20000>,
263		      <0x0 0x11940000 0 0x40000>;
264		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
265	};
266};
267
268&sysc {
269	interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>,
270		     <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>,
271		     <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>,
272		     <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
273	interrupt-names = "lpm_int", "ca55stbydone_int",
274			  "cm33stbyr_int", "ca55_deny";
275};
276