1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G2UL SoC 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/r9a07g043-cpg.h> 10 11/ { 12 compatible = "renesas,r9a07g043"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_clk1: audio-clk1 { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by boards that provide it */ 20 clock-frequency = <0>; 21 }; 22 23 audio_clk2: audio-clk2 { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 /* This value must be overridden by boards that provide it */ 27 clock-frequency = <0>; 28 }; 29 30 /* External CAN clock - to be overridden by boards that provide it */ 31 can_clk: can-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ 38 extal_clk: extal-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 /* This value must be overridden by the board */ 42 clock-frequency = <0>; 43 }; 44 45 cluster0_opp: opp-table-0 { 46 compatible = "operating-points-v2"; 47 opp-shared; 48 49 opp-125000000 { 50 opp-hz = /bits/ 64 <125000000>; 51 opp-microvolt = <1100000>; 52 clock-latency-ns = <300000>; 53 }; 54 opp-250000000 { 55 opp-hz = /bits/ 64 <250000000>; 56 opp-microvolt = <1100000>; 57 clock-latency-ns = <300000>; 58 }; 59 opp-500000000 { 60 opp-hz = /bits/ 64 <500000000>; 61 opp-microvolt = <1100000>; 62 clock-latency-ns = <300000>; 63 }; 64 opp-1000000000 { 65 opp-hz = /bits/ 64 <1000000000>; 66 opp-microvolt = <1100000>; 67 clock-latency-ns = <300000>; 68 opp-suspend; 69 }; 70 }; 71 72 cpus { 73 #address-cells = <1>; 74 #size-cells = <0>; 75 76 cpu0: cpu@0 { 77 compatible = "arm,cortex-a55"; 78 reg = <0>; 79 device_type = "cpu"; 80 next-level-cache = <&L3_CA55>; 81 enable-method = "psci"; 82 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; 83 operating-points-v2 = <&cluster0_opp>; 84 }; 85 86 L3_CA55: cache-controller-0 { 87 compatible = "cache"; 88 cache-unified; 89 cache-size = <0x40000>; 90 }; 91 }; 92 93 psci { 94 compatible = "arm,psci-1.0", "arm,psci-0.2"; 95 method = "smc"; 96 }; 97 98 soc: soc { 99 compatible = "simple-bus"; 100 interrupt-parent = <&gic>; 101 #address-cells = <2>; 102 #size-cells = <2>; 103 ranges; 104 105 ssi0: ssi@10049c00 { 106 compatible = "renesas,r9a07g043-ssi", 107 "renesas,rz-ssi"; 108 reg = <0 0x10049c00 0 0x400>; 109 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>, 111 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>, 112 <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>; 113 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 114 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>, 115 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>, 116 <&audio_clk1>, <&audio_clk2>; 117 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 118 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>; 119 dmas = <&dmac 0x2655>, <&dmac 0x2656>; 120 dma-names = "tx", "rx"; 121 power-domains = <&cpg>; 122 #sound-dai-cells = <0>; 123 status = "disabled"; 124 }; 125 126 ssi1: ssi@1004a000 { 127 compatible = "renesas,r9a07g043-ssi", 128 "renesas,rz-ssi"; 129 reg = <0 0x1004a000 0 0x400>; 130 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>, 132 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>, 133 <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>; 134 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 135 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>, 136 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>, 137 <&audio_clk1>, <&audio_clk2>; 138 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 139 resets = <&cpg R9A07G043_SSI1_RST_M2_REG>; 140 dmas = <&dmac 0x2659>, <&dmac 0x265a>; 141 dma-names = "tx", "rx"; 142 power-domains = <&cpg>; 143 #sound-dai-cells = <0>; 144 status = "disabled"; 145 }; 146 147 ssi2: ssi@1004a400 { 148 compatible = "renesas,r9a07g043-ssi", 149 "renesas,rz-ssi"; 150 reg = <0 0x1004a400 0 0x400>; 151 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>, 153 <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>, 154 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>; 155 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 156 clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>, 157 <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>, 158 <&audio_clk1>, <&audio_clk2>; 159 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 160 resets = <&cpg R9A07G043_SSI2_RST_M2_REG>; 161 dmas = <&dmac 0x265f>; 162 dma-names = "rt"; 163 power-domains = <&cpg>; 164 #sound-dai-cells = <0>; 165 status = "disabled"; 166 }; 167 168 ssi3: ssi@1004a800 { 169 compatible = "renesas,r9a07g043-ssi", 170 "renesas,rz-ssi"; 171 reg = <0 0x1004a800 0 0x400>; 172 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>, 174 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>, 175 <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>; 176 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 177 clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>, 178 <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>, 179 <&audio_clk1>, <&audio_clk2>; 180 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 181 resets = <&cpg R9A07G043_SSI3_RST_M2_REG>; 182 dmas = <&dmac 0x2661>, <&dmac 0x2662>; 183 dma-names = "tx", "rx"; 184 power-domains = <&cpg>; 185 #sound-dai-cells = <0>; 186 status = "disabled"; 187 }; 188 189 spi0: spi@1004ac00 { 190 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; 191 reg = <0 0x1004ac00 0 0x400>; 192 interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; 195 interrupt-names = "error", "rx", "tx"; 196 clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>; 197 resets = <&cpg R9A07G043_RSPI0_RST>; 198 power-domains = <&cpg>; 199 num-cs = <1>; 200 #address-cells = <1>; 201 #size-cells = <0>; 202 status = "disabled"; 203 }; 204 205 spi1: spi@1004b000 { 206 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; 207 reg = <0 0x1004b000 0 0x400>; 208 interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; 211 interrupt-names = "error", "rx", "tx"; 212 clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>; 213 resets = <&cpg R9A07G043_RSPI1_RST>; 214 power-domains = <&cpg>; 215 num-cs = <1>; 216 #address-cells = <1>; 217 #size-cells = <0>; 218 status = "disabled"; 219 }; 220 221 spi2: spi@1004b400 { 222 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; 223 reg = <0 0x1004b400 0 0x400>; 224 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; 227 interrupt-names = "error", "rx", "tx"; 228 clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>; 229 resets = <&cpg R9A07G043_RSPI2_RST>; 230 power-domains = <&cpg>; 231 num-cs = <1>; 232 #address-cells = <1>; 233 #size-cells = <0>; 234 status = "disabled"; 235 }; 236 237 scif0: serial@1004b800 { 238 compatible = "renesas,scif-r9a07g043", 239 "renesas,scif-r9a07g044"; 240 reg = <0 0x1004b800 0 0x400>; 241 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 247 interrupt-names = "eri", "rxi", "txi", 248 "bri", "dri", "tei"; 249 clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; 250 clock-names = "fck"; 251 power-domains = <&cpg>; 252 resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>; 253 status = "disabled"; 254 }; 255 256 scif1: serial@1004bc00 { 257 compatible = "renesas,scif-r9a07g043", 258 "renesas,scif-r9a07g044"; 259 reg = <0 0x1004bc00 0 0x400>; 260 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 266 interrupt-names = "eri", "rxi", "txi", 267 "bri", "dri", "tei"; 268 clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>; 269 clock-names = "fck"; 270 power-domains = <&cpg>; 271 resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>; 272 status = "disabled"; 273 }; 274 275 scif2: serial@1004c000 { 276 compatible = "renesas,scif-r9a07g043", 277 "renesas,scif-r9a07g044"; 278 reg = <0 0x1004c000 0 0x400>; 279 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; 285 interrupt-names = "eri", "rxi", "txi", 286 "bri", "dri", "tei"; 287 clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>; 288 clock-names = "fck"; 289 power-domains = <&cpg>; 290 resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>; 291 status = "disabled"; 292 }; 293 294 scif3: serial@1004c400 { 295 compatible = "renesas,scif-r9a07g043", 296 "renesas,scif-r9a07g044"; 297 reg = <0 0x1004c400 0 0x400>; 298 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; 304 interrupt-names = "eri", "rxi", "txi", 305 "bri", "dri", "tei"; 306 clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>; 307 clock-names = "fck"; 308 power-domains = <&cpg>; 309 resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>; 310 status = "disabled"; 311 }; 312 313 scif4: serial@1004c800 { 314 compatible = "renesas,scif-r9a07g043", 315 "renesas,scif-r9a07g044"; 316 reg = <0 0x1004c800 0 0x400>; 317 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 323 interrupt-names = "eri", "rxi", "txi", 324 "bri", "dri", "tei"; 325 clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>; 326 clock-names = "fck"; 327 power-domains = <&cpg>; 328 resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>; 329 status = "disabled"; 330 }; 331 332 sci0: serial@1004d000 { 333 compatible = "renesas,r9a07g043-sci", "renesas,sci"; 334 reg = <0 0x1004d000 0 0x400>; 335 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 339 interrupt-names = "eri", "rxi", "txi", "tei"; 340 clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>; 341 clock-names = "fck"; 342 power-domains = <&cpg>; 343 resets = <&cpg R9A07G043_SCI0_RST>; 344 status = "disabled"; 345 }; 346 347 sci1: serial@1004d400 { 348 compatible = "renesas,r9a07g043-sci", "renesas,sci"; 349 reg = <0 0x1004d400 0 0x400>; 350 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 354 interrupt-names = "eri", "rxi", "txi", "tei"; 355 clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>; 356 clock-names = "fck"; 357 power-domains = <&cpg>; 358 resets = <&cpg R9A07G043_SCI1_RST>; 359 status = "disabled"; 360 }; 361 362 canfd: can@10050000 { 363 compatible = "renesas,r9a07g043-canfd", "renesas,rzg2l-canfd"; 364 reg = <0 0x10050000 0 0x8000>; 365 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 369 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; 373 interrupt-names = "g_err", "g_recc", 374 "ch0_err", "ch0_rec", "ch0_trx", 375 "ch1_err", "ch1_rec", "ch1_trx"; 376 clocks = <&cpg CPG_MOD R9A07G043_CANFD_PCLK>, 377 <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>, 378 <&can_clk>; 379 clock-names = "fck", "canfd", "can_clk"; 380 assigned-clocks = <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>; 381 assigned-clock-rates = <50000000>; 382 resets = <&cpg R9A07G043_CANFD_RSTP_N>, 383 <&cpg R9A07G043_CANFD_RSTC_N>; 384 reset-names = "rstp_n", "rstc_n"; 385 power-domains = <&cpg>; 386 status = "disabled"; 387 388 channel0 { 389 status = "disabled"; 390 }; 391 channel1 { 392 status = "disabled"; 393 }; 394 }; 395 396 i2c0: i2c@10058000 { 397 #address-cells = <1>; 398 #size-cells = <0>; 399 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 400 reg = <0 0x10058000 0 0x400>; 401 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>, 403 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>, 404 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 405 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 409 interrupt-names = "tei", "ri", "ti", "spi", "sti", 410 "naki", "ali", "tmoi"; 411 clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>; 412 clock-frequency = <100000>; 413 resets = <&cpg R9A07G043_I2C0_MRST>; 414 power-domains = <&cpg>; 415 status = "disabled"; 416 }; 417 418 i2c1: i2c@10058400 { 419 #address-cells = <1>; 420 #size-cells = <0>; 421 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 422 reg = <0 0x10058400 0 0x400>; 423 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>, 425 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>, 426 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 431 interrupt-names = "tei", "ri", "ti", "spi", "sti", 432 "naki", "ali", "tmoi"; 433 clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>; 434 clock-frequency = <100000>; 435 resets = <&cpg R9A07G043_I2C1_MRST>; 436 power-domains = <&cpg>; 437 status = "disabled"; 438 }; 439 440 i2c2: i2c@10058800 { 441 #address-cells = <1>; 442 #size-cells = <0>; 443 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 444 reg = <0 0x10058800 0 0x400>; 445 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 447 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 448 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 453 interrupt-names = "tei", "ri", "ti", "spi", "sti", 454 "naki", "ali", "tmoi"; 455 clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>; 456 clock-frequency = <100000>; 457 resets = <&cpg R9A07G043_I2C2_MRST>; 458 power-domains = <&cpg>; 459 status = "disabled"; 460 }; 461 462 i2c3: i2c@10058c00 { 463 #address-cells = <1>; 464 #size-cells = <0>; 465 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 466 reg = <0 0x10058c00 0 0x400>; 467 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>, 469 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 470 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 475 interrupt-names = "tei", "ri", "ti", "spi", "sti", 476 "naki", "ali", "tmoi"; 477 clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>; 478 clock-frequency = <100000>; 479 resets = <&cpg R9A07G043_I2C3_MRST>; 480 power-domains = <&cpg>; 481 status = "disabled"; 482 }; 483 484 adc: adc@10059000 { 485 reg = <0 0x10059000 0 0x400>; 486 /* place holder */ 487 }; 488 489 sbc: spi@10060000 { 490 reg = <0 0x10060000 0 0x10000>, 491 <0 0x20000000 0 0x10000000>, 492 <0 0x10070000 0 0x10000>; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 /* place holder */ 496 }; 497 498 cpg: clock-controller@11010000 { 499 compatible = "renesas,r9a07g043-cpg"; 500 reg = <0 0x11010000 0 0x10000>; 501 clocks = <&extal_clk>; 502 clock-names = "extal"; 503 #clock-cells = <2>; 504 #reset-cells = <1>; 505 #power-domain-cells = <0>; 506 }; 507 508 sysc: system-controller@11020000 { 509 compatible = "renesas,r9a07g043-sysc"; 510 reg = <0 0x11020000 0 0x10000>; 511 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 515 interrupt-names = "lpm_int", "ca55stbydone_int", 516 "cm33stbyr_int", "ca55_deny"; 517 status = "disabled"; 518 }; 519 520 pinctrl: pinctrl@11030000 { 521 compatible = "renesas,r9a07g043-pinctrl"; 522 reg = <0 0x11030000 0 0x10000>; 523 gpio-controller; 524 #gpio-cells = <2>; 525 gpio-ranges = <&pinctrl 0 0 152>; 526 clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; 527 power-domains = <&cpg>; 528 resets = <&cpg R9A07G043_GPIO_RSTN>, 529 <&cpg R9A07G043_GPIO_PORT_RESETN>, 530 <&cpg R9A07G043_GPIO_SPARE_RESETN>; 531 }; 532 533 dmac: dma-controller@11820000 { 534 compatible = "renesas,r9a07g043-dmac", 535 "renesas,rz-dmac"; 536 reg = <0 0x11820000 0 0x10000>, 537 <0 0x11830000 0 0x10000>; 538 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, 539 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 540 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 541 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 542 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 543 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, 544 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 545 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, 546 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, 547 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 548 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 549 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, 550 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 551 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, 552 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 553 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 554 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; 555 interrupt-names = "error", 556 "ch0", "ch1", "ch2", "ch3", 557 "ch4", "ch5", "ch6", "ch7", 558 "ch8", "ch9", "ch10", "ch11", 559 "ch12", "ch13", "ch14", "ch15"; 560 clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>, 561 <&cpg CPG_MOD R9A07G043_DMAC_PCLK>; 562 power-domains = <&cpg>; 563 resets = <&cpg R9A07G043_DMAC_ARESETN>, 564 <&cpg R9A07G043_DMAC_RST_ASYNC>; 565 #dma-cells = <1>; 566 dma-channels = <16>; 567 }; 568 569 gic: interrupt-controller@11900000 { 570 compatible = "arm,gic-v3"; 571 #interrupt-cells = <3>; 572 #address-cells = <0>; 573 interrupt-controller; 574 reg = <0x0 0x11900000 0 0x40000>, 575 <0x0 0x11940000 0 0x60000>; 576 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 577 }; 578 579 sdhi0: mmc@11c00000 { 580 compatible = "renesas,sdhi-r9a07g043", 581 "renesas,rcar-gen3-sdhi"; 582 reg = <0x0 0x11c00000 0 0x10000>; 583 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>, 586 <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>, 587 <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>, 588 <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>; 589 clock-names = "core", "clkh", "cd", "aclk"; 590 resets = <&cpg R9A07G043_SDHI0_IXRST>; 591 power-domains = <&cpg>; 592 status = "disabled"; 593 }; 594 595 sdhi1: mmc@11c10000 { 596 compatible = "renesas,sdhi-r9a07g043", 597 "renesas,rcar-gen3-sdhi"; 598 reg = <0x0 0x11c10000 0 0x10000>; 599 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>, 602 <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>, 603 <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>, 604 <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>; 605 clock-names = "core", "clkh", "cd", "aclk"; 606 resets = <&cpg R9A07G043_SDHI1_IXRST>; 607 power-domains = <&cpg>; 608 status = "disabled"; 609 }; 610 611 eth0: ethernet@11c20000 { 612 compatible = "renesas,r9a07g043-gbeth", 613 "renesas,rzg2l-gbeth"; 614 reg = <0 0x11c20000 0 0x10000>; 615 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 618 interrupt-names = "mux", "fil", "arp_ns"; 619 phy-mode = "rgmii"; 620 clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>, 621 <&cpg CPG_MOD R9A07G043_ETH0_CLK_CHI>, 622 <&cpg CPG_CORE R9A07G043_CLK_HP>; 623 clock-names = "axi", "chi", "refclk"; 624 resets = <&cpg R9A07G043_ETH0_RST_HW_N>; 625 power-domains = <&cpg>; 626 #address-cells = <1>; 627 #size-cells = <0>; 628 status = "disabled"; 629 }; 630 631 eth1: ethernet@11c30000 { 632 compatible = "renesas,r9a07g043-gbeth", 633 "renesas,rzg2l-gbeth"; 634 reg = <0 0x11c30000 0 0x10000>; 635 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 638 interrupt-names = "mux", "fil", "arp_ns"; 639 phy-mode = "rgmii"; 640 clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>, 641 <&cpg CPG_MOD R9A07G043_ETH1_CLK_CHI>, 642 <&cpg CPG_CORE R9A07G043_CLK_HP>; 643 clock-names = "axi", "chi", "refclk"; 644 resets = <&cpg R9A07G043_ETH1_RST_HW_N>; 645 power-domains = <&cpg>; 646 #address-cells = <1>; 647 #size-cells = <0>; 648 status = "disabled"; 649 }; 650 651 phyrst: usbphy-ctrl@11c40000 { 652 compatible = "renesas,r9a07g043-usbphy-ctrl", 653 "renesas,rzg2l-usbphy-ctrl"; 654 reg = <0 0x11c40000 0 0x10000>; 655 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>; 656 resets = <&cpg R9A07G043_USB_PRESETN>; 657 power-domains = <&cpg>; 658 #reset-cells = <1>; 659 status = "disabled"; 660 }; 661 662 ohci0: usb@11c50000 { 663 compatible = "generic-ohci"; 664 reg = <0 0x11c50000 0 0x100>; 665 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 667 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; 668 resets = <&phyrst 0>, 669 <&cpg R9A07G043_USB_U2H0_HRESETN>; 670 phys = <&usb2_phy0 1>; 671 phy-names = "usb"; 672 power-domains = <&cpg>; 673 status = "disabled"; 674 }; 675 676 ohci1: usb@11c70000 { 677 compatible = "generic-ohci"; 678 reg = <0 0x11c70000 0 0x100>; 679 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 680 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 681 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; 682 resets = <&phyrst 1>, 683 <&cpg R9A07G043_USB_U2H1_HRESETN>; 684 phys = <&usb2_phy1 1>; 685 phy-names = "usb"; 686 power-domains = <&cpg>; 687 status = "disabled"; 688 }; 689 690 ehci0: usb@11c50100 { 691 compatible = "generic-ehci"; 692 reg = <0 0x11c50100 0 0x100>; 693 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 694 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 695 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; 696 resets = <&phyrst 0>, 697 <&cpg R9A07G043_USB_U2H0_HRESETN>; 698 phys = <&usb2_phy0 2>; 699 phy-names = "usb"; 700 companion = <&ohci0>; 701 power-domains = <&cpg>; 702 status = "disabled"; 703 }; 704 705 ehci1: usb@11c70100 { 706 compatible = "generic-ehci"; 707 reg = <0 0x11c70100 0 0x100>; 708 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 710 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; 711 resets = <&phyrst 1>, 712 <&cpg R9A07G043_USB_U2H1_HRESETN>; 713 phys = <&usb2_phy1 2>; 714 phy-names = "usb"; 715 companion = <&ohci1>; 716 power-domains = <&cpg>; 717 status = "disabled"; 718 }; 719 720 usb2_phy0: usb-phy@11c50200 { 721 compatible = "renesas,usb2-phy-r9a07g043", 722 "renesas,rzg2l-usb2-phy"; 723 reg = <0 0x11c50200 0 0x700>; 724 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 725 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 726 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; 727 resets = <&phyrst 0>; 728 #phy-cells = <1>; 729 power-domains = <&cpg>; 730 status = "disabled"; 731 }; 732 733 usb2_phy1: usb-phy@11c70200 { 734 compatible = "renesas,usb2-phy-r9a07g043", 735 "renesas,rzg2l-usb2-phy"; 736 reg = <0 0x11c70200 0 0x700>; 737 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 739 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; 740 resets = <&phyrst 1>; 741 #phy-cells = <1>; 742 power-domains = <&cpg>; 743 status = "disabled"; 744 }; 745 746 hsusb: usb@11c60000 { 747 compatible = "renesas,usbhs-r9a07g043", 748 "renesas,rza2-usbhs"; 749 reg = <0 0x11c60000 0 0x10000>; 750 interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, 751 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 755 <&cpg CPG_MOD R9A07G043_USB_U2P_EXR_CPUCLK>; 756 resets = <&phyrst 0>, 757 <&cpg R9A07G043_USB_U2P_EXL_SYSRST>; 758 renesas,buswait = <7>; 759 phys = <&usb2_phy0 3>; 760 phy-names = "usb"; 761 power-domains = <&cpg>; 762 status = "disabled"; 763 }; 764 765 wdt0: watchdog@12800800 { 766 compatible = "renesas,r9a07g043-wdt", 767 "renesas,rzg2l-wdt"; 768 reg = <0 0x12800800 0 0x400>; 769 clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>, 770 <&cpg CPG_MOD R9A07G043_WDT0_CLK>; 771 clock-names = "pclk", "oscclk"; 772 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 774 interrupt-names = "wdt", "perrout"; 775 resets = <&cpg R9A07G043_WDT0_PRESETN>; 776 power-domains = <&cpg>; 777 status = "disabled"; 778 }; 779 780 wdt2: watchdog@12800400 { 781 compatible = "renesas,r9a07g043-wdt", 782 "renesas,rzg2l-wdt"; 783 reg = <0 0x12800400 0 0x400>; 784 clocks = <&cpg CPG_MOD R9A07G043_WDT2_PCLK>, 785 <&cpg CPG_MOD R9A07G043_WDT2_CLK>; 786 clock-names = "pclk", "oscclk"; 787 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 789 interrupt-names = "wdt", "perrout"; 790 resets = <&cpg R9A07G043_WDT2_PRESETN>; 791 power-domains = <&cpg>; 792 status = "disabled"; 793 }; 794 795 ostm0: timer@12801000 { 796 compatible = "renesas,r9a07g043-ostm", 797 "renesas,ostm"; 798 reg = <0x0 0x12801000 0x0 0x400>; 799 interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>; 800 clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>; 801 resets = <&cpg R9A07G043_OSTM0_PRESETZ>; 802 power-domains = <&cpg>; 803 status = "disabled"; 804 }; 805 806 ostm1: timer@12801400 { 807 compatible = "renesas,r9a07g043-ostm", 808 "renesas,ostm"; 809 reg = <0x0 0x12801400 0x0 0x400>; 810 interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>; 811 clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>; 812 resets = <&cpg R9A07G043_OSTM1_PRESETZ>; 813 power-domains = <&cpg>; 814 status = "disabled"; 815 }; 816 817 ostm2: timer@12801800 { 818 compatible = "renesas,r9a07g043-ostm", 819 "renesas,ostm"; 820 reg = <0x0 0x12801800 0x0 0x400>; 821 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>; 822 clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>; 823 resets = <&cpg R9A07G043_OSTM2_PRESETZ>; 824 power-domains = <&cpg>; 825 status = "disabled"; 826 }; 827 }; 828 829 timer { 830 compatible = "arm,armv8-timer"; 831 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 832 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 833 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 834 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 835 }; 836}; 837