1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/Five and RZ/G2UL SoCs 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r9a07g043-cpg.h> 9 10/ { 11 compatible = "renesas,r9a07g043"; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 audio_clk1: audio1-clk { 16 compatible = "fixed-clock"; 17 #clock-cells = <0>; 18 /* This value must be overridden by boards that provide it */ 19 clock-frequency = <0>; 20 }; 21 22 audio_clk2: audio2-clk { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 /* This value must be overridden by boards that provide it */ 26 clock-frequency = <0>; 27 }; 28 29 /* External CAN clock - to be overridden by boards that provide it */ 30 can_clk: can-clk { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <0>; 34 }; 35 36 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ 37 extal_clk: extal-clk { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 /* This value must be overridden by the board */ 41 clock-frequency = <0>; 42 }; 43 44 cluster0_opp: opp-table-0 { 45 compatible = "operating-points-v2"; 46 opp-shared; 47 48 opp-125000000 { 49 opp-hz = /bits/ 64 <125000000>; 50 opp-microvolt = <1100000>; 51 clock-latency-ns = <300000>; 52 }; 53 opp-250000000 { 54 opp-hz = /bits/ 64 <250000000>; 55 opp-microvolt = <1100000>; 56 clock-latency-ns = <300000>; 57 }; 58 opp-500000000 { 59 opp-hz = /bits/ 64 <500000000>; 60 opp-microvolt = <1100000>; 61 clock-latency-ns = <300000>; 62 }; 63 opp-1000000000 { 64 opp-hz = /bits/ 64 <1000000000>; 65 opp-microvolt = <1100000>; 66 clock-latency-ns = <300000>; 67 opp-suspend; 68 }; 69 }; 70 71 soc: soc { 72 compatible = "simple-bus"; 73 #address-cells = <2>; 74 #size-cells = <2>; 75 ranges; 76 77 ssi0: ssi@10049c00 { 78 compatible = "renesas,r9a07g043-ssi", 79 "renesas,rz-ssi"; 80 reg = <0 0x10049c00 0 0x400>; 81 interrupts = <SOC_PERIPHERAL_IRQ(326) IRQ_TYPE_LEVEL_HIGH>, 82 <SOC_PERIPHERAL_IRQ(327) IRQ_TYPE_EDGE_RISING>, 83 <SOC_PERIPHERAL_IRQ(328) IRQ_TYPE_EDGE_RISING>; 84 interrupt-names = "int_req", "dma_rx", "dma_tx"; 85 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>, 86 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>, 87 <&audio_clk1>, <&audio_clk2>; 88 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 89 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>; 90 dmas = <&dmac 0x2655>, <&dmac 0x2656>; 91 dma-names = "tx", "rx"; 92 power-domains = <&cpg>; 93 #sound-dai-cells = <0>; 94 status = "disabled"; 95 }; 96 97 ssi1: ssi@1004a000 { 98 compatible = "renesas,r9a07g043-ssi", 99 "renesas,rz-ssi"; 100 reg = <0 0x1004a000 0 0x400>; 101 interrupts = <SOC_PERIPHERAL_IRQ(330) IRQ_TYPE_LEVEL_HIGH>, 102 <SOC_PERIPHERAL_IRQ(331) IRQ_TYPE_EDGE_RISING>, 103 <SOC_PERIPHERAL_IRQ(332) IRQ_TYPE_EDGE_RISING>; 104 interrupt-names = "int_req", "dma_rx", "dma_tx"; 105 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>, 106 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>, 107 <&audio_clk1>, <&audio_clk2>; 108 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 109 resets = <&cpg R9A07G043_SSI1_RST_M2_REG>; 110 dmas = <&dmac 0x2659>, <&dmac 0x265a>; 111 dma-names = "tx", "rx"; 112 power-domains = <&cpg>; 113 #sound-dai-cells = <0>; 114 status = "disabled"; 115 }; 116 117 ssi2: ssi@1004a400 { 118 compatible = "renesas,r9a07g043-ssi", 119 "renesas,rz-ssi"; 120 reg = <0 0x1004a400 0 0x400>; 121 interrupts = <SOC_PERIPHERAL_IRQ(334) IRQ_TYPE_LEVEL_HIGH>, 122 <SOC_PERIPHERAL_IRQ(337) IRQ_TYPE_EDGE_RISING>; 123 interrupt-names = "int_req", "dma_rt"; 124 clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>, 125 <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>, 126 <&audio_clk1>, <&audio_clk2>; 127 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 128 resets = <&cpg R9A07G043_SSI2_RST_M2_REG>; 129 dmas = <&dmac 0x265f>; 130 dma-names = "rt"; 131 power-domains = <&cpg>; 132 #sound-dai-cells = <0>; 133 status = "disabled"; 134 }; 135 136 ssi3: ssi@1004a800 { 137 compatible = "renesas,r9a07g043-ssi", 138 "renesas,rz-ssi"; 139 reg = <0 0x1004a800 0 0x400>; 140 interrupts = <SOC_PERIPHERAL_IRQ(338) IRQ_TYPE_LEVEL_HIGH>, 141 <SOC_PERIPHERAL_IRQ(339) IRQ_TYPE_EDGE_RISING>, 142 <SOC_PERIPHERAL_IRQ(340) IRQ_TYPE_EDGE_RISING>; 143 interrupt-names = "int_req", "dma_rx", "dma_tx"; 144 clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>, 145 <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>, 146 <&audio_clk1>, <&audio_clk2>; 147 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 148 resets = <&cpg R9A07G043_SSI3_RST_M2_REG>; 149 dmas = <&dmac 0x2661>, <&dmac 0x2662>; 150 dma-names = "tx", "rx"; 151 power-domains = <&cpg>; 152 #sound-dai-cells = <0>; 153 status = "disabled"; 154 }; 155 156 spi0: spi@1004ac00 { 157 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; 158 reg = <0 0x1004ac00 0 0x400>; 159 interrupts = <SOC_PERIPHERAL_IRQ(415) IRQ_TYPE_LEVEL_HIGH>, 160 <SOC_PERIPHERAL_IRQ(413) IRQ_TYPE_LEVEL_HIGH>, 161 <SOC_PERIPHERAL_IRQ(414) IRQ_TYPE_LEVEL_HIGH>; 162 interrupt-names = "error", "rx", "tx"; 163 clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>; 164 resets = <&cpg R9A07G043_RSPI0_RST>; 165 dmas = <&dmac 0x2e95>, <&dmac 0x2e96>; 166 dma-names = "tx", "rx"; 167 power-domains = <&cpg>; 168 num-cs = <1>; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 status = "disabled"; 172 }; 173 174 spi1: spi@1004b000 { 175 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; 176 reg = <0 0x1004b000 0 0x400>; 177 interrupts = <SOC_PERIPHERAL_IRQ(418) IRQ_TYPE_LEVEL_HIGH>, 178 <SOC_PERIPHERAL_IRQ(416) IRQ_TYPE_LEVEL_HIGH>, 179 <SOC_PERIPHERAL_IRQ(417) IRQ_TYPE_LEVEL_HIGH>; 180 interrupt-names = "error", "rx", "tx"; 181 clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>; 182 resets = <&cpg R9A07G043_RSPI1_RST>; 183 dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>; 184 dma-names = "tx", "rx"; 185 power-domains = <&cpg>; 186 num-cs = <1>; 187 #address-cells = <1>; 188 #size-cells = <0>; 189 status = "disabled"; 190 }; 191 192 spi2: spi@1004b400 { 193 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; 194 reg = <0 0x1004b400 0 0x400>; 195 interrupts = <SOC_PERIPHERAL_IRQ(421) IRQ_TYPE_LEVEL_HIGH>, 196 <SOC_PERIPHERAL_IRQ(419) IRQ_TYPE_LEVEL_HIGH>, 197 <SOC_PERIPHERAL_IRQ(420) IRQ_TYPE_LEVEL_HIGH>; 198 interrupt-names = "error", "rx", "tx"; 199 clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>; 200 resets = <&cpg R9A07G043_RSPI2_RST>; 201 dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>; 202 dma-names = "tx", "rx"; 203 power-domains = <&cpg>; 204 num-cs = <1>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 status = "disabled"; 208 }; 209 210 scif0: serial@1004b800 { 211 compatible = "renesas,scif-r9a07g043", 212 "renesas,scif-r9a07g044"; 213 reg = <0 0x1004b800 0 0x400>; 214 interrupts = <SOC_PERIPHERAL_IRQ(380) IRQ_TYPE_LEVEL_HIGH>, 215 <SOC_PERIPHERAL_IRQ(382) IRQ_TYPE_LEVEL_HIGH>, 216 <SOC_PERIPHERAL_IRQ(383) IRQ_TYPE_LEVEL_HIGH>, 217 <SOC_PERIPHERAL_IRQ(381) IRQ_TYPE_LEVEL_HIGH>, 218 <SOC_PERIPHERAL_IRQ(384) IRQ_TYPE_LEVEL_HIGH>, 219 <SOC_PERIPHERAL_IRQ(384) IRQ_TYPE_LEVEL_HIGH>; 220 interrupt-names = "eri", "rxi", "txi", 221 "bri", "dri", "tei"; 222 clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; 223 clock-names = "fck"; 224 power-domains = <&cpg>; 225 resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>; 226 status = "disabled"; 227 }; 228 229 scif1: serial@1004bc00 { 230 compatible = "renesas,scif-r9a07g043", 231 "renesas,scif-r9a07g044"; 232 reg = <0 0x1004bc00 0 0x400>; 233 interrupts = <SOC_PERIPHERAL_IRQ(385) IRQ_TYPE_LEVEL_HIGH>, 234 <SOC_PERIPHERAL_IRQ(387) IRQ_TYPE_LEVEL_HIGH>, 235 <SOC_PERIPHERAL_IRQ(388) IRQ_TYPE_LEVEL_HIGH>, 236 <SOC_PERIPHERAL_IRQ(386) IRQ_TYPE_LEVEL_HIGH>, 237 <SOC_PERIPHERAL_IRQ(389) IRQ_TYPE_LEVEL_HIGH>, 238 <SOC_PERIPHERAL_IRQ(389) IRQ_TYPE_LEVEL_HIGH>; 239 interrupt-names = "eri", "rxi", "txi", 240 "bri", "dri", "tei"; 241 clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>; 242 clock-names = "fck"; 243 power-domains = <&cpg>; 244 resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>; 245 status = "disabled"; 246 }; 247 248 scif2: serial@1004c000 { 249 compatible = "renesas,scif-r9a07g043", 250 "renesas,scif-r9a07g044"; 251 reg = <0 0x1004c000 0 0x400>; 252 interrupts = <SOC_PERIPHERAL_IRQ(390) IRQ_TYPE_LEVEL_HIGH>, 253 <SOC_PERIPHERAL_IRQ(392) IRQ_TYPE_LEVEL_HIGH>, 254 <SOC_PERIPHERAL_IRQ(393) IRQ_TYPE_LEVEL_HIGH>, 255 <SOC_PERIPHERAL_IRQ(391) IRQ_TYPE_LEVEL_HIGH>, 256 <SOC_PERIPHERAL_IRQ(394) IRQ_TYPE_LEVEL_HIGH>, 257 <SOC_PERIPHERAL_IRQ(394) IRQ_TYPE_LEVEL_HIGH>; 258 interrupt-names = "eri", "rxi", "txi", 259 "bri", "dri", "tei"; 260 clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>; 261 clock-names = "fck"; 262 power-domains = <&cpg>; 263 resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>; 264 status = "disabled"; 265 }; 266 267 scif3: serial@1004c400 { 268 compatible = "renesas,scif-r9a07g043", 269 "renesas,scif-r9a07g044"; 270 reg = <0 0x1004c400 0 0x400>; 271 interrupts = <SOC_PERIPHERAL_IRQ(395) IRQ_TYPE_LEVEL_HIGH>, 272 <SOC_PERIPHERAL_IRQ(397) IRQ_TYPE_LEVEL_HIGH>, 273 <SOC_PERIPHERAL_IRQ(398) IRQ_TYPE_LEVEL_HIGH>, 274 <SOC_PERIPHERAL_IRQ(396) IRQ_TYPE_LEVEL_HIGH>, 275 <SOC_PERIPHERAL_IRQ(399) IRQ_TYPE_LEVEL_HIGH>, 276 <SOC_PERIPHERAL_IRQ(399) IRQ_TYPE_LEVEL_HIGH>; 277 interrupt-names = "eri", "rxi", "txi", 278 "bri", "dri", "tei"; 279 clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>; 280 clock-names = "fck"; 281 power-domains = <&cpg>; 282 resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>; 283 status = "disabled"; 284 }; 285 286 scif4: serial@1004c800 { 287 compatible = "renesas,scif-r9a07g043", 288 "renesas,scif-r9a07g044"; 289 reg = <0 0x1004c800 0 0x400>; 290 interrupts = <SOC_PERIPHERAL_IRQ(400) IRQ_TYPE_LEVEL_HIGH>, 291 <SOC_PERIPHERAL_IRQ(402) IRQ_TYPE_LEVEL_HIGH>, 292 <SOC_PERIPHERAL_IRQ(403) IRQ_TYPE_LEVEL_HIGH>, 293 <SOC_PERIPHERAL_IRQ(401) IRQ_TYPE_LEVEL_HIGH>, 294 <SOC_PERIPHERAL_IRQ(404) IRQ_TYPE_LEVEL_HIGH>, 295 <SOC_PERIPHERAL_IRQ(404) IRQ_TYPE_LEVEL_HIGH>; 296 interrupt-names = "eri", "rxi", "txi", 297 "bri", "dri", "tei"; 298 clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>; 299 clock-names = "fck"; 300 power-domains = <&cpg>; 301 resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>; 302 status = "disabled"; 303 }; 304 305 sci0: serial@1004d000 { 306 compatible = "renesas,r9a07g043-sci", "renesas,sci"; 307 reg = <0 0x1004d000 0 0x400>; 308 interrupts = <SOC_PERIPHERAL_IRQ(405) IRQ_TYPE_LEVEL_HIGH>, 309 <SOC_PERIPHERAL_IRQ(406) IRQ_TYPE_EDGE_RISING>, 310 <SOC_PERIPHERAL_IRQ(407) IRQ_TYPE_EDGE_RISING>, 311 <SOC_PERIPHERAL_IRQ(408) IRQ_TYPE_LEVEL_HIGH>; 312 interrupt-names = "eri", "rxi", "txi", "tei"; 313 clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>; 314 clock-names = "fck"; 315 power-domains = <&cpg>; 316 resets = <&cpg R9A07G043_SCI0_RST>; 317 status = "disabled"; 318 }; 319 320 sci1: serial@1004d400 { 321 compatible = "renesas,r9a07g043-sci", "renesas,sci"; 322 reg = <0 0x1004d400 0 0x400>; 323 interrupts = <SOC_PERIPHERAL_IRQ(409) IRQ_TYPE_LEVEL_HIGH>, 324 <SOC_PERIPHERAL_IRQ(410) IRQ_TYPE_EDGE_RISING>, 325 <SOC_PERIPHERAL_IRQ(411) IRQ_TYPE_EDGE_RISING>, 326 <SOC_PERIPHERAL_IRQ(412) IRQ_TYPE_LEVEL_HIGH>; 327 interrupt-names = "eri", "rxi", "txi", "tei"; 328 clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>; 329 clock-names = "fck"; 330 power-domains = <&cpg>; 331 resets = <&cpg R9A07G043_SCI1_RST>; 332 status = "disabled"; 333 }; 334 335 canfd: can@10050000 { 336 compatible = "renesas,r9a07g043-canfd", "renesas,rzg2l-canfd"; 337 reg = <0 0x10050000 0 0x8000>; 338 interrupts = <SOC_PERIPHERAL_IRQ(426) IRQ_TYPE_LEVEL_HIGH>, 339 <SOC_PERIPHERAL_IRQ(427) IRQ_TYPE_LEVEL_HIGH>, 340 <SOC_PERIPHERAL_IRQ(422) IRQ_TYPE_LEVEL_HIGH>, 341 <SOC_PERIPHERAL_IRQ(424) IRQ_TYPE_LEVEL_HIGH>, 342 <SOC_PERIPHERAL_IRQ(428) IRQ_TYPE_LEVEL_HIGH>, 343 <SOC_PERIPHERAL_IRQ(423) IRQ_TYPE_LEVEL_HIGH>, 344 <SOC_PERIPHERAL_IRQ(425) IRQ_TYPE_LEVEL_HIGH>, 345 <SOC_PERIPHERAL_IRQ(429) IRQ_TYPE_LEVEL_HIGH>; 346 interrupt-names = "g_err", "g_recc", 347 "ch0_err", "ch0_rec", "ch0_trx", 348 "ch1_err", "ch1_rec", "ch1_trx"; 349 clocks = <&cpg CPG_MOD R9A07G043_CANFD_PCLK>, 350 <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>, 351 <&can_clk>; 352 clock-names = "fck", "canfd", "can_clk"; 353 assigned-clocks = <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>; 354 assigned-clock-rates = <50000000>; 355 resets = <&cpg R9A07G043_CANFD_RSTP_N>, 356 <&cpg R9A07G043_CANFD_RSTC_N>; 357 reset-names = "rstp_n", "rstc_n"; 358 power-domains = <&cpg>; 359 status = "disabled"; 360 361 channel0 { 362 status = "disabled"; 363 }; 364 channel1 { 365 status = "disabled"; 366 }; 367 }; 368 369 i2c0: i2c@10058000 { 370 #address-cells = <1>; 371 #size-cells = <0>; 372 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 373 reg = <0 0x10058000 0 0x400>; 374 interrupts = <SOC_PERIPHERAL_IRQ(350) IRQ_TYPE_LEVEL_HIGH>, 375 <SOC_PERIPHERAL_IRQ(348) IRQ_TYPE_EDGE_RISING>, 376 <SOC_PERIPHERAL_IRQ(349) IRQ_TYPE_EDGE_RISING>, 377 <SOC_PERIPHERAL_IRQ(352) IRQ_TYPE_LEVEL_HIGH>, 378 <SOC_PERIPHERAL_IRQ(353) IRQ_TYPE_LEVEL_HIGH>, 379 <SOC_PERIPHERAL_IRQ(351) IRQ_TYPE_LEVEL_HIGH>, 380 <SOC_PERIPHERAL_IRQ(354) IRQ_TYPE_LEVEL_HIGH>, 381 <SOC_PERIPHERAL_IRQ(355) IRQ_TYPE_LEVEL_HIGH>; 382 interrupt-names = "tei", "ri", "ti", "spi", "sti", 383 "naki", "ali", "tmoi"; 384 clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>; 385 clock-frequency = <100000>; 386 resets = <&cpg R9A07G043_I2C0_MRST>; 387 power-domains = <&cpg>; 388 status = "disabled"; 389 }; 390 391 i2c1: i2c@10058400 { 392 #address-cells = <1>; 393 #size-cells = <0>; 394 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 395 reg = <0 0x10058400 0 0x400>; 396 interrupts = <SOC_PERIPHERAL_IRQ(358) IRQ_TYPE_LEVEL_HIGH>, 397 <SOC_PERIPHERAL_IRQ(356) IRQ_TYPE_EDGE_RISING>, 398 <SOC_PERIPHERAL_IRQ(357) IRQ_TYPE_EDGE_RISING>, 399 <SOC_PERIPHERAL_IRQ(360) IRQ_TYPE_LEVEL_HIGH>, 400 <SOC_PERIPHERAL_IRQ(361) IRQ_TYPE_LEVEL_HIGH>, 401 <SOC_PERIPHERAL_IRQ(359) IRQ_TYPE_LEVEL_HIGH>, 402 <SOC_PERIPHERAL_IRQ(362) IRQ_TYPE_LEVEL_HIGH>, 403 <SOC_PERIPHERAL_IRQ(363) IRQ_TYPE_LEVEL_HIGH>; 404 interrupt-names = "tei", "ri", "ti", "spi", "sti", 405 "naki", "ali", "tmoi"; 406 clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>; 407 clock-frequency = <100000>; 408 resets = <&cpg R9A07G043_I2C1_MRST>; 409 power-domains = <&cpg>; 410 status = "disabled"; 411 }; 412 413 i2c2: i2c@10058800 { 414 #address-cells = <1>; 415 #size-cells = <0>; 416 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 417 reg = <0 0x10058800 0 0x400>; 418 interrupts = <SOC_PERIPHERAL_IRQ(366) IRQ_TYPE_LEVEL_HIGH>, 419 <SOC_PERIPHERAL_IRQ(364) IRQ_TYPE_EDGE_RISING>, 420 <SOC_PERIPHERAL_IRQ(365) IRQ_TYPE_EDGE_RISING>, 421 <SOC_PERIPHERAL_IRQ(368) IRQ_TYPE_LEVEL_HIGH>, 422 <SOC_PERIPHERAL_IRQ(369) IRQ_TYPE_LEVEL_HIGH>, 423 <SOC_PERIPHERAL_IRQ(367) IRQ_TYPE_LEVEL_HIGH>, 424 <SOC_PERIPHERAL_IRQ(370) IRQ_TYPE_LEVEL_HIGH>, 425 <SOC_PERIPHERAL_IRQ(371) IRQ_TYPE_LEVEL_HIGH>; 426 interrupt-names = "tei", "ri", "ti", "spi", "sti", 427 "naki", "ali", "tmoi"; 428 clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>; 429 clock-frequency = <100000>; 430 resets = <&cpg R9A07G043_I2C2_MRST>; 431 power-domains = <&cpg>; 432 status = "disabled"; 433 }; 434 435 i2c3: i2c@10058c00 { 436 #address-cells = <1>; 437 #size-cells = <0>; 438 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 439 reg = <0 0x10058c00 0 0x400>; 440 interrupts = <SOC_PERIPHERAL_IRQ(374) IRQ_TYPE_LEVEL_HIGH>, 441 <SOC_PERIPHERAL_IRQ(372) IRQ_TYPE_EDGE_RISING>, 442 <SOC_PERIPHERAL_IRQ(373) IRQ_TYPE_EDGE_RISING>, 443 <SOC_PERIPHERAL_IRQ(376) IRQ_TYPE_LEVEL_HIGH>, 444 <SOC_PERIPHERAL_IRQ(377) IRQ_TYPE_LEVEL_HIGH>, 445 <SOC_PERIPHERAL_IRQ(375) IRQ_TYPE_LEVEL_HIGH>, 446 <SOC_PERIPHERAL_IRQ(378) IRQ_TYPE_LEVEL_HIGH>, 447 <SOC_PERIPHERAL_IRQ(379) IRQ_TYPE_LEVEL_HIGH>; 448 interrupt-names = "tei", "ri", "ti", "spi", "sti", 449 "naki", "ali", "tmoi"; 450 clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>; 451 clock-frequency = <100000>; 452 resets = <&cpg R9A07G043_I2C3_MRST>; 453 power-domains = <&cpg>; 454 status = "disabled"; 455 }; 456 457 adc: adc@10059000 { 458 compatible = "renesas,r9a07g043-adc", "renesas,rzg2l-adc"; 459 reg = <0 0x10059000 0 0x400>; 460 interrupts = <SOC_PERIPHERAL_IRQ(347) IRQ_TYPE_EDGE_RISING>; 461 clocks = <&cpg CPG_MOD R9A07G043_ADC_ADCLK>, 462 <&cpg CPG_MOD R9A07G043_ADC_PCLK>; 463 clock-names = "adclk", "pclk"; 464 resets = <&cpg R9A07G043_ADC_PRESETN>, 465 <&cpg R9A07G043_ADC_ADRST_N>; 466 reset-names = "presetn", "adrst-n"; 467 power-domains = <&cpg>; 468 status = "disabled"; 469 470 #address-cells = <1>; 471 #size-cells = <0>; 472 473 channel@0 { 474 reg = <0>; 475 }; 476 channel@1 { 477 reg = <1>; 478 }; 479 }; 480 481 tsu: thermal@10059400 { 482 compatible = "renesas,r9a07g043-tsu", 483 "renesas,rzg2l-tsu"; 484 reg = <0 0x10059400 0 0x400>; 485 clocks = <&cpg CPG_MOD R9A07G043_TSU_PCLK>; 486 resets = <&cpg R9A07G043_TSU_PRESETN>; 487 power-domains = <&cpg>; 488 #thermal-sensor-cells = <1>; 489 }; 490 491 sbc: spi@10060000 { 492 compatible = "renesas,r9a07g043-rpc-if", 493 "renesas,rzg2l-rpc-if"; 494 reg = <0 0x10060000 0 0x10000>, 495 <0 0x20000000 0 0x10000000>, 496 <0 0x10070000 0 0x10000>; 497 reg-names = "regs", "dirmap", "wbuf"; 498 clocks = <&cpg CPG_MOD R9A07G043_SPI_CLK2>, 499 <&cpg CPG_MOD R9A07G043_SPI_CLK>; 500 resets = <&cpg R9A07G043_SPI_RST>; 501 power-domains = <&cpg>; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 status = "disabled"; 505 }; 506 507 cpg: clock-controller@11010000 { 508 compatible = "renesas,r9a07g043-cpg"; 509 reg = <0 0x11010000 0 0x10000>; 510 clocks = <&extal_clk>; 511 clock-names = "extal"; 512 #clock-cells = <2>; 513 #reset-cells = <1>; 514 #power-domain-cells = <0>; 515 }; 516 517 sysc: system-controller@11020000 { 518 compatible = "renesas,r9a07g043-sysc"; 519 reg = <0 0x11020000 0 0x10000>; 520 status = "disabled"; 521 }; 522 523 pinctrl: pinctrl@11030000 { 524 compatible = "renesas,r9a07g043-pinctrl"; 525 reg = <0 0x11030000 0 0x10000>; 526 gpio-controller; 527 #gpio-cells = <2>; 528 gpio-ranges = <&pinctrl 0 0 152>; 529 #interrupt-cells = <2>; 530 interrupt-controller; 531 clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; 532 power-domains = <&cpg>; 533 resets = <&cpg R9A07G043_GPIO_RSTN>, 534 <&cpg R9A07G043_GPIO_PORT_RESETN>, 535 <&cpg R9A07G043_GPIO_SPARE_RESETN>; 536 }; 537 538 dmac: dma-controller@11820000 { 539 compatible = "renesas,r9a07g043-dmac", 540 "renesas,rz-dmac"; 541 reg = <0 0x11820000 0 0x10000>, 542 <0 0x11830000 0 0x10000>; 543 interrupts = <SOC_PERIPHERAL_IRQ(141) IRQ_TYPE_EDGE_RISING>, 544 <SOC_PERIPHERAL_IRQ(125) IRQ_TYPE_EDGE_RISING>, 545 <SOC_PERIPHERAL_IRQ(126) IRQ_TYPE_EDGE_RISING>, 546 <SOC_PERIPHERAL_IRQ(127) IRQ_TYPE_EDGE_RISING>, 547 <SOC_PERIPHERAL_IRQ(128) IRQ_TYPE_EDGE_RISING>, 548 <SOC_PERIPHERAL_IRQ(129) IRQ_TYPE_EDGE_RISING>, 549 <SOC_PERIPHERAL_IRQ(130) IRQ_TYPE_EDGE_RISING>, 550 <SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_EDGE_RISING>, 551 <SOC_PERIPHERAL_IRQ(132) IRQ_TYPE_EDGE_RISING>, 552 <SOC_PERIPHERAL_IRQ(133) IRQ_TYPE_EDGE_RISING>, 553 <SOC_PERIPHERAL_IRQ(134) IRQ_TYPE_EDGE_RISING>, 554 <SOC_PERIPHERAL_IRQ(135) IRQ_TYPE_EDGE_RISING>, 555 <SOC_PERIPHERAL_IRQ(136) IRQ_TYPE_EDGE_RISING>, 556 <SOC_PERIPHERAL_IRQ(137) IRQ_TYPE_EDGE_RISING>, 557 <SOC_PERIPHERAL_IRQ(138) IRQ_TYPE_EDGE_RISING>, 558 <SOC_PERIPHERAL_IRQ(139) IRQ_TYPE_EDGE_RISING>, 559 <SOC_PERIPHERAL_IRQ(140) IRQ_TYPE_EDGE_RISING>; 560 interrupt-names = "error", 561 "ch0", "ch1", "ch2", "ch3", 562 "ch4", "ch5", "ch6", "ch7", 563 "ch8", "ch9", "ch10", "ch11", 564 "ch12", "ch13", "ch14", "ch15"; 565 clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>, 566 <&cpg CPG_MOD R9A07G043_DMAC_PCLK>; 567 clock-names = "main", "register"; 568 power-domains = <&cpg>; 569 resets = <&cpg R9A07G043_DMAC_ARESETN>, 570 <&cpg R9A07G043_DMAC_RST_ASYNC>; 571 reset-names = "arst", "rst_async"; 572 #dma-cells = <1>; 573 dma-channels = <16>; 574 }; 575 576 sdhi0: mmc@11c00000 { 577 compatible = "renesas,sdhi-r9a07g043", 578 "renesas,rcar-gen3-sdhi"; 579 reg = <0x0 0x11c00000 0 0x10000>; 580 interrupts = <SOC_PERIPHERAL_IRQ(104) IRQ_TYPE_LEVEL_HIGH>, 581 <SOC_PERIPHERAL_IRQ(105) IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>, 583 <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>, 584 <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>, 585 <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>; 586 clock-names = "core", "clkh", "cd", "aclk"; 587 resets = <&cpg R9A07G043_SDHI0_IXRST>; 588 power-domains = <&cpg>; 589 status = "disabled"; 590 }; 591 592 sdhi1: mmc@11c10000 { 593 compatible = "renesas,sdhi-r9a07g043", 594 "renesas,rcar-gen3-sdhi"; 595 reg = <0x0 0x11c10000 0 0x10000>; 596 interrupts = <SOC_PERIPHERAL_IRQ(106) IRQ_TYPE_LEVEL_HIGH>, 597 <SOC_PERIPHERAL_IRQ(107) IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>, 599 <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>, 600 <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>, 601 <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>; 602 clock-names = "core", "clkh", "cd", "aclk"; 603 resets = <&cpg R9A07G043_SDHI1_IXRST>; 604 power-domains = <&cpg>; 605 status = "disabled"; 606 }; 607 608 eth0: ethernet@11c20000 { 609 compatible = "renesas,r9a07g043-gbeth", 610 "renesas,rzg2l-gbeth"; 611 reg = <0 0x11c20000 0 0x10000>; 612 interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>, 613 <SOC_PERIPHERAL_IRQ(85) IRQ_TYPE_LEVEL_HIGH>, 614 <SOC_PERIPHERAL_IRQ(86) IRQ_TYPE_LEVEL_HIGH>; 615 interrupt-names = "mux", "fil", "arp_ns"; 616 phy-mode = "rgmii"; 617 clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>, 618 <&cpg CPG_MOD R9A07G043_ETH0_CLK_CHI>, 619 <&cpg CPG_CORE R9A07G043_CLK_HP>; 620 clock-names = "axi", "chi", "refclk"; 621 resets = <&cpg R9A07G043_ETH0_RST_HW_N>; 622 power-domains = <&cpg>; 623 #address-cells = <1>; 624 #size-cells = <0>; 625 status = "disabled"; 626 }; 627 628 eth1: ethernet@11c30000 { 629 compatible = "renesas,r9a07g043-gbeth", 630 "renesas,rzg2l-gbeth"; 631 reg = <0 0x11c30000 0 0x10000>; 632 interrupts = <SOC_PERIPHERAL_IRQ(87) IRQ_TYPE_LEVEL_HIGH>, 633 <SOC_PERIPHERAL_IRQ(88) IRQ_TYPE_LEVEL_HIGH>, 634 <SOC_PERIPHERAL_IRQ(89) IRQ_TYPE_LEVEL_HIGH>; 635 interrupt-names = "mux", "fil", "arp_ns"; 636 phy-mode = "rgmii"; 637 clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>, 638 <&cpg CPG_MOD R9A07G043_ETH1_CLK_CHI>, 639 <&cpg CPG_CORE R9A07G043_CLK_HP>; 640 clock-names = "axi", "chi", "refclk"; 641 resets = <&cpg R9A07G043_ETH1_RST_HW_N>; 642 power-domains = <&cpg>; 643 #address-cells = <1>; 644 #size-cells = <0>; 645 status = "disabled"; 646 }; 647 648 phyrst: usbphy-ctrl@11c40000 { 649 compatible = "renesas,r9a07g043-usbphy-ctrl", 650 "renesas,rzg2l-usbphy-ctrl"; 651 reg = <0 0x11c40000 0 0x10000>; 652 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>; 653 resets = <&cpg R9A07G043_USB_PRESETN>; 654 power-domains = <&cpg>; 655 #reset-cells = <1>; 656 status = "disabled"; 657 }; 658 659 ohci0: usb@11c50000 { 660 compatible = "generic-ohci"; 661 reg = <0 0x11c50000 0 0x100>; 662 interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>; 663 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 664 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; 665 resets = <&phyrst 0>, 666 <&cpg R9A07G043_USB_U2H0_HRESETN>; 667 phys = <&usb2_phy0 1>; 668 phy-names = "usb"; 669 power-domains = <&cpg>; 670 status = "disabled"; 671 }; 672 673 ohci1: usb@11c70000 { 674 compatible = "generic-ohci"; 675 reg = <0 0x11c70000 0 0x100>; 676 interrupts = <SOC_PERIPHERAL_IRQ(96) IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 678 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; 679 resets = <&phyrst 1>, 680 <&cpg R9A07G043_USB_U2H1_HRESETN>; 681 phys = <&usb2_phy1 1>; 682 phy-names = "usb"; 683 power-domains = <&cpg>; 684 status = "disabled"; 685 }; 686 687 ehci0: usb@11c50100 { 688 compatible = "generic-ehci"; 689 reg = <0 0x11c50100 0 0x100>; 690 interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>; 691 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 692 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; 693 resets = <&phyrst 0>, 694 <&cpg R9A07G043_USB_U2H0_HRESETN>; 695 phys = <&usb2_phy0 2>; 696 phy-names = "usb"; 697 companion = <&ohci0>; 698 power-domains = <&cpg>; 699 status = "disabled"; 700 }; 701 702 ehci1: usb@11c70100 { 703 compatible = "generic-ehci"; 704 reg = <0 0x11c70100 0 0x100>; 705 interrupts = <SOC_PERIPHERAL_IRQ(97) IRQ_TYPE_LEVEL_HIGH>; 706 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 707 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; 708 resets = <&phyrst 1>, 709 <&cpg R9A07G043_USB_U2H1_HRESETN>; 710 phys = <&usb2_phy1 2>; 711 phy-names = "usb"; 712 companion = <&ohci1>; 713 power-domains = <&cpg>; 714 status = "disabled"; 715 }; 716 717 usb2_phy0: usb-phy@11c50200 { 718 compatible = "renesas,usb2-phy-r9a07g043", 719 "renesas,rzg2l-usb2-phy"; 720 reg = <0 0x11c50200 0 0x700>; 721 interrupts = <SOC_PERIPHERAL_IRQ(94) IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 723 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; 724 resets = <&phyrst 0>; 725 #phy-cells = <1>; 726 power-domains = <&cpg>; 727 status = "disabled"; 728 }; 729 730 usb2_phy1: usb-phy@11c70200 { 731 compatible = "renesas,usb2-phy-r9a07g043", 732 "renesas,rzg2l-usb2-phy"; 733 reg = <0 0x11c70200 0 0x700>; 734 interrupts = <SOC_PERIPHERAL_IRQ(99) IRQ_TYPE_LEVEL_HIGH>; 735 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 736 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; 737 resets = <&phyrst 1>; 738 #phy-cells = <1>; 739 power-domains = <&cpg>; 740 status = "disabled"; 741 }; 742 743 hsusb: usb@11c60000 { 744 compatible = "renesas,usbhs-r9a07g043", 745 "renesas,rza2-usbhs"; 746 reg = <0 0x11c60000 0 0x10000>; 747 interrupts = <SOC_PERIPHERAL_IRQ(100) IRQ_TYPE_EDGE_RISING>, 748 <SOC_PERIPHERAL_IRQ(101) IRQ_TYPE_LEVEL_HIGH>, 749 <SOC_PERIPHERAL_IRQ(102) IRQ_TYPE_LEVEL_HIGH>, 750 <SOC_PERIPHERAL_IRQ(103) IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 752 <&cpg CPG_MOD R9A07G043_USB_U2P_EXR_CPUCLK>; 753 resets = <&phyrst 0>, 754 <&cpg R9A07G043_USB_U2P_EXL_SYSRST>; 755 renesas,buswait = <7>; 756 phys = <&usb2_phy0 3>; 757 phy-names = "usb"; 758 power-domains = <&cpg>; 759 status = "disabled"; 760 }; 761 762 wdt0: watchdog@12800800 { 763 compatible = "renesas,r9a07g043-wdt", 764 "renesas,rzg2l-wdt"; 765 reg = <0 0x12800800 0 0x400>; 766 clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>, 767 <&cpg CPG_MOD R9A07G043_WDT0_CLK>; 768 clock-names = "pclk", "oscclk"; 769 interrupts = <SOC_PERIPHERAL_IRQ(49) IRQ_TYPE_LEVEL_HIGH>, 770 <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>; 771 interrupt-names = "wdt", "perrout"; 772 resets = <&cpg R9A07G043_WDT0_PRESETN>; 773 power-domains = <&cpg>; 774 status = "disabled"; 775 }; 776 777 ostm0: timer@12801000 { 778 compatible = "renesas,r9a07g043-ostm", 779 "renesas,ostm"; 780 reg = <0x0 0x12801000 0x0 0x400>; 781 interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_EDGE_RISING>; 782 clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>; 783 resets = <&cpg R9A07G043_OSTM0_PRESETZ>; 784 power-domains = <&cpg>; 785 status = "disabled"; 786 }; 787 788 ostm1: timer@12801400 { 789 compatible = "renesas,r9a07g043-ostm", 790 "renesas,ostm"; 791 reg = <0x0 0x12801400 0x0 0x400>; 792 interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_EDGE_RISING>; 793 clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>; 794 resets = <&cpg R9A07G043_OSTM1_PRESETZ>; 795 power-domains = <&cpg>; 796 status = "disabled"; 797 }; 798 799 ostm2: timer@12801800 { 800 compatible = "renesas,r9a07g043-ostm", 801 "renesas,ostm"; 802 reg = <0x0 0x12801800 0x0 0x400>; 803 interrupts = <SOC_PERIPHERAL_IRQ(48) IRQ_TYPE_EDGE_RISING>; 804 clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>; 805 resets = <&cpg R9A07G043_OSTM2_PRESETZ>; 806 power-domains = <&cpg>; 807 status = "disabled"; 808 }; 809 }; 810 811 thermal-zones { 812 cpu-thermal { 813 polling-delay-passive = <250>; 814 polling-delay = <1000>; 815 thermal-sensors = <&tsu 0>; 816 sustainable-power = <717>; 817 818 cooling-maps { 819 map0 { 820 trip = <&target>; 821 cooling-device = <&cpu0 0 2>; 822 contribution = <1024>; 823 }; 824 }; 825 826 trips { 827 sensor_crit: sensor-crit { 828 temperature = <125000>; 829 hysteresis = <1000>; 830 type = "critical"; 831 }; 832 833 target: trip-point { 834 temperature = <100000>; 835 hysteresis = <1000>; 836 type = "passive"; 837 }; 838 }; 839 }; 840 }; 841}; 842