1*71e90034SNguyen Tran// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*71e90034SNguyen Tran/* 3*71e90034SNguyen Tran * Device Tree Source for the Geist board with R-Car M3Le 4*71e90034SNguyen Tran * 5*71e90034SNguyen Tran * Copyright (C) 2025-2026 Renesas Electronics Corp. 6*71e90034SNguyen Tran */ 7*71e90034SNguyen Tran 8*71e90034SNguyen Tran/dts-v1/; 9*71e90034SNguyen Tran#include <dt-bindings/gpio/gpio.h> 10*71e90034SNguyen Tran#include <dt-bindings/input/input.h> 11*71e90034SNguyen Tran#include "r8a779md.dtsi" 12*71e90034SNguyen Tran 13*71e90034SNguyen Tran/ { 14*71e90034SNguyen Tran model = "Renesas Geist board based on r8a779md"; 15*71e90034SNguyen Tran compatible = "renesas,geist", "renesas,r8a779md", "renesas,r8a77965"; 16*71e90034SNguyen Tran 17*71e90034SNguyen Tran aliases { 18*71e90034SNguyen Tran serial0 = &scif2; 19*71e90034SNguyen Tran serial1 = &hscif1; 20*71e90034SNguyen Tran ethernet0 = &avb; 21*71e90034SNguyen Tran mmc0 = &sdhi2; 22*71e90034SNguyen Tran mmc1 = &sdhi0; 23*71e90034SNguyen Tran }; 24*71e90034SNguyen Tran 25*71e90034SNguyen Tran audio_clkout: audio-clkout { 26*71e90034SNguyen Tran /* 27*71e90034SNguyen Tran * This is same as <&rcar_sound 0> 28*71e90034SNguyen Tran * but needed to avoid cs2500/rcar_sound probe dead-lock 29*71e90034SNguyen Tran */ 30*71e90034SNguyen Tran compatible = "fixed-clock"; 31*71e90034SNguyen Tran #clock-cells = <0>; 32*71e90034SNguyen Tran clock-frequency = <12288000>; 33*71e90034SNguyen Tran }; 34*71e90034SNguyen Tran 35*71e90034SNguyen Tran backlight: backlight { 36*71e90034SNguyen Tran compatible = "pwm-backlight"; 37*71e90034SNguyen Tran pwms = <&pwm1 0 50000>; 38*71e90034SNguyen Tran 39*71e90034SNguyen Tran brightness-levels = <256 128 64 16 8 4 0>; 40*71e90034SNguyen Tran default-brightness-level = <6>; 41*71e90034SNguyen Tran 42*71e90034SNguyen Tran power-supply = <®_12v>; 43*71e90034SNguyen Tran enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; 44*71e90034SNguyen Tran }; 45*71e90034SNguyen Tran 46*71e90034SNguyen Tran chosen { 47*71e90034SNguyen Tran bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 48*71e90034SNguyen Tran stdout-path = "serial0:115200n8"; 49*71e90034SNguyen Tran }; 50*71e90034SNguyen Tran 51*71e90034SNguyen Tran cvbs-in { 52*71e90034SNguyen Tran compatible = "composite-video-connector"; 53*71e90034SNguyen Tran label = "CVBS IN"; 54*71e90034SNguyen Tran 55*71e90034SNguyen Tran port { 56*71e90034SNguyen Tran cvbs_con: endpoint { 57*71e90034SNguyen Tran remote-endpoint = <&adv7482_ain7>; 58*71e90034SNguyen Tran }; 59*71e90034SNguyen Tran }; 60*71e90034SNguyen Tran }; 61*71e90034SNguyen Tran 62*71e90034SNguyen Tran hdmi-in { 63*71e90034SNguyen Tran compatible = "hdmi-connector"; 64*71e90034SNguyen Tran label = "HDMI IN"; 65*71e90034SNguyen Tran type = "a"; 66*71e90034SNguyen Tran 67*71e90034SNguyen Tran port { 68*71e90034SNguyen Tran hdmi_in_con: endpoint { 69*71e90034SNguyen Tran remote-endpoint = <&adv7482_hdmi>; 70*71e90034SNguyen Tran }; 71*71e90034SNguyen Tran }; 72*71e90034SNguyen Tran }; 73*71e90034SNguyen Tran 74*71e90034SNguyen Tran keys { 75*71e90034SNguyen Tran compatible = "gpio-keys"; 76*71e90034SNguyen Tran 77*71e90034SNguyen Tran pinctrl-0 = <&keys_pins>; 78*71e90034SNguyen Tran pinctrl-names = "default"; 79*71e90034SNguyen Tran 80*71e90034SNguyen Tran key-1 { 81*71e90034SNguyen Tran gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; 82*71e90034SNguyen Tran linux,code = <KEY_1>; 83*71e90034SNguyen Tran label = "SW4-1"; 84*71e90034SNguyen Tran wakeup-source; 85*71e90034SNguyen Tran debounce-interval = <20>; 86*71e90034SNguyen Tran }; 87*71e90034SNguyen Tran 88*71e90034SNguyen Tran key-2 { 89*71e90034SNguyen Tran gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; 90*71e90034SNguyen Tran linux,code = <KEY_2>; 91*71e90034SNguyen Tran label = "SW4-2"; 92*71e90034SNguyen Tran wakeup-source; 93*71e90034SNguyen Tran debounce-interval = <20>; 94*71e90034SNguyen Tran }; 95*71e90034SNguyen Tran 96*71e90034SNguyen Tran key-3 { 97*71e90034SNguyen Tran gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; 98*71e90034SNguyen Tran linux,code = <KEY_3>; 99*71e90034SNguyen Tran label = "SW4-3"; 100*71e90034SNguyen Tran wakeup-source; 101*71e90034SNguyen Tran debounce-interval = <20>; 102*71e90034SNguyen Tran }; 103*71e90034SNguyen Tran 104*71e90034SNguyen Tran key-4 { 105*71e90034SNguyen Tran gpios = <&gpio5 23 GPIO_ACTIVE_LOW>; 106*71e90034SNguyen Tran linux,code = <KEY_4>; 107*71e90034SNguyen Tran label = "SW4-4"; 108*71e90034SNguyen Tran wakeup-source; 109*71e90034SNguyen Tran debounce-interval = <20>; 110*71e90034SNguyen Tran }; 111*71e90034SNguyen Tran 112*71e90034SNguyen Tran key-a { 113*71e90034SNguyen Tran gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; 114*71e90034SNguyen Tran linux,code = <KEY_A>; 115*71e90034SNguyen Tran label = "TSW0"; 116*71e90034SNguyen Tran wakeup-source; 117*71e90034SNguyen Tran debounce-interval = <20>; 118*71e90034SNguyen Tran }; 119*71e90034SNguyen Tran 120*71e90034SNguyen Tran key-b { 121*71e90034SNguyen Tran gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; 122*71e90034SNguyen Tran linux,code = <KEY_B>; 123*71e90034SNguyen Tran label = "TSW1"; 124*71e90034SNguyen Tran wakeup-source; 125*71e90034SNguyen Tran debounce-interval = <20>; 126*71e90034SNguyen Tran }; 127*71e90034SNguyen Tran 128*71e90034SNguyen Tran key-c { 129*71e90034SNguyen Tran gpios = <&gpio6 13 GPIO_ACTIVE_LOW>; 130*71e90034SNguyen Tran linux,code = <KEY_C>; 131*71e90034SNguyen Tran label = "TSW2"; 132*71e90034SNguyen Tran wakeup-source; 133*71e90034SNguyen Tran debounce-interval = <20>; 134*71e90034SNguyen Tran }; 135*71e90034SNguyen Tran }; 136*71e90034SNguyen Tran 137*71e90034SNguyen Tran memory@48000000 { 138*71e90034SNguyen Tran device_type = "memory"; 139*71e90034SNguyen Tran /* first 128MB is reserved for secure area. */ 140*71e90034SNguyen Tran reg = <0x0 0x48000000 0x0 0x78000000>; 141*71e90034SNguyen Tran }; 142*71e90034SNguyen Tran 143*71e90034SNguyen Tran memory@480000000 { 144*71e90034SNguyen Tran device_type = "memory"; 145*71e90034SNguyen Tran reg = <0x4 0x80000000 0x0 0x80000000>; 146*71e90034SNguyen Tran }; 147*71e90034SNguyen Tran 148*71e90034SNguyen Tran reg_1p8v: regulator-1p8v { 149*71e90034SNguyen Tran compatible = "regulator-fixed"; 150*71e90034SNguyen Tran regulator-name = "fixed-1.8V"; 151*71e90034SNguyen Tran regulator-min-microvolt = <1800000>; 152*71e90034SNguyen Tran regulator-max-microvolt = <1800000>; 153*71e90034SNguyen Tran regulator-boot-on; 154*71e90034SNguyen Tran regulator-always-on; 155*71e90034SNguyen Tran }; 156*71e90034SNguyen Tran 157*71e90034SNguyen Tran reg_3p3v: regulator-3p3v { 158*71e90034SNguyen Tran compatible = "regulator-fixed"; 159*71e90034SNguyen Tran regulator-name = "fixed-3.3V"; 160*71e90034SNguyen Tran regulator-min-microvolt = <3300000>; 161*71e90034SNguyen Tran regulator-max-microvolt = <3300000>; 162*71e90034SNguyen Tran regulator-boot-on; 163*71e90034SNguyen Tran regulator-always-on; 164*71e90034SNguyen Tran }; 165*71e90034SNguyen Tran 166*71e90034SNguyen Tran reg_12v: regulator-12v { 167*71e90034SNguyen Tran compatible = "regulator-fixed"; 168*71e90034SNguyen Tran regulator-name = "fixed-12V"; 169*71e90034SNguyen Tran regulator-min-microvolt = <12000000>; 170*71e90034SNguyen Tran regulator-max-microvolt = <12000000>; 171*71e90034SNguyen Tran regulator-boot-on; 172*71e90034SNguyen Tran regulator-always-on; 173*71e90034SNguyen Tran }; 174*71e90034SNguyen Tran 175*71e90034SNguyen Tran vbus0_usb2: regulator-vbus0-usb2 { 176*71e90034SNguyen Tran compatible = "regulator-fixed"; 177*71e90034SNguyen Tran 178*71e90034SNguyen Tran regulator-name = "USB20_VBUS0"; 179*71e90034SNguyen Tran regulator-min-microvolt = <5000000>; 180*71e90034SNguyen Tran regulator-max-microvolt = <5000000>; 181*71e90034SNguyen Tran 182*71e90034SNguyen Tran gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>; 183*71e90034SNguyen Tran enable-active-high; 184*71e90034SNguyen Tran }; 185*71e90034SNguyen Tran 186*71e90034SNguyen Tran vcc_sdhi0: regulator-vcc-sdhi0 { 187*71e90034SNguyen Tran compatible = "regulator-fixed"; 188*71e90034SNguyen Tran 189*71e90034SNguyen Tran regulator-name = "SDHI0 Vcc"; 190*71e90034SNguyen Tran regulator-min-microvolt = <3300000>; 191*71e90034SNguyen Tran regulator-max-microvolt = <3300000>; 192*71e90034SNguyen Tran 193*71e90034SNguyen Tran gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; 194*71e90034SNguyen Tran enable-active-high; 195*71e90034SNguyen Tran }; 196*71e90034SNguyen Tran 197*71e90034SNguyen Tran vccq_sdhi0: regulator-vccq-sdhi0 { 198*71e90034SNguyen Tran compatible = "regulator-gpio"; 199*71e90034SNguyen Tran 200*71e90034SNguyen Tran regulator-name = "SDHI0 VccQ"; 201*71e90034SNguyen Tran regulator-min-microvolt = <1800000>; 202*71e90034SNguyen Tran regulator-max-microvolt = <3300000>; 203*71e90034SNguyen Tran 204*71e90034SNguyen Tran gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; 205*71e90034SNguyen Tran gpios-states = <1>; 206*71e90034SNguyen Tran states = <3300000 1>, <1800000 0>; 207*71e90034SNguyen Tran }; 208*71e90034SNguyen Tran 209*71e90034SNguyen Tran sound_card: sound { 210*71e90034SNguyen Tran compatible = "audio-graph-card"; 211*71e90034SNguyen Tran 212*71e90034SNguyen Tran label = "rcar-sound"; 213*71e90034SNguyen Tran dais = <&rsnd_port0>; /* AK4619 Audio Codec */ 214*71e90034SNguyen Tran }; 215*71e90034SNguyen Tran 216*71e90034SNguyen Tran x12_clk: x12-clock { 217*71e90034SNguyen Tran compatible = "fixed-clock"; 218*71e90034SNguyen Tran #clock-cells = <0>; 219*71e90034SNguyen Tran clock-frequency = <24576000>; 220*71e90034SNguyen Tran }; 221*71e90034SNguyen Tran 222*71e90034SNguyen Tran /* External DU dot clocks */ 223*71e90034SNguyen Tran x21_clk: x21-clock { 224*71e90034SNguyen Tran compatible = "fixed-clock"; 225*71e90034SNguyen Tran #clock-cells = <0>; 226*71e90034SNguyen Tran clock-frequency = <33000000>; 227*71e90034SNguyen Tran }; 228*71e90034SNguyen Tran 229*71e90034SNguyen Tran x22_clk: x22-clock { 230*71e90034SNguyen Tran compatible = "fixed-clock"; 231*71e90034SNguyen Tran #clock-cells = <0>; 232*71e90034SNguyen Tran clock-frequency = <33000000>; 233*71e90034SNguyen Tran }; 234*71e90034SNguyen Tran 235*71e90034SNguyen Tran x23_clk: x23-clock { 236*71e90034SNguyen Tran compatible = "fixed-clock"; 237*71e90034SNguyen Tran #clock-cells = <0>; 238*71e90034SNguyen Tran clock-frequency = <25000000>; 239*71e90034SNguyen Tran }; 240*71e90034SNguyen Tran 241*71e90034SNguyen Tran x3013_clk: x3013-clock { 242*71e90034SNguyen Tran compatible = "fixed-clock"; 243*71e90034SNguyen Tran #clock-cells = <0>; 244*71e90034SNguyen Tran clock-frequency = <25000000>; 245*71e90034SNguyen Tran }; 246*71e90034SNguyen Tran}; 247*71e90034SNguyen Tran 248*71e90034SNguyen Tran&audio_clk_a { 249*71e90034SNguyen Tran clock-frequency = <22579200>; 250*71e90034SNguyen Tran}; 251*71e90034SNguyen Tran 252*71e90034SNguyen Tran&avb { 253*71e90034SNguyen Tran pinctrl-0 = <&avb_pins>; 254*71e90034SNguyen Tran pinctrl-names = "default"; 255*71e90034SNguyen Tran phy-handle = <&phy0>; 256*71e90034SNguyen Tran tx-internal-delay-ps = <2000>; 257*71e90034SNguyen Tran status = "okay"; 258*71e90034SNguyen Tran 259*71e90034SNguyen Tran phy0: ethernet-phy@0 { 260*71e90034SNguyen Tran compatible = "ethernet-phy-id0022.1622"; 261*71e90034SNguyen Tran rxc-skew-ps = <1500>; 262*71e90034SNguyen Tran reg = <0>; 263*71e90034SNguyen Tran interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>; 264*71e90034SNguyen Tran reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; 265*71e90034SNguyen Tran reset-assert-us = <10000>; 266*71e90034SNguyen Tran reset-deassert-us = <300>; 267*71e90034SNguyen Tran }; 268*71e90034SNguyen Tran}; 269*71e90034SNguyen Tran 270*71e90034SNguyen Tran&csi40 { 271*71e90034SNguyen Tran status = "okay"; 272*71e90034SNguyen Tran 273*71e90034SNguyen Tran ports { 274*71e90034SNguyen Tran port@0 { 275*71e90034SNguyen Tran csi40_in: endpoint { 276*71e90034SNguyen Tran clock-lanes = <0>; 277*71e90034SNguyen Tran data-lanes = <1 2 3 4>; 278*71e90034SNguyen Tran remote-endpoint = <&adv7482_txa>; 279*71e90034SNguyen Tran }; 280*71e90034SNguyen Tran }; 281*71e90034SNguyen Tran }; 282*71e90034SNguyen Tran}; 283*71e90034SNguyen Tran 284*71e90034SNguyen Tran&ehci0 { 285*71e90034SNguyen Tran dr_mode = "otg"; 286*71e90034SNguyen Tran status = "okay"; 287*71e90034SNguyen Tran}; 288*71e90034SNguyen Tran 289*71e90034SNguyen Tran&extalr_clk { 290*71e90034SNguyen Tran clock-frequency = <32768>; 291*71e90034SNguyen Tran}; 292*71e90034SNguyen Tran 293*71e90034SNguyen Tran&extal_clk { 294*71e90034SNguyen Tran clock-frequency = <16666666>; 295*71e90034SNguyen Tran}; 296*71e90034SNguyen Tran 297*71e90034SNguyen Tran&hscif1 { 298*71e90034SNguyen Tran pinctrl-0 = <&hscif1_pins>; 299*71e90034SNguyen Tran pinctrl-names = "default"; 300*71e90034SNguyen Tran 301*71e90034SNguyen Tran uart-has-rtscts; 302*71e90034SNguyen Tran /* Please only enable hscif1 or scif1 */ 303*71e90034SNguyen Tran status = "okay"; 304*71e90034SNguyen Tran}; 305*71e90034SNguyen Tran 306*71e90034SNguyen Tran&hsusb { 307*71e90034SNguyen Tran dr_mode = "otg"; 308*71e90034SNguyen Tran status = "okay"; 309*71e90034SNguyen Tran}; 310*71e90034SNguyen Tran 311*71e90034SNguyen Tran&i2c2 { 312*71e90034SNguyen Tran pinctrl-0 = <&i2c2_pins>; 313*71e90034SNguyen Tran pinctrl-names = "default"; 314*71e90034SNguyen Tran clock-frequency = <100000>; 315*71e90034SNguyen Tran status = "okay"; 316*71e90034SNguyen Tran 317*71e90034SNguyen Tran ak4619: codec@10 { 318*71e90034SNguyen Tran compatible = "asahi-kasei,ak4619"; 319*71e90034SNguyen Tran reg = <0x10>; 320*71e90034SNguyen Tran clocks = <&rcar_sound 3>; 321*71e90034SNguyen Tran clock-names = "mclk"; 322*71e90034SNguyen Tran #sound-dai-cells = <0>; 323*71e90034SNguyen Tran 324*71e90034SNguyen Tran port { 325*71e90034SNguyen Tran ak4619_endpoint: endpoint { 326*71e90034SNguyen Tran remote-endpoint = <&rsnd_endpoint0>; 327*71e90034SNguyen Tran }; 328*71e90034SNguyen Tran }; 329*71e90034SNguyen Tran }; 330*71e90034SNguyen Tran 331*71e90034SNguyen Tran /* Pin-to-pin, register map, and control compatible with CS2000 and CS2200 */ 332*71e90034SNguyen Tran cs2500: clock-controller@4f { 333*71e90034SNguyen Tran #clock-cells = <0>; 334*71e90034SNguyen Tran compatible = "cirrus,cs2500", "cirrus,cs2000-cp"; 335*71e90034SNguyen Tran reg = <0x4f>; 336*71e90034SNguyen Tran clocks = <&audio_clkout>, <&x12_clk>; 337*71e90034SNguyen Tran clock-names = "clk_in", "ref_clk"; 338*71e90034SNguyen Tran 339*71e90034SNguyen Tran assigned-clocks = <&cs2500>; 340*71e90034SNguyen Tran assigned-clock-rates = <24576000>; /* 1/1 divide */ 341*71e90034SNguyen Tran }; 342*71e90034SNguyen Tran}; 343*71e90034SNguyen Tran 344*71e90034SNguyen Tran&i2c4 { 345*71e90034SNguyen Tran clock-frequency = <400000>; 346*71e90034SNguyen Tran status = "okay"; 347*71e90034SNguyen Tran 348*71e90034SNguyen Tran versaclock3: clock-controller@68 { 349*71e90034SNguyen Tran compatible = "renesas,5p35023"; 350*71e90034SNguyen Tran reg = <0x68>; 351*71e90034SNguyen Tran #clock-cells = <1>; 352*71e90034SNguyen Tran clocks = <&x3013_clk>; 353*71e90034SNguyen Tran assigned-clocks = <&versaclock3 4>, <&versaclock3 5>; 354*71e90034SNguyen Tran assigned-clock-rates = <100000000>, <100000000>; 355*71e90034SNguyen Tran }; 356*71e90034SNguyen Tran 357*71e90034SNguyen Tran versaclock5: clock-controller@6a { 358*71e90034SNguyen Tran compatible = "idt,5p49v5923"; 359*71e90034SNguyen Tran reg = <0x6a>; 360*71e90034SNguyen Tran #clock-cells = <1>; 361*71e90034SNguyen Tran clocks = <&x23_clk>; 362*71e90034SNguyen Tran clock-names = "xin"; 363*71e90034SNguyen Tran }; 364*71e90034SNguyen Tran 365*71e90034SNguyen Tran video-receiver@70 { 366*71e90034SNguyen Tran compatible = "adi,adv7482"; 367*71e90034SNguyen Tran reg = <0x70 0x71 0x72 0x73 0x74 0x75 368*71e90034SNguyen Tran 0x60 0x61 0x62 0x63 0x64 0x65>; 369*71e90034SNguyen Tran reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater", 370*71e90034SNguyen Tran "infoframe", "cbus", "cec", "sdp", "txa", "txb" ; 371*71e90034SNguyen Tran 372*71e90034SNguyen Tran interrupts-extended = <&gpio6 30 IRQ_TYPE_LEVEL_LOW>, 373*71e90034SNguyen Tran <&gpio6 31 IRQ_TYPE_LEVEL_LOW>; 374*71e90034SNguyen Tran interrupt-names = "intrq1", "intrq2"; 375*71e90034SNguyen Tran 376*71e90034SNguyen Tran ports { 377*71e90034SNguyen Tran #address-cells = <1>; 378*71e90034SNguyen Tran #size-cells = <0>; 379*71e90034SNguyen Tran 380*71e90034SNguyen Tran port@7 { 381*71e90034SNguyen Tran reg = <7>; 382*71e90034SNguyen Tran 383*71e90034SNguyen Tran adv7482_ain7: endpoint { 384*71e90034SNguyen Tran remote-endpoint = <&cvbs_con>; 385*71e90034SNguyen Tran }; 386*71e90034SNguyen Tran }; 387*71e90034SNguyen Tran 388*71e90034SNguyen Tran port@8 { 389*71e90034SNguyen Tran reg = <8>; 390*71e90034SNguyen Tran 391*71e90034SNguyen Tran adv7482_hdmi: endpoint { 392*71e90034SNguyen Tran remote-endpoint = <&hdmi_in_con>; 393*71e90034SNguyen Tran }; 394*71e90034SNguyen Tran }; 395*71e90034SNguyen Tran 396*71e90034SNguyen Tran port@a { 397*71e90034SNguyen Tran reg = <10>; 398*71e90034SNguyen Tran 399*71e90034SNguyen Tran adv7482_txa: endpoint { 400*71e90034SNguyen Tran clock-lanes = <0>; 401*71e90034SNguyen Tran data-lanes = <1 2 3 4>; 402*71e90034SNguyen Tran remote-endpoint = <&csi40_in>; 403*71e90034SNguyen Tran }; 404*71e90034SNguyen Tran }; 405*71e90034SNguyen Tran }; 406*71e90034SNguyen Tran }; 407*71e90034SNguyen Tran 408*71e90034SNguyen Tran csa_vdd: adc@7c { 409*71e90034SNguyen Tran compatible = "maxim,max9611"; 410*71e90034SNguyen Tran reg = <0x7c>; 411*71e90034SNguyen Tran 412*71e90034SNguyen Tran shunt-resistor-micro-ohms = <5000>; 413*71e90034SNguyen Tran }; 414*71e90034SNguyen Tran 415*71e90034SNguyen Tran csa_dvfs: adc@7f { 416*71e90034SNguyen Tran compatible = "maxim,max9611"; 417*71e90034SNguyen Tran reg = <0x7f>; 418*71e90034SNguyen Tran 419*71e90034SNguyen Tran shunt-resistor-micro-ohms = <5000>; 420*71e90034SNguyen Tran }; 421*71e90034SNguyen Tran}; 422*71e90034SNguyen Tran 423*71e90034SNguyen Tran&i2c_dvfs { 424*71e90034SNguyen Tran status = "okay"; 425*71e90034SNguyen Tran 426*71e90034SNguyen Tran clock-frequency = <400000>; 427*71e90034SNguyen Tran 428*71e90034SNguyen Tran eeprom@50 { 429*71e90034SNguyen Tran compatible = "rohm,br24t01", "atmel,24c01"; 430*71e90034SNguyen Tran reg = <0x50>; 431*71e90034SNguyen Tran pagesize = <8>; 432*71e90034SNguyen Tran }; 433*71e90034SNguyen Tran}; 434*71e90034SNguyen Tran 435*71e90034SNguyen Tran&ohci0 { 436*71e90034SNguyen Tran dr_mode = "otg"; 437*71e90034SNguyen Tran status = "okay"; 438*71e90034SNguyen Tran}; 439*71e90034SNguyen Tran 440*71e90034SNguyen Tran&pcie_bus_clk { 441*71e90034SNguyen Tran status = "disabled"; 442*71e90034SNguyen Tran}; 443*71e90034SNguyen Tran 444*71e90034SNguyen Tran&pciec0 { 445*71e90034SNguyen Tran clocks = <&cpg CPG_MOD 319>, <&versaclock3 4>; 446*71e90034SNguyen Tran status = "okay"; 447*71e90034SNguyen Tran}; 448*71e90034SNguyen Tran 449*71e90034SNguyen Tran&pciec0_rp { 450*71e90034SNguyen Tran clocks = <&versaclock3 5>; 451*71e90034SNguyen Tran}; 452*71e90034SNguyen Tran 453*71e90034SNguyen Tran&pfc { 454*71e90034SNguyen Tran pinctrl-0 = <&scif_clk_pins>; 455*71e90034SNguyen Tran pinctrl-names = "default"; 456*71e90034SNguyen Tran 457*71e90034SNguyen Tran avb_pins: avb { 458*71e90034SNguyen Tran mux { 459*71e90034SNguyen Tran groups = "avb_link", "avb_mdio", "avb_mii"; 460*71e90034SNguyen Tran function = "avb"; 461*71e90034SNguyen Tran }; 462*71e90034SNguyen Tran 463*71e90034SNguyen Tran pins_mdio { 464*71e90034SNguyen Tran groups = "avb_mdio"; 465*71e90034SNguyen Tran drive-strength = <24>; 466*71e90034SNguyen Tran }; 467*71e90034SNguyen Tran 468*71e90034SNguyen Tran pins_mii_tx { 469*71e90034SNguyen Tran pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", 470*71e90034SNguyen Tran "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; 471*71e90034SNguyen Tran drive-strength = <12>; 472*71e90034SNguyen Tran }; 473*71e90034SNguyen Tran }; 474*71e90034SNguyen Tran 475*71e90034SNguyen Tran hscif1_pins: hscif1 { 476*71e90034SNguyen Tran groups = "hscif1_data_a", "hscif1_ctrl_a"; 477*71e90034SNguyen Tran function = "hscif1"; 478*71e90034SNguyen Tran }; 479*71e90034SNguyen Tran 480*71e90034SNguyen Tran i2c2_pins: i2c2 { 481*71e90034SNguyen Tran groups = "i2c2_a"; 482*71e90034SNguyen Tran function = "i2c2"; 483*71e90034SNguyen Tran }; 484*71e90034SNguyen Tran 485*71e90034SNguyen Tran irq0_pins: irq0 { 486*71e90034SNguyen Tran groups = "intc_ex_irq0"; 487*71e90034SNguyen Tran function = "intc_ex"; 488*71e90034SNguyen Tran }; 489*71e90034SNguyen Tran 490*71e90034SNguyen Tran keys_pins: keys { 491*71e90034SNguyen Tran pins = "GP_5_17", "GP_5_20", "GP_5_22"; 492*71e90034SNguyen Tran bias-pull-up; 493*71e90034SNguyen Tran }; 494*71e90034SNguyen Tran 495*71e90034SNguyen Tran pwm1_pins: pwm1 { 496*71e90034SNguyen Tran groups = "pwm1_a"; 497*71e90034SNguyen Tran function = "pwm1"; 498*71e90034SNguyen Tran }; 499*71e90034SNguyen Tran 500*71e90034SNguyen Tran scif1_pins: scif1 { 501*71e90034SNguyen Tran groups = "scif1_data_a", "scif1_ctrl"; 502*71e90034SNguyen Tran function = "scif1"; 503*71e90034SNguyen Tran }; 504*71e90034SNguyen Tran 505*71e90034SNguyen Tran scif2_pins: scif2 { 506*71e90034SNguyen Tran groups = "scif2_data_a"; 507*71e90034SNguyen Tran function = "scif2"; 508*71e90034SNguyen Tran }; 509*71e90034SNguyen Tran 510*71e90034SNguyen Tran scif_clk_pins: scif_clk { 511*71e90034SNguyen Tran groups = "scif_clk_a"; 512*71e90034SNguyen Tran function = "scif_clk"; 513*71e90034SNguyen Tran }; 514*71e90034SNguyen Tran 515*71e90034SNguyen Tran sdhi0_pins: sd0 { 516*71e90034SNguyen Tran groups = "sdhi0_data4", "sdhi0_ctrl"; 517*71e90034SNguyen Tran function = "sdhi0"; 518*71e90034SNguyen Tran power-source = <3300>; 519*71e90034SNguyen Tran }; 520*71e90034SNguyen Tran 521*71e90034SNguyen Tran sdhi0_pins_uhs: sd0_uhs { 522*71e90034SNguyen Tran groups = "sdhi0_data4", "sdhi0_ctrl"; 523*71e90034SNguyen Tran function = "sdhi0"; 524*71e90034SNguyen Tran power-source = <1800>; 525*71e90034SNguyen Tran }; 526*71e90034SNguyen Tran 527*71e90034SNguyen Tran sdhi2_pins: sd2 { 528*71e90034SNguyen Tran groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; 529*71e90034SNguyen Tran function = "sdhi2"; 530*71e90034SNguyen Tran power-source = <1800>; 531*71e90034SNguyen Tran }; 532*71e90034SNguyen Tran 533*71e90034SNguyen Tran sound_pins: sound { 534*71e90034SNguyen Tran groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; 535*71e90034SNguyen Tran function = "ssi"; 536*71e90034SNguyen Tran }; 537*71e90034SNguyen Tran 538*71e90034SNguyen Tran sound_clk_pins: sound_clk { 539*71e90034SNguyen Tran groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", 540*71e90034SNguyen Tran "audio_clkout_a", "audio_clkout3_a"; 541*71e90034SNguyen Tran function = "audio_clk"; 542*71e90034SNguyen Tran }; 543*71e90034SNguyen Tran 544*71e90034SNguyen Tran usb0_pins: usb0 { 545*71e90034SNguyen Tran groups = "usb0"; 546*71e90034SNguyen Tran function = "usb0"; 547*71e90034SNguyen Tran }; 548*71e90034SNguyen Tran}; 549*71e90034SNguyen Tran 550*71e90034SNguyen Tran&pwm1 { 551*71e90034SNguyen Tran pinctrl-0 = <&pwm1_pins>; 552*71e90034SNguyen Tran pinctrl-names = "default"; 553*71e90034SNguyen Tran 554*71e90034SNguyen Tran status = "okay"; 555*71e90034SNguyen Tran}; 556*71e90034SNguyen Tran 557*71e90034SNguyen Tran&rcar_sound { 558*71e90034SNguyen Tran pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; 559*71e90034SNguyen Tran pinctrl-names = "default"; 560*71e90034SNguyen Tran 561*71e90034SNguyen Tran /* Single DAI */ 562*71e90034SNguyen Tran #sound-dai-cells = <0>; 563*71e90034SNguyen Tran 564*71e90034SNguyen Tran /* audio_clkout0/1/2/3 */ 565*71e90034SNguyen Tran #clock-cells = <1>; 566*71e90034SNguyen Tran clock-frequency = <12288000 11289600>; 567*71e90034SNguyen Tran 568*71e90034SNguyen Tran status = "okay"; 569*71e90034SNguyen Tran 570*71e90034SNguyen Tran /* update <audio_clk_b> to <cs2500> */ 571*71e90034SNguyen Tran clocks = <&cpg CPG_MOD 1005>, 572*71e90034SNguyen Tran <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 573*71e90034SNguyen Tran <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 574*71e90034SNguyen Tran <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 575*71e90034SNguyen Tran <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 576*71e90034SNguyen Tran <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 577*71e90034SNguyen Tran <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 578*71e90034SNguyen Tran <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 579*71e90034SNguyen Tran <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 580*71e90034SNguyen Tran <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 581*71e90034SNguyen Tran <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 582*71e90034SNguyen Tran <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 583*71e90034SNguyen Tran <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 584*71e90034SNguyen Tran <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 585*71e90034SNguyen Tran <&audio_clk_a>, <&cs2500>, 586*71e90034SNguyen Tran <&audio_clk_c>, 587*71e90034SNguyen Tran <&cpg CPG_MOD 922>; 588*71e90034SNguyen Tran 589*71e90034SNguyen Tran ports { 590*71e90034SNguyen Tran #address-cells = <1>; 591*71e90034SNguyen Tran #size-cells = <0>; 592*71e90034SNguyen Tran 593*71e90034SNguyen Tran rsnd_port0: port@0 { 594*71e90034SNguyen Tran reg = <0>; 595*71e90034SNguyen Tran 596*71e90034SNguyen Tran rsnd_endpoint0: endpoint { 597*71e90034SNguyen Tran remote-endpoint = <&ak4619_endpoint>; 598*71e90034SNguyen Tran dai-format = "left_j"; 599*71e90034SNguyen Tran bitclock-master = <&rsnd_endpoint0>; 600*71e90034SNguyen Tran frame-master = <&rsnd_endpoint0>; 601*71e90034SNguyen Tran playback = <&ssi0>, <&src0>, <&dvc0>; 602*71e90034SNguyen Tran capture = <&ssi1>, <&src1>, <&dvc1>; 603*71e90034SNguyen Tran }; 604*71e90034SNguyen Tran }; 605*71e90034SNguyen Tran }; 606*71e90034SNguyen Tran}; 607*71e90034SNguyen Tran 608*71e90034SNguyen Tran&rwdt { 609*71e90034SNguyen Tran timeout-sec = <60>; 610*71e90034SNguyen Tran status = "okay"; 611*71e90034SNguyen Tran}; 612*71e90034SNguyen Tran 613*71e90034SNguyen Tran&scif1 { 614*71e90034SNguyen Tran pinctrl-0 = <&scif1_pins>; 615*71e90034SNguyen Tran pinctrl-names = "default"; 616*71e90034SNguyen Tran 617*71e90034SNguyen Tran uart-has-rtscts; 618*71e90034SNguyen Tran /* Please only enable hscif1 or scif1 */ 619*71e90034SNguyen Tran /* status = "okay"; */ 620*71e90034SNguyen Tran}; 621*71e90034SNguyen Tran 622*71e90034SNguyen Tran&scif2 { 623*71e90034SNguyen Tran pinctrl-0 = <&scif2_pins>; 624*71e90034SNguyen Tran pinctrl-names = "default"; 625*71e90034SNguyen Tran 626*71e90034SNguyen Tran status = "okay"; 627*71e90034SNguyen Tran}; 628*71e90034SNguyen Tran 629*71e90034SNguyen Tran&scif_clk { 630*71e90034SNguyen Tran clock-frequency = <14745600>; 631*71e90034SNguyen Tran}; 632*71e90034SNguyen Tran 633*71e90034SNguyen Tran&sdhi0 { 634*71e90034SNguyen Tran pinctrl-0 = <&sdhi0_pins>; 635*71e90034SNguyen Tran pinctrl-1 = <&sdhi0_pins_uhs>; 636*71e90034SNguyen Tran pinctrl-names = "default", "state_uhs"; 637*71e90034SNguyen Tran 638*71e90034SNguyen Tran vmmc-supply = <&vcc_sdhi0>; 639*71e90034SNguyen Tran vqmmc-supply = <&vccq_sdhi0>; 640*71e90034SNguyen Tran cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; 641*71e90034SNguyen Tran wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; 642*71e90034SNguyen Tran bus-width = <4>; 643*71e90034SNguyen Tran sd-uhs-sdr50; 644*71e90034SNguyen Tran sd-uhs-sdr104; 645*71e90034SNguyen Tran status = "okay"; 646*71e90034SNguyen Tran}; 647*71e90034SNguyen Tran 648*71e90034SNguyen Tran&sdhi2 { 649*71e90034SNguyen Tran /* used for on-board 8bit eMMC */ 650*71e90034SNguyen Tran pinctrl-0 = <&sdhi2_pins>; 651*71e90034SNguyen Tran pinctrl-1 = <&sdhi2_pins>; 652*71e90034SNguyen Tran pinctrl-names = "default", "state_uhs"; 653*71e90034SNguyen Tran 654*71e90034SNguyen Tran vmmc-supply = <®_3p3v>; 655*71e90034SNguyen Tran vqmmc-supply = <®_1p8v>; 656*71e90034SNguyen Tran bus-width = <8>; 657*71e90034SNguyen Tran mmc-hs200-1_8v; 658*71e90034SNguyen Tran no-sd; 659*71e90034SNguyen Tran no-sdio; 660*71e90034SNguyen Tran non-removable; 661*71e90034SNguyen Tran fixed-emmc-driver-type = <1>; 662*71e90034SNguyen Tran full-pwr-cycle-in-suspend; 663*71e90034SNguyen Tran status = "okay"; 664*71e90034SNguyen Tran}; 665*71e90034SNguyen Tran 666*71e90034SNguyen Tran&ssi1 { 667*71e90034SNguyen Tran shared-pin; 668*71e90034SNguyen Tran}; 669*71e90034SNguyen Tran 670*71e90034SNguyen Tran&usb_extal_clk { 671*71e90034SNguyen Tran clock-frequency = <50000000>; 672*71e90034SNguyen Tran}; 673*71e90034SNguyen Tran 674*71e90034SNguyen Tran&usb2_phy0 { 675*71e90034SNguyen Tran pinctrl-0 = <&usb0_pins>; 676*71e90034SNguyen Tran pinctrl-names = "default"; 677*71e90034SNguyen Tran 678*71e90034SNguyen Tran vbus-supply = <&vbus0_usb2>; 679*71e90034SNguyen Tran status = "okay"; 680*71e90034SNguyen Tran}; 681*71e90034SNguyen Tran 682*71e90034SNguyen Tran&vin0 { 683*71e90034SNguyen Tran status = "okay"; 684*71e90034SNguyen Tran}; 685*71e90034SNguyen Tran 686*71e90034SNguyen Tran&vin1 { 687*71e90034SNguyen Tran status = "okay"; 688*71e90034SNguyen Tran}; 689*71e90034SNguyen Tran 690*71e90034SNguyen Tran&vin2 { 691*71e90034SNguyen Tran status = "okay"; 692*71e90034SNguyen Tran}; 693*71e90034SNguyen Tran 694*71e90034SNguyen Tran&vin3 { 695*71e90034SNguyen Tran status = "okay"; 696*71e90034SNguyen Tran}; 697*71e90034SNguyen Tran 698*71e90034SNguyen Tran&vin4 { 699*71e90034SNguyen Tran status = "okay"; 700*71e90034SNguyen Tran}; 701*71e90034SNguyen Tran 702*71e90034SNguyen Tran&vin5 { 703*71e90034SNguyen Tran status = "okay"; 704*71e90034SNguyen Tran}; 705*71e90034SNguyen Tran 706*71e90034SNguyen Tran&vin6 { 707*71e90034SNguyen Tran status = "okay"; 708*71e90034SNguyen Tran}; 709*71e90034SNguyen Tran 710*71e90034SNguyen Tran&vin7 { 711*71e90034SNguyen Tran status = "okay"; 712*71e90034SNguyen Tran}; 713*71e90034SNguyen Tran 714*71e90034SNguyen Tran&vspb { 715*71e90034SNguyen Tran status = "okay"; 716*71e90034SNguyen Tran}; 717*71e90034SNguyen Tran 718*71e90034SNguyen Tran&vspi0 { 719*71e90034SNguyen Tran status = "okay"; 720*71e90034SNguyen Tran}; 721