1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the R-Car V4M (R8A779H0) SoC 4 * 5 * Copyright (C) 2023 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/renesas,r8a779h0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a779h0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cluster0_opp: opp-table-0 { 18 compatible = "operating-points-v2"; 19 opp-shared; 20 21 opp-500000000 { 22 opp-hz = /bits/ 64 <500000000>; 23 opp-microvolt = <825000>; 24 clock-latency-ns = <500000>; 25 }; 26 opp-1000000000 { 27 opp-hz = /bits/ 64 <1000000000>; 28 opp-microvolt = <825000>; 29 clock-latency-ns = <500000>; 30 }; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 cpu-map { 38 cluster0 { 39 core0 { 40 cpu = <&a76_0>; 41 }; 42 core1 { 43 cpu = <&a76_1>; 44 }; 45 core2 { 46 cpu = <&a76_2>; 47 }; 48 core3 { 49 cpu = <&a76_3>; 50 }; 51 }; 52 }; 53 54 a76_0: cpu@0 { 55 compatible = "arm,cortex-a76"; 56 reg = <0>; 57 device_type = "cpu"; 58 power-domains = <&sysc R8A779H0_PD_A1E0D0C0>; 59 next-level-cache = <&L3_CA76>; 60 enable-method = "psci"; 61 cpu-idle-states = <&CPU_SLEEP_0>; 62 clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC0>; 63 operating-points-v2 = <&cluster0_opp>; 64 }; 65 66 a76_1: cpu@100 { 67 compatible = "arm,cortex-a76"; 68 reg = <0x100>; 69 device_type = "cpu"; 70 power-domains = <&sysc R8A779H0_PD_A1E0D0C1>; 71 next-level-cache = <&L3_CA76>; 72 enable-method = "psci"; 73 cpu-idle-states = <&CPU_SLEEP_0>; 74 clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC1>; 75 operating-points-v2 = <&cluster0_opp>; 76 }; 77 78 a76_2: cpu@200 { 79 compatible = "arm,cortex-a76"; 80 reg = <0x200>; 81 device_type = "cpu"; 82 power-domains = <&sysc R8A779H0_PD_A1E0D0C2>; 83 next-level-cache = <&L3_CA76>; 84 enable-method = "psci"; 85 cpu-idle-states = <&CPU_SLEEP_0>; 86 clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC2>; 87 operating-points-v2 = <&cluster0_opp>; 88 }; 89 90 a76_3: cpu@300 { 91 compatible = "arm,cortex-a76"; 92 reg = <0x300>; 93 device_type = "cpu"; 94 power-domains = <&sysc R8A779H0_PD_A1E0D0C3>; 95 next-level-cache = <&L3_CA76>; 96 enable-method = "psci"; 97 cpu-idle-states = <&CPU_SLEEP_0>; 98 clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC3>; 99 operating-points-v2 = <&cluster0_opp>; 100 }; 101 102 idle-states { 103 entry-method = "psci"; 104 105 CPU_SLEEP_0: cpu-sleep-0 { 106 compatible = "arm,idle-state"; 107 arm,psci-suspend-param = <0x0010000>; 108 local-timer-stop; 109 entry-latency-us = <400>; 110 exit-latency-us = <500>; 111 min-residency-us = <4000>; 112 }; 113 }; 114 115 L3_CA76: cache-controller { 116 compatible = "cache"; 117 power-domains = <&sysc R8A779H0_PD_A2E0D0>; 118 cache-unified; 119 cache-level = <3>; 120 }; 121 }; 122 123 extal_clk: extal-clk { 124 compatible = "fixed-clock"; 125 #clock-cells = <0>; 126 /* This value must be overridden by the board */ 127 clock-frequency = <0>; 128 }; 129 130 extalr_clk: extalr-clk { 131 compatible = "fixed-clock"; 132 #clock-cells = <0>; 133 /* This value must be overridden by the board */ 134 clock-frequency = <0>; 135 }; 136 137 pmu-a76 { 138 compatible = "arm,cortex-a76-pmu"; 139 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 140 }; 141 142 psci { 143 compatible = "arm,psci-1.0", "arm,psci-0.2"; 144 method = "smc"; 145 }; 146 147 /* External SCIF clock - to be overridden by boards that provide it */ 148 scif_clk: scif-clk { 149 compatible = "fixed-clock"; 150 #clock-cells = <0>; 151 clock-frequency = <0>; 152 }; 153 154 soc: soc { 155 compatible = "simple-bus"; 156 interrupt-parent = <&gic>; 157 #address-cells = <2>; 158 #size-cells = <2>; 159 ranges; 160 161 rwdt: watchdog@e6020000 { 162 compatible = "renesas,r8a779h0-wdt", 163 "renesas,rcar-gen4-wdt"; 164 reg = <0 0xe6020000 0 0x0c>; 165 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 166 clocks = <&cpg CPG_MOD 907>; 167 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 168 resets = <&cpg 907>; 169 status = "disabled"; 170 }; 171 172 pfc: pinctrl@e6050000 { 173 compatible = "renesas,pfc-r8a779h0"; 174 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, 175 <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, 176 <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, 177 <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>; 178 }; 179 180 gpio0: gpio@e6050180 { 181 compatible = "renesas,gpio-r8a779h0", 182 "renesas,rcar-gen4-gpio"; 183 reg = <0 0xe6050180 0 0x54>; 184 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>; 185 #gpio-cells = <2>; 186 gpio-controller; 187 gpio-ranges = <&pfc 0 0 19>; 188 #interrupt-cells = <2>; 189 interrupt-controller; 190 clocks = <&cpg CPG_MOD 915>; 191 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 192 resets = <&cpg 915>; 193 }; 194 195 gpio1: gpio@e6050980 { 196 compatible = "renesas,gpio-r8a779h0", 197 "renesas,rcar-gen4-gpio"; 198 reg = <0 0xe6050980 0 0x54>; 199 interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>; 200 #gpio-cells = <2>; 201 gpio-controller; 202 gpio-ranges = <&pfc 0 32 30>; 203 #interrupt-cells = <2>; 204 interrupt-controller; 205 clocks = <&cpg CPG_MOD 915>; 206 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 207 resets = <&cpg 915>; 208 }; 209 210 gpio2: gpio@e6058180 { 211 compatible = "renesas,gpio-r8a779h0", 212 "renesas,rcar-gen4-gpio"; 213 reg = <0 0xe6058180 0 0x54>; 214 interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>; 215 #gpio-cells = <2>; 216 gpio-controller; 217 gpio-ranges = <&pfc 0 64 20>; 218 #interrupt-cells = <2>; 219 interrupt-controller; 220 clocks = <&cpg CPG_MOD 916>; 221 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 222 resets = <&cpg 916>; 223 }; 224 225 gpio3: gpio@e6058980 { 226 compatible = "renesas,gpio-r8a779h0", 227 "renesas,rcar-gen4-gpio"; 228 reg = <0 0xe6058980 0 0x54>; 229 interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>; 230 #gpio-cells = <2>; 231 gpio-controller; 232 gpio-ranges = <&pfc 0 96 32>; 233 #interrupt-cells = <2>; 234 interrupt-controller; 235 clocks = <&cpg CPG_MOD 916>; 236 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 237 resets = <&cpg 916>; 238 }; 239 240 gpio4: gpio@e6060180 { 241 compatible = "renesas,gpio-r8a779h0", 242 "renesas,rcar-gen4-gpio"; 243 reg = <0 0xe6060180 0 0x54>; 244 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>; 245 #gpio-cells = <2>; 246 gpio-controller; 247 gpio-ranges = <&pfc 0 128 25>; 248 #interrupt-cells = <2>; 249 interrupt-controller; 250 clocks = <&cpg CPG_MOD 917>; 251 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 252 resets = <&cpg 917>; 253 }; 254 255 gpio5: gpio@e6060980 { 256 compatible = "renesas,gpio-r8a779h0", 257 "renesas,rcar-gen4-gpio"; 258 reg = <0 0xe6060980 0 0x54>; 259 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>; 260 #gpio-cells = <2>; 261 gpio-controller; 262 gpio-ranges = <&pfc 0 160 21>; 263 #interrupt-cells = <2>; 264 interrupt-controller; 265 clocks = <&cpg CPG_MOD 917>; 266 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 267 resets = <&cpg 917>; 268 }; 269 270 gpio6: gpio@e6061180 { 271 compatible = "renesas,gpio-r8a779h0", 272 "renesas,rcar-gen4-gpio"; 273 reg = <0 0xe6061180 0 0x54>; 274 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>; 275 #gpio-cells = <2>; 276 gpio-controller; 277 gpio-ranges = <&pfc 0 192 21>; 278 #interrupt-cells = <2>; 279 interrupt-controller; 280 clocks = <&cpg CPG_MOD 917>; 281 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 282 resets = <&cpg 917>; 283 }; 284 285 gpio7: gpio@e6061980 { 286 compatible = "renesas,gpio-r8a779h0", 287 "renesas,rcar-gen4-gpio"; 288 reg = <0 0xe6061980 0 0x54>; 289 interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>; 290 #gpio-cells = <2>; 291 gpio-controller; 292 gpio-ranges = <&pfc 0 224 21>; 293 #interrupt-cells = <2>; 294 interrupt-controller; 295 clocks = <&cpg CPG_MOD 917>; 296 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 297 resets = <&cpg 917>; 298 }; 299 300 cpg: clock-controller@e6150000 { 301 compatible = "renesas,r8a779h0-cpg-mssr"; 302 reg = <0 0xe6150000 0 0x4000>; 303 clocks = <&extal_clk>, <&extalr_clk>; 304 clock-names = "extal", "extalr"; 305 #clock-cells = <2>; 306 #power-domain-cells = <0>; 307 #reset-cells = <1>; 308 }; 309 310 rst: reset-controller@e6160000 { 311 compatible = "renesas,r8a779h0-rst"; 312 reg = <0 0xe6160000 0 0x4000>; 313 }; 314 315 sysc: system-controller@e6180000 { 316 compatible = "renesas,r8a779h0-sysc"; 317 reg = <0 0xe6180000 0 0x4000>; 318 #power-domain-cells = <1>; 319 }; 320 321 i2c0: i2c@e6500000 { 322 compatible = "renesas,i2c-r8a779h0", 323 "renesas,rcar-gen4-i2c"; 324 reg = <0 0xe6500000 0 0x40>; 325 interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&cpg CPG_MOD 518>; 327 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 328 resets = <&cpg 518>; 329 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 330 <&dmac2 0x91>, <&dmac2 0x90>; 331 dma-names = "tx", "rx", "tx", "rx"; 332 i2c-scl-internal-delay-ns = <110>; 333 #address-cells = <1>; 334 #size-cells = <0>; 335 status = "disabled"; 336 }; 337 338 i2c1: i2c@e6508000 { 339 compatible = "renesas,i2c-r8a779h0", 340 "renesas,rcar-gen4-i2c"; 341 reg = <0 0xe6508000 0 0x40>; 342 interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&cpg CPG_MOD 519>; 344 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 345 resets = <&cpg 519>; 346 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 347 <&dmac2 0x93>, <&dmac2 0x92>; 348 dma-names = "tx", "rx", "tx", "rx"; 349 i2c-scl-internal-delay-ns = <110>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 status = "disabled"; 353 }; 354 355 i2c2: i2c@e6510000 { 356 compatible = "renesas,i2c-r8a779h0", 357 "renesas,rcar-gen4-i2c"; 358 reg = <0 0xe6510000 0 0x40>; 359 interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&cpg CPG_MOD 520>; 361 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 362 resets = <&cpg 520>; 363 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 364 <&dmac2 0x95>, <&dmac2 0x94>; 365 dma-names = "tx", "rx", "tx", "rx"; 366 i2c-scl-internal-delay-ns = <110>; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 status = "disabled"; 370 }; 371 372 i2c3: i2c@e66d0000 { 373 compatible = "renesas,i2c-r8a779h0", 374 "renesas,rcar-gen4-i2c"; 375 reg = <0 0xe66d0000 0 0x40>; 376 interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&cpg CPG_MOD 521>; 378 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 379 resets = <&cpg 521>; 380 dmas = <&dmac1 0x97>, <&dmac1 0x96>, 381 <&dmac2 0x97>, <&dmac2 0x96>; 382 dma-names = "tx", "rx", "tx", "rx"; 383 i2c-scl-internal-delay-ns = <110>; 384 #address-cells = <1>; 385 #size-cells = <0>; 386 status = "disabled"; 387 }; 388 389 hscif0: serial@e6540000 { 390 compatible = "renesas,hscif-r8a779h0", 391 "renesas,rcar-gen4-hscif", "renesas,hscif"; 392 reg = <0 0xe6540000 0 0x60>; 393 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&cpg CPG_MOD 514>, 395 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, 396 <&scif_clk>; 397 clock-names = "fck", "brg_int", "scif_clk"; 398 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 399 resets = <&cpg 514>; 400 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 401 <&dmac2 0x31>, <&dmac2 0x30>; 402 dma-names = "tx", "rx", "tx", "rx"; 403 status = "disabled"; 404 }; 405 406 avb0: ethernet@e6800000 { 407 compatible = "renesas,etheravb-r8a779h0", 408 "renesas,etheravb-rcar-gen4"; 409 reg = <0 0xe6800000 0 0x1000>; 410 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 435 interrupt-names = "ch0", "ch1", "ch2", "ch3", 436 "ch4", "ch5", "ch6", "ch7", 437 "ch8", "ch9", "ch10", "ch11", 438 "ch12", "ch13", "ch14", "ch15", 439 "ch16", "ch17", "ch18", "ch19", 440 "ch20", "ch21", "ch22", "ch23", 441 "ch24"; 442 clocks = <&cpg CPG_MOD 211>; 443 clock-names = "fck"; 444 power-domains = <&sysc R8A779H0_PD_C4>; 445 resets = <&cpg 211>; 446 phy-mode = "rgmii"; 447 rx-internal-delay-ps = <0>; 448 tx-internal-delay-ps = <0>; 449 #address-cells = <1>; 450 #size-cells = <0>; 451 status = "disabled"; 452 }; 453 454 avb1: ethernet@e6810000 { 455 compatible = "renesas,etheravb-r8a779h0", 456 "renesas,etheravb-rcar-gen4"; 457 reg = <0 0xe6810000 0 0x1000>; 458 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 483 interrupt-names = "ch0", "ch1", "ch2", "ch3", 484 "ch4", "ch5", "ch6", "ch7", 485 "ch8", "ch9", "ch10", "ch11", 486 "ch12", "ch13", "ch14", "ch15", 487 "ch16", "ch17", "ch18", "ch19", 488 "ch20", "ch21", "ch22", "ch23", 489 "ch24"; 490 clocks = <&cpg CPG_MOD 212>; 491 clock-names = "fck"; 492 power-domains = <&sysc R8A779H0_PD_C4>; 493 resets = <&cpg 212>; 494 phy-mode = "rgmii"; 495 rx-internal-delay-ps = <0>; 496 tx-internal-delay-ps = <0>; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 status = "disabled"; 500 }; 501 502 avb2: ethernet@e6820000 { 503 compatible = "renesas,etheravb-r8a779h0", 504 "renesas,etheravb-rcar-gen4"; 505 reg = <0 0xe6820000 0 0x1000>; 506 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 531 interrupt-names = "ch0", "ch1", "ch2", "ch3", 532 "ch4", "ch5", "ch6", "ch7", 533 "ch8", "ch9", "ch10", "ch11", 534 "ch12", "ch13", "ch14", "ch15", 535 "ch16", "ch17", "ch18", "ch19", 536 "ch20", "ch21", "ch22", "ch23", 537 "ch24"; 538 clocks = <&cpg CPG_MOD 213>; 539 clock-names = "fck"; 540 power-domains = <&sysc R8A779H0_PD_C4>; 541 resets = <&cpg 213>; 542 phy-mode = "rgmii"; 543 rx-internal-delay-ps = <0>; 544 tx-internal-delay-ps = <0>; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 status = "disabled"; 548 }; 549 550 dmac1: dma-controller@e7350000 { 551 compatible = "renesas,dmac-r8a779h0", 552 "renesas,rcar-gen4-dmac"; 553 reg = <0 0xe7350000 0 0x1000>, 554 <0 0xe7300000 0 0x10000>; 555 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 572 interrupt-names = "error", 573 "ch0", "ch1", "ch2", "ch3", "ch4", 574 "ch5", "ch6", "ch7", "ch8", "ch9", 575 "ch10", "ch11", "ch12", "ch13", 576 "ch14", "ch15"; 577 clocks = <&cpg CPG_MOD 709>; 578 clock-names = "fck"; 579 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 580 resets = <&cpg 709>; 581 #dma-cells = <1>; 582 dma-channels = <16>; 583 }; 584 585 dmac2: dma-controller@e7351000 { 586 compatible = "renesas,dmac-r8a779h0", 587 "renesas,rcar-gen4-dmac"; 588 reg = <0 0xe7351000 0 0x1000>, 589 <0 0xe7310000 0 0x10000>; 590 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 599 interrupt-names = "error", 600 "ch0", "ch1", "ch2", "ch3", "ch4", 601 "ch5", "ch6", "ch7"; 602 clocks = <&cpg CPG_MOD 710>; 603 clock-names = "fck"; 604 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 605 resets = <&cpg 710>; 606 #dma-cells = <1>; 607 dma-channels = <8>; 608 }; 609 610 mmc0: mmc@ee140000 { 611 compatible = "renesas,sdhi-r8a779h0", 612 "renesas,rcar-gen4-sdhi"; 613 reg = <0 0xee140000 0 0x2000>; 614 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&cpg CPG_MOD 706>, 616 <&cpg CPG_CORE R8A779H0_CLK_SD0H>; 617 clock-names = "core", "clkh"; 618 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 619 resets = <&cpg 706>; 620 max-frequency = <200000000>; 621 status = "disabled"; 622 }; 623 624 rpc: spi@ee200000 { 625 compatible = "renesas,r8a779h0-rpc-if", 626 "renesas,rcar-gen4-rpc-if"; 627 reg = <0 0xee200000 0 0x200>, 628 <0 0x08000000 0 0x04000000>, 629 <0 0xee208000 0 0x100>; 630 reg-names = "regs", "dirmap", "wbuf"; 631 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&cpg CPG_MOD 629>; 633 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 634 resets = <&cpg 629>; 635 #address-cells = <1>; 636 #size-cells = <0>; 637 status = "disabled"; 638 }; 639 640 gic: interrupt-controller@f1000000 { 641 compatible = "arm,gic-v3"; 642 #interrupt-cells = <3>; 643 #address-cells = <0>; 644 interrupt-controller; 645 reg = <0x0 0xf1000000 0 0x20000>, 646 <0x0 0xf1060000 0 0x110000>; 647 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 648 }; 649 650 prr: chipid@fff00044 { 651 compatible = "renesas,prr"; 652 reg = <0 0xfff00044 0 4>; 653 }; 654 }; 655 656 timer { 657 compatible = "arm,armv8-timer"; 658 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 659 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 660 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 661 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 662 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 663 }; 664}; 665