1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the R-Car V4H ES3.0 Sparrow Hawk board 4 * 5 * Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org> 6 */ 7/* 8 * DA7212 Codec settings 9 * 10 * for Playback 11 * > amixer set "Headphone" 40% 12 * > amixer set "Headphone" on 13 * > amixer set "Mixout Left DAC Left" on 14 * > amixer set "Mixout Right DAC Right" on 15 * > aplay xxx.wav 16 * 17 * for Capture (Aux/Mic) 18 * 19 * on/off (B) 20 * CONN3 (HeadSet) ---+----> MSIOF1 21 * | 22 * CONN4 AUX ---------+ on/off (A) 23 * 24 * > amixer set "Mixin PGA" on 25 * > amixer set "Mixin PGA" 50% 26 * > amixer set "ADC" on 27 * > amixer set "ADC" 80% 28 * > amixer set "Aux" on ^ 29 * > amixer set "Aux" 80% | (A) 30 * > amixer set "Mixin Left Aux Left" on | 31 * > amixer set "Mixin Right Aux Right" on v 32 * > amixer set "Mic 1" on ^ 33 * > amixer set "Mic 1" 80% | (B) 34 * > amixer set "Mixin Left Mic 1" on | 35 * > amixer set "Mixin Right Mic 1" on v 36 * > arecord -f cd xxx.wav 37 */ 38 39/dts-v1/; 40#include <dt-bindings/gpio/gpio.h> 41 42#include "r8a779g3.dtsi" 43 44/ { 45 model = "Retronix Sparrow Hawk board based on r8a779g3"; 46 compatible = "retronix,sparrow-hawk", "renesas,r8a779g3", 47 "renesas,r8a779g0"; 48 49 aliases { 50 ethernet0 = &avb0; 51 i2c0 = &i2c0; 52 i2c1 = &i2c1; 53 i2c2 = &i2c2; 54 i2c3 = &i2c3; 55 i2c4 = &i2c4; 56 i2c5 = &i2c5; 57 serial0 = &hscif0; 58 serial1 = &hscif1; 59 serial2 = &hscif3; 60 spi0 = &rpc; 61 }; 62 63 chosen { 64 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 65 stdout-path = "serial0:921600n8"; 66 }; 67 68 /* Page 31 / FAN */ 69 fan: pwm-fan { 70 pinctrl-0 = <&irq4_pins>; 71 pinctrl-names = "default"; 72 compatible = "pwm-fan"; 73 #cooling-cells = <2>; 74 interrupts-extended = <&intc_ex 4 IRQ_TYPE_EDGE_FALLING>; 75 /* 76 * The fan model connected to this device can be selected 77 * by user. Set "cooling-levels" DT property to single 255 78 * entry to force the fan PWM into constant HIGH, which 79 * forces the fan to spin at maximum RPM, thus providing 80 * maximum cooling to this device and protection against 81 * misconfigured PWM duty cycle to the fan. 82 * 83 * User has to configure "pwms" and "pulses-per-revolution" 84 * DT properties according to fan datasheet first, and then 85 * extend "cooling-levels = <0 m n ... 255>" property to 86 * achieve proper fan control compatible with fan model 87 * installed by user. 88 */ 89 cooling-levels = <255>; 90 pulses-per-revolution = <2>; 91 pwms = <&pwm0 0 50000>; 92 }; 93 94 /* 95 * Page 15 / LPDDR5 96 * 97 * This configuration listed below is for the 8 GiB board variant 98 * with MT62F1G64D8EK-023 WT:C LPDDR5 part populated on the board. 99 * 100 * A variant with 16 GiB MT62F2G64D8EK-023 WT:C part populated on 101 * the board is automatically handled by the bootloader, which 102 * adjusts the correct DRAM size into the memory nodes below. 103 */ 104 memory@48000000 { 105 device_type = "memory"; 106 /* first 128MB is reserved for secure area. */ 107 reg = <0x0 0x48000000 0x0 0x78000000>; 108 }; 109 110 memory@480000000 { 111 device_type = "memory"; 112 reg = <0x4 0x80000000 0x0 0x80000000>; 113 }; 114 115 memory@600000000 { 116 device_type = "memory"; 117 reg = <0x6 0x00000000 0x1 0x00000000>; 118 }; 119 120 /* Page 27 / DSI to Display */ 121 mini-dp-con { 122 compatible = "dp-connector"; 123 label = "CN6"; 124 type = "full-size"; 125 126 port { 127 mini_dp_con_in: endpoint { 128 remote-endpoint = <&sn65dsi86_out>; 129 }; 130 }; 131 }; 132 133 reg_1p2v: regulator-1p2v { 134 compatible = "regulator-fixed"; 135 regulator-name = "fixed-1.2V"; 136 regulator-min-microvolt = <1200000>; 137 regulator-max-microvolt = <1200000>; 138 regulator-boot-on; 139 regulator-always-on; 140 }; 141 142 reg_1p8v: regulator-1p8v { 143 compatible = "regulator-fixed"; 144 regulator-name = "fixed-1.8V"; 145 regulator-min-microvolt = <1800000>; 146 regulator-max-microvolt = <1800000>; 147 regulator-boot-on; 148 regulator-always-on; 149 }; 150 151 reg_3p3v: regulator-3p3v { 152 compatible = "regulator-fixed"; 153 regulator-name = "fixed-3.3V"; 154 regulator-min-microvolt = <3300000>; 155 regulator-max-microvolt = <3300000>; 156 regulator-boot-on; 157 regulator-always-on; 158 }; 159 160 /* Page 27 / DSI to Display */ 161 sn65dsi86_refclk: clk-x9 { 162 compatible = "fixed-clock"; 163 #clock-cells = <0>; 164 clock-frequency = <38400000>; 165 }; 166 167 /* Page 30 / Audio_Codec */ 168 sound_card: sound { 169 compatible = "audio-graph-card2"; 170 links = <&msiof1_snd>; 171 }; 172 173 /* Page 17 uSD-Slot */ 174 vcc_sdhi: regulator-vcc-sdhi { 175 compatible = "regulator-gpio"; 176 regulator-name = "SDHI VccQ"; 177 regulator-min-microvolt = <1800000>; 178 regulator-max-microvolt = <3300000>; 179 gpios = <&gpio8 13 GPIO_ACTIVE_HIGH>; 180 gpios-states = <1>; 181 states = <3300000 0>, <1800000 1>; 182 }; 183}; 184 185&audio_clkin { 186 clock-frequency = <24576000>; 187}; 188 189/* Page 22 / Ether_AVB0 */ 190&avb0 { 191 pinctrl-0 = <&avb0_pins>; 192 pinctrl-names = "default"; 193 phy-handle = <&avb0_phy>; 194 tx-internal-delay-ps = <2000>; 195 status = "okay"; 196 197 mdio { 198 #address-cells = <1>; 199 #size-cells = <0>; 200 201 avb0_phy: ethernet-phy@0 { /* KSZ9031RNXVB */ 202 compatible = "ethernet-phy-id0022.1622", 203 "ethernet-phy-ieee802.3-c22"; 204 rxc-skew-ps = <1500>; 205 reg = <0>; 206 /* AVB0_PHY_INT_V */ 207 interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>; 208 /* GP7_10/AVB0_RESETN_V */ 209 reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; 210 reset-assert-us = <10000>; 211 reset-deassert-us = <300>; 212 }; 213 }; 214}; 215 216/* Page 28 / CANFD_IF */ 217&can_clk { 218 clock-frequency = <40000000>; 219}; 220 221/* Page 28 / CANFD_IF */ 222&canfd { 223 pinctrl-0 = <&canfd3_pins>, <&canfd4_pins>, <&can_clk_pins>; 224 pinctrl-names = "default"; 225 226 status = "okay"; 227 228 channel3 { 229 status = "okay"; 230 }; 231 232 channel4 { 233 status = "okay"; 234 }; 235}; 236 237/* Page 27 / DSI to Display */ 238&dsi1 { 239 status = "okay"; 240 241 ports { 242 port@1 { 243 dsi1_out: endpoint { 244 remote-endpoint = <&sn65dsi86_in>; 245 data-lanes = <1 2 3 4>; 246 }; 247 }; 248 }; 249}; 250 251/* Page 27 / DSI to Display */ 252&du { 253 status = "okay"; 254}; 255 256/* Page 5 / R-Car V4H_INT_I2C */ 257&extal_clk { /* X3 */ 258 clock-frequency = <16666666>; 259}; 260 261/* Page 5 / R-Car V4H_INT_I2C */ 262&extalr_clk { /* X2 */ 263 clock-frequency = <32768>; 264}; 265 266/* Page 26 / 2230 Key M M.2 */ 267&gpio4 { 268 /* 9FGV0441 nOE inputs 0 and 1 */ 269 pcie-m2-oe-hog { 270 gpio-hog; 271 gpios = <21 GPIO_ACTIVE_HIGH>; 272 output-low; 273 line-name = "PCIe-CLK-nOE-M2"; 274 }; 275 276 /* 9FGV0441 nOE inputs 2 and 3 */ 277 pcie-usb-oe-hog { 278 gpio-hog; 279 gpios = <22 GPIO_ACTIVE_HIGH>; 280 output-low; 281 line-name = "PCIe-CLK-nOE-USB"; 282 }; 283}; 284 285/* Page 23 / DEBUG */ 286&hscif0 { /* FTDI ADBUS[3:0] */ 287 pinctrl-0 = <&hscif0_pins>; 288 pinctrl-names = "default"; 289 uart-has-rtscts; 290 bootph-all; 291 292 status = "okay"; 293}; 294 295/* Page 23 / DEBUG */ 296&hscif1 { /* FTDI BDBUS[3:0] */ 297 pinctrl-0 = <&hscif1_pins>; 298 pinctrl-names = "default"; 299 uart-has-rtscts; 300 301 status = "okay"; 302}; 303 304/* Page 24 / UART */ 305&hscif3 { /* CN7 pins 8 (TX) and 10 (RX) */ 306 pinctrl-0 = <&hscif3_pins>; 307 pinctrl-names = "default"; 308 309 status = "okay"; 310}; 311 312/* Page 24 / I2C SWITCH */ 313&i2c0 { 314 #address-cells = <1>; 315 #size-cells = <0>; 316 pinctrl-0 = <&i2c0_pins>; 317 pinctrl-names = "default"; 318 clock-frequency = <400000>; 319 status = "okay"; 320 321 mux@71 { 322 compatible = "nxp,pca9544"; /* TCA9544 */ 323 reg = <0x71>; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 vdd-supply = <®_3p3v>; 327 328 i2c0_mux0: i2c@0 { 329 reg = <0>; 330 #address-cells = <1>; 331 #size-cells = <0>; 332 333 /* Page 27 / DSI to Display */ 334 bridge@2c { 335 pinctrl-0 = <&irq0_pins>; 336 pinctrl-names = "default"; 337 338 compatible = "ti,sn65dsi86"; 339 reg = <0x2c>; 340 341 clocks = <&sn65dsi86_refclk>; 342 clock-names = "refclk"; 343 344 interrupts-extended = <&intc_ex 0 IRQ_TYPE_LEVEL_HIGH>; 345 346 enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; 347 348 vccio-supply = <®_1p8v>; 349 vpll-supply = <®_1p8v>; 350 vcca-supply = <®_1p2v>; 351 vcc-supply = <®_1p2v>; 352 353 ports { 354 #address-cells = <1>; 355 #size-cells = <0>; 356 357 port@0 { 358 reg = <0>; 359 sn65dsi86_in: endpoint { 360 remote-endpoint = <&dsi1_out>; 361 }; 362 }; 363 364 port@1 { 365 reg = <1>; 366 sn65dsi86_out: endpoint { 367 remote-endpoint = <&mini_dp_con_in>; 368 }; 369 }; 370 }; 371 }; 372 }; 373 374 i2c0_mux1: i2c@1 { 375 reg = <1>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 379 /* Page 30 / Audio_Codec */ 380 codec@1a { 381 compatible = "dlg,da7212"; 382 383 #sound-dai-cells = <0>; 384 reg = <0x1a>; 385 386 clocks = <&rcar_sound>; 387 clock-names = "mclk"; 388 389 VDDA-supply = <®_1p8v>; 390 VDDMIC-supply = <®_3p3v>; 391 VDDIO-supply = <®_3p3v>; 392 393 port { 394 da7212_endpoint: endpoint { 395 bitclock-master; 396 frame-master; 397 remote-endpoint = <&msiof1_snd_endpoint>; 398 }; 399 }; 400 }; 401 }; 402 403 i2c0_mux2: i2c@2 { 404 reg = <2>; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 }; 408 409 i2c0_mux3: i2c@3 { 410 reg = <3>; 411 #address-cells = <1>; 412 #size-cells = <0>; 413 }; 414 }; 415}; 416 417/* Page 29 / CSI_IF_CN / CAM_CN0 */ 418&i2c1 { 419 #address-cells = <1>; 420 #size-cells = <0>; 421 pinctrl-0 = <&i2c1_pins>; 422 pinctrl-names = "default"; 423}; 424 425/* Page 29 / CSI_IF_CN / CAM_CN1 */ 426&i2c2 { 427 #address-cells = <1>; 428 #size-cells = <0>; 429 pinctrl-0 = <&i2c2_pins>; 430 pinctrl-names = "default"; 431}; 432 433/* Page 31 / IO_CN */ 434&i2c3 { 435 #address-cells = <1>; 436 #size-cells = <0>; 437 pinctrl-0 = <&i2c3_pins>; 438 pinctrl-names = "default"; 439}; 440 441/* Page 31 / IO_CN */ 442&i2c4 { 443 #address-cells = <1>; 444 #size-cells = <0>; 445 pinctrl-0 = <&i2c4_pins>; 446 pinctrl-names = "default"; 447}; 448 449/* Page 18 / POWER_CORE and Page 19 / POWER_PMIC */ 450&i2c5 { 451 #address-cells = <1>; 452 #size-cells = <0>; 453 pinctrl-0 = <&i2c5_pins>; 454 pinctrl-names = "default"; 455}; 456 457/* Page 17 uSD-Slot */ 458&mmc0 { 459 pinctrl-0 = <&sd_pins>; 460 pinctrl-1 = <&sd_uhs_pins>; 461 pinctrl-names = "default", "state_uhs"; 462 bus-width = <4>; 463 cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; /* SD_CD */ 464 sd-uhs-sdr50; 465 sd-uhs-sdr104; 466 vmmc-supply = <®_3p3v>; 467 vqmmc-supply = <&vcc_sdhi>; 468 status = "okay"; 469}; 470 471&msiof1 { 472 pinctrl-0 = <&msiof1_pins>; 473 pinctrl-names = "default"; 474 475 status = "okay"; 476 477 /* ignore DT warning */ 478 /delete-property/#address-cells; 479 /delete-property/#size-cells; 480 481 msiof1_snd: port { 482 msiof1_snd_endpoint: endpoint { 483 remote-endpoint = <&da7212_endpoint>; 484 }; 485 }; 486}; 487 488/* Page 26 / 2230 Key M M.2 */ 489&pcie0_clkref { 490 clock-frequency = <100000000>; 491}; 492 493&pciec0 { 494 reset-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 495 status = "okay"; 496}; 497 498/* Page 25 / PCIe to USB */ 499&pcie1_clkref { 500 clock-frequency = <100000000>; 501}; 502 503&pciec1 { 504 /* uPD720201 is PCIe Gen2 x1 device */ 505 num-lanes = <1>; 506 reset-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 507 status = "okay"; 508}; 509 510&pfc { 511 pinctrl-0 = <&scif_clk_pins>; 512 pinctrl-names = "default"; 513 514 /* Page 22 / Ether_AVB0 */ 515 avb0_pins: avb0 { 516 mux { 517 groups = "avb0_link", "avb0_mdio", "avb0_rgmii", 518 "avb0_txcrefclk"; 519 function = "avb0"; 520 }; 521 522 pins-mdio { 523 groups = "avb0_mdio"; 524 drive-strength = <21>; 525 }; 526 527 pins-mii { 528 groups = "avb0_rgmii"; 529 drive-strength = <21>; 530 }; 531 532 }; 533 534 /* Page 28 / CANFD_IF */ 535 can_clk_pins: can-clk { 536 groups = "can_clk"; 537 function = "can_clk"; 538 }; 539 540 /* Page 28 / CANFD_IF */ 541 canfd3_pins: canfd3 { 542 groups = "canfd3_data"; 543 function = "canfd3"; 544 }; 545 546 /* Page 28 / CANFD_IF */ 547 canfd4_pins: canfd4 { 548 groups = "canfd4_data"; 549 function = "canfd4"; 550 }; 551 552 /* Page 23 / DEBUG */ 553 hscif0_pins: hscif0 { 554 groups = "hscif0_data", "hscif0_ctrl"; 555 function = "hscif0"; 556 }; 557 558 /* Page 23 / DEBUG */ 559 hscif1_pins: hscif1 { 560 groups = "hscif1_data_a", "hscif1_ctrl_a"; 561 function = "hscif1"; 562 }; 563 564 /* Page 24 / UART */ 565 hscif3_pins: hscif3 { 566 groups = "hscif3_data_a"; 567 function = "hscif3"; 568 }; 569 570 /* Page 24 / I2C SWITCH */ 571 i2c0_pins: i2c0 { 572 groups = "i2c0"; 573 function = "i2c0"; 574 }; 575 576 /* Page 29 / CSI_IF_CN / CAM_CN0 */ 577 i2c1_pins: i2c1 { 578 groups = "i2c1"; 579 function = "i2c1"; 580 }; 581 582 /* Page 29 / CSI_IF_CN / CAM_CN1 */ 583 i2c2_pins: i2c2 { 584 groups = "i2c2"; 585 function = "i2c2"; 586 }; 587 588 /* Page 31 / IO_CN */ 589 i2c3_pins: i2c3 { 590 groups = "i2c3"; 591 function = "i2c3"; 592 }; 593 594 /* Page 31 / IO_CN */ 595 i2c4_pins: i2c4 { 596 groups = "i2c4"; 597 function = "i2c4"; 598 }; 599 600 /* Page 18 / POWER_CORE */ 601 i2c5_pins: i2c5 { 602 groups = "i2c5"; 603 function = "i2c5"; 604 }; 605 606 /* Page 27 / DSI to Display */ 607 irq0_pins: irq0 { 608 groups = "intc_ex_irq0_a"; 609 function = "intc_ex"; 610 }; 611 612 /* Page 31 / FAN */ 613 irq4_pins: irq4 { 614 groups = "intc_ex_irq4_b"; 615 function = "intc_ex"; 616 }; 617 618 /* Page 31 / FAN */ 619 pwm0_pins: pwm0 { 620 groups = "pwm0"; 621 function = "pwm0"; 622 }; 623 624 /* Page 31 / CN7 pin 12 */ 625 pwm1_pins: pwm1 { 626 groups = "pwm1_b"; 627 function = "pwm1"; 628 }; 629 630 /* Page 31 / CN7 pin 32 */ 631 pwm6_pins: pwm6 { 632 groups = "pwm6"; 633 function = "pwm6"; 634 }; 635 636 /* Page 31 / CN7 pin 33 */ 637 pwm7_pins: pwm7 { 638 groups = "pwm7"; 639 function = "pwm7"; 640 }; 641 642 /* Page 16 / QSPI_FLASH */ 643 qspi0_pins: qspi0 { 644 groups = "qspi0_ctrl", "qspi0_data4"; 645 function = "qspi0"; 646 bootph-all; 647 }; 648 649 /* Page 6 / SCIF_CLK_SOC_V */ 650 scif_clk_pins: scif-clk { 651 groups = "scif_clk"; 652 function = "scif_clk"; 653 }; 654 655 /* Page 17 uSD-Slot */ 656 sd_pins: sd { 657 groups = "mmc_data4", "mmc_ctrl"; 658 function = "mmc"; 659 power-source = <3300>; 660 }; 661 662 /* Page 17 uSD-Slot */ 663 sd_uhs_pins: sd-uhs { 664 groups = "mmc_data4", "mmc_ctrl"; 665 function = "mmc"; 666 power-source = <1800>; 667 }; 668 669 /* Page 30 / Audio_Codec */ 670 msiof1_pins: sound { 671 groups = "msiof1_clk", "msiof1_sync", "msiof1_txd", "msiof1_rxd"; 672 function = "msiof1"; 673 }; 674 675 /* Page 30 / Audio_Codec */ 676 sound_clk_pins: sound-clk { 677 groups = "audio_clkin", "audio_clkout"; 678 function = "audio_clk"; 679 }; 680}; 681 682/* Page 30 / Audio_Codec */ 683&rcar_sound { 684 pinctrl-0 = <&sound_clk_pins>; 685 pinctrl-names = "default"; 686 687 /* It is used for ADG output as DA7212_MCLK */ 688 689 /* audio_clkout */ 690 clock-frequency = <12288000>; /* 48 kHz groups */ 691 692 status = "okay"; 693}; 694 695/* Page 31 / FAN */ 696&pwm0 { 697 pinctrl-0 = <&pwm0_pins>; 698 pinctrl-names = "default"; 699 status = "okay"; 700}; 701 702/* Page 31 / CN7 pin 12 */ 703&pwm1 { 704 pinctrl-0 = <&pwm1_pins>; 705 pinctrl-names = "default"; 706 status = "okay"; 707}; 708 709/* Page 31 / CN7 pin 32 */ 710&pwm6 { 711 pinctrl-0 = <&pwm6_pins>; 712 pinctrl-names = "default"; 713 status = "okay"; 714}; 715 716/* Page 31 / CN7 pin 33 */ 717&pwm7 { 718 pinctrl-0 = <&pwm7_pins>; 719 pinctrl-names = "default"; 720 status = "okay"; 721}; 722 723/* Page 16 / QSPI_FLASH */ 724&rpc { 725 pinctrl-0 = <&qspi0_pins>; 726 pinctrl-names = "default"; 727 bootph-all; 728 729 status = "okay"; 730 731 flash@0 { 732 compatible = "spansion,s25fs512s", "jedec,spi-nor"; 733 reg = <0>; 734 spi-max-frequency = <40000000>; 735 spi-rx-bus-width = <4>; 736 spi-tx-bus-width = <4>; 737 bootph-all; 738 739 partitions { 740 compatible = "fixed-partitions"; 741 #address-cells = <1>; 742 #size-cells = <1>; 743 744 boot@0 { 745 reg = <0x0 0x1000000>; 746 read-only; 747 }; 748 749 user@1000000 { 750 reg = <0x1000000 0x2f80000>; 751 }; 752 753 env1@3f80000 { 754 reg = <0x3f80000 0x40000>; 755 }; 756 757 env2@3fc0000 { 758 reg = <0x3fc0000 0x40000>; 759 }; 760 }; 761 }; 762}; 763 764&rwdt { 765 timeout-sec = <60>; 766 status = "okay"; 767}; 768 769/* Page 6 / SCIF_CLK_SOC_V */ 770&scif_clk { /* X12 */ 771 clock-frequency = <24000000>; 772}; 773