1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the R-Car V4H ES3.0 Sparrow Hawk board 4 * 5 * Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org> 6 */ 7/* 8 * DA7212 Codec settings 9 * 10 * for Playback 11 * > amixer set "Headphone" 40% 12 * > amixer set "Headphone" on 13 * > amixer set "Mixout Left DAC Left" on 14 * > amixer set "Mixout Right DAC Right" on 15 * > aplay xxx.wav 16 * 17 * for Capture (Aux/Mic) 18 * 19 * on/off (B) 20 * CONN3 (HeadSet) ---+----> MSIOF1 21 * | 22 * CONN4 AUX ---------+ on/off (A) 23 * 24 * > amixer set "Mixin PGA" on 25 * > amixer set "Mixin PGA" 50% 26 * > amixer set "ADC" on 27 * > amixer set "ADC" 80% 28 * > amixer set "Aux" on ^ 29 * > amixer set "Aux" 80% | (A) 30 * > amixer set "Mixin Left Aux Left" on | 31 * > amixer set "Mixin Right Aux Right" on v 32 * > amixer set "Mic 1" on ^ 33 * > amixer set "Mic 1" 80% | (B) 34 * > amixer set "Mixin Left Mic 1" on | 35 * > amixer set "Mixin Right Mic 1" on v 36 * > arecord -f cd xxx.wav 37 */ 38 39/dts-v1/; 40#include <dt-bindings/gpio/gpio.h> 41#include <dt-bindings/thermal/thermal.h> 42 43#include "r8a779g3.dtsi" 44 45/ { 46 model = "Retronix Sparrow Hawk board based on r8a779g3"; 47 compatible = "retronix,sparrow-hawk", "renesas,r8a779g3", 48 "renesas,r8a779g0"; 49 50 aliases { 51 ethernet0 = &avb0; 52 i2c0 = &i2c0; 53 i2c1 = &i2c1; 54 i2c2 = &i2c2; 55 i2c3 = &i2c3; 56 i2c4 = &i2c4; 57 i2c5 = &i2c5; 58 serial0 = &hscif0; 59 serial1 = &hscif1; 60 serial2 = &hscif3; 61 spi0 = &rpc; 62 }; 63 64 chosen { 65 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 66 stdout-path = "serial0:921600n8"; 67 }; 68 69 /* Page 31 / FAN */ 70 fan: pwm-fan { 71 pinctrl-0 = <&irq4_pins>; 72 pinctrl-names = "default"; 73 compatible = "pwm-fan"; 74 #cooling-cells = <2>; 75 interrupts-extended = <&intc_ex 4 IRQ_TYPE_EDGE_FALLING>; 76 /* 77 * The fan model connected to this device can be selected 78 * by user. Set "cooling-levels" DT property to single 255 79 * entry to force the fan PWM into constant HIGH, which 80 * forces the fan to spin at maximum RPM, thus providing 81 * maximum cooling to this device and protection against 82 * misconfigured PWM duty cycle to the fan. 83 * 84 * User has to configure "pwms" and "pulses-per-revolution" 85 * DT properties according to fan datasheet first, and then 86 * extend "cooling-levels = <0 m n ... 255>" property to 87 * achieve proper fan control compatible with fan model 88 * installed by user. 89 */ 90 cooling-levels = <255>; 91 pulses-per-revolution = <2>; 92 pwms = <&pwm0 0 50000>; 93 }; 94 95 /* 96 * Page 15 / LPDDR5 97 * 98 * This configuration listed below is for the 8 GiB board variant 99 * with MT62F1G64D8EK-023 WT:C LPDDR5 part populated on the board. 100 * 101 * A variant with 16 GiB MT62F2G64D8EK-023 WT:C part populated on 102 * the board is automatically handled by the bootloader, which 103 * adjusts the correct DRAM size into the memory nodes below. 104 */ 105 memory@48000000 { 106 device_type = "memory"; 107 /* first 128MB is reserved for secure area. */ 108 reg = <0x0 0x48000000 0x0 0x78000000>; 109 }; 110 111 memory@480000000 { 112 device_type = "memory"; 113 reg = <0x4 0x80000000 0x0 0x80000000>; 114 }; 115 116 memory@600000000 { 117 device_type = "memory"; 118 reg = <0x6 0x00000000 0x1 0x00000000>; 119 }; 120 121 /* Page 27 / DSI to Display */ 122 mini-dp-con { 123 compatible = "dp-connector"; 124 label = "CN6"; 125 type = "full-size"; 126 127 port { 128 mini_dp_con_in: endpoint { 129 remote-endpoint = <&sn65dsi86_out>; 130 }; 131 }; 132 }; 133 134 /* Page 26 / PCIe.0/1 CLK */ 135 pcie_refclk: clk-x8 { 136 compatible = "fixed-clock"; 137 #clock-cells = <0>; 138 clock-frequency = <25000000>; 139 }; 140 141 reg_1p2v: regulator-1p2v { 142 compatible = "regulator-fixed"; 143 regulator-name = "fixed-1.2V"; 144 regulator-min-microvolt = <1200000>; 145 regulator-max-microvolt = <1200000>; 146 regulator-boot-on; 147 regulator-always-on; 148 }; 149 150 reg_1p8v: regulator-1p8v { 151 compatible = "regulator-fixed"; 152 regulator-name = "fixed-1.8V"; 153 regulator-min-microvolt = <1800000>; 154 regulator-max-microvolt = <1800000>; 155 regulator-boot-on; 156 regulator-always-on; 157 }; 158 159 reg_3p3v: regulator-3p3v { 160 compatible = "regulator-fixed"; 161 regulator-name = "fixed-3.3V"; 162 regulator-min-microvolt = <3300000>; 163 regulator-max-microvolt = <3300000>; 164 regulator-boot-on; 165 regulator-always-on; 166 }; 167 168 /* Page 27 / DSI to Display */ 169 sn65dsi86_refclk: clk-x9 { 170 compatible = "fixed-clock"; 171 #clock-cells = <0>; 172 clock-frequency = <38400000>; 173 }; 174 175 /* Page 30 / Audio_Codec */ 176 sound_card: sound { 177 compatible = "audio-graph-card2"; 178 links = <&msiof1_snd>; 179 }; 180 181 /* Page 17 uSD-Slot */ 182 vcc_sdhi: regulator-vcc-sdhi { 183 compatible = "regulator-gpio"; 184 regulator-name = "SDHI VccQ"; 185 regulator-min-microvolt = <1800000>; 186 regulator-max-microvolt = <3300000>; 187 gpios = <&gpio8 13 GPIO_ACTIVE_HIGH>; 188 gpios-states = <1>; 189 states = <1800000 0>, <3300000 1>; 190 }; 191}; 192 193/* Use thermal-idle cooling for all SoC cores */ 194&a76_0 { 195 #cooling-cells = <2>; 196 197 a76_0_thermal_idle: thermal-idle { 198 #cooling-cells = <2>; 199 duration-us = <10000>; 200 exit-latency-us = <500>; 201 }; 202}; 203 204&a76_1 { 205 a76_1_thermal_idle: thermal-idle { 206 #cooling-cells = <2>; 207 duration-us = <10000>; 208 exit-latency-us = <500>; 209 }; 210}; 211 212&a76_2 { 213 a76_2_thermal_idle: thermal-idle { 214 #cooling-cells = <2>; 215 duration-us = <10000>; 216 exit-latency-us = <500>; 217 }; 218}; 219 220&a76_3 { 221 a76_3_thermal_idle: thermal-idle { 222 #cooling-cells = <2>; 223 duration-us = <10000>; 224 exit-latency-us = <500>; 225 }; 226}; 227 228&audio_clkin { 229 clock-frequency = <24576000>; 230}; 231 232/* Page 22 / Ether_AVB0 */ 233&avb0 { 234 pinctrl-0 = <&avb0_pins>; 235 pinctrl-names = "default"; 236 phy-handle = <&avb0_phy>; 237 tx-internal-delay-ps = <2000>; 238 status = "okay"; 239 240 mdio { 241 #address-cells = <1>; 242 #size-cells = <0>; 243 244 avb0_phy: ethernet-phy@0 { /* KSZ9031RNXVB */ 245 compatible = "ethernet-phy-id0022.1622", 246 "ethernet-phy-ieee802.3-c22"; 247 rxc-skew-ps = <1500>; 248 reg = <0>; 249 /* AVB0_PHY_INT_V */ 250 interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>; 251 /* GP7_10/AVB0_RESETN_V */ 252 reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; 253 reset-assert-us = <10000>; 254 reset-deassert-us = <300>; 255 }; 256 }; 257}; 258 259/* Page 28 / CANFD_IF */ 260&can_clk { 261 clock-frequency = <40000000>; 262}; 263 264/* Page 28 / CANFD_IF */ 265&canfd { 266 pinctrl-0 = <&canfd3_pins>, <&canfd4_pins>, <&can_clk_pins>; 267 pinctrl-names = "default"; 268 269 status = "okay"; 270 271 channel3 { 272 status = "okay"; 273 }; 274 275 channel4 { 276 status = "okay"; 277 }; 278}; 279 280/* Page 27 / DSI to Display */ 281&dsi1 { 282 status = "okay"; 283 284 ports { 285 port@1 { 286 dsi1_out: endpoint { 287 remote-endpoint = <&sn65dsi86_in>; 288 data-lanes = <1 2 3 4>; 289 }; 290 }; 291 }; 292}; 293 294/* Page 27 / DSI to Display */ 295&du { 296 status = "okay"; 297}; 298 299/* Page 5 / R-Car V4H_INT_I2C */ 300&extal_clk { /* X3 */ 301 clock-frequency = <16666666>; 302}; 303 304/* Page 5 / R-Car V4H_INT_I2C */ 305&extalr_clk { /* X2 */ 306 clock-frequency = <32768>; 307}; 308 309/* Page 26 / 2230 Key M M.2 */ 310&gpio4 { 311 /* 9FGV0441 nOE inputs 0 and 1 */ 312 pcie-m2-oe-hog { 313 gpio-hog; 314 gpios = <21 GPIO_ACTIVE_HIGH>; 315 output-low; 316 line-name = "PCIe-CLK-nOE-M2"; 317 }; 318 319 /* 9FGV0441 nOE inputs 2 and 3 */ 320 pcie-usb-oe-hog { 321 gpio-hog; 322 gpios = <22 GPIO_ACTIVE_HIGH>; 323 output-low; 324 line-name = "PCIe-CLK-nOE-USB"; 325 }; 326}; 327 328/* Page 23 / DEBUG */ 329&hscif0 { /* FTDI ADBUS[3:0] */ 330 pinctrl-0 = <&hscif0_pins>; 331 pinctrl-names = "default"; 332 uart-has-rtscts; 333 bootph-all; 334 335 status = "okay"; 336}; 337 338/* Page 23 / DEBUG */ 339&hscif1 { /* FTDI BDBUS[3:0] */ 340 pinctrl-0 = <&hscif1_pins>; 341 pinctrl-names = "default"; 342 uart-has-rtscts; 343 344 status = "okay"; 345}; 346 347/* Page 24 / UART */ 348&hscif3 { /* CN7 pins 8 (TX) and 10 (RX) */ 349 pinctrl-0 = <&hscif3_pins>; 350 pinctrl-names = "default"; 351 352 status = "okay"; 353}; 354 355/* Page 24 / I2C SWITCH */ 356&i2c0 { 357 #address-cells = <1>; 358 #size-cells = <0>; 359 pinctrl-0 = <&i2c0_pins>; 360 pinctrl-names = "default"; 361 clock-frequency = <400000>; 362 status = "okay"; 363 364 mux@71 { 365 compatible = "nxp,pca9544"; /* TCA9544 */ 366 reg = <0x71>; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 vdd-supply = <®_3p3v>; 370 371 i2c0_mux0: i2c@0 { 372 reg = <0>; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 376 /* Page 27 / DSI to Display */ 377 bridge@2c { 378 pinctrl-0 = <&irq0_pins>; 379 pinctrl-names = "default"; 380 381 compatible = "ti,sn65dsi86"; 382 reg = <0x2c>; 383 384 clocks = <&sn65dsi86_refclk>; 385 clock-names = "refclk"; 386 387 interrupts-extended = <&intc_ex 0 IRQ_TYPE_LEVEL_HIGH>; 388 389 enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; 390 391 vccio-supply = <®_1p8v>; 392 vpll-supply = <®_1p8v>; 393 vcca-supply = <®_1p2v>; 394 vcc-supply = <®_1p2v>; 395 396 ports { 397 #address-cells = <1>; 398 #size-cells = <0>; 399 400 port@0 { 401 reg = <0>; 402 sn65dsi86_in: endpoint { 403 remote-endpoint = <&dsi1_out>; 404 }; 405 }; 406 407 port@1 { 408 reg = <1>; 409 sn65dsi86_out: endpoint { 410 remote-endpoint = <&mini_dp_con_in>; 411 }; 412 }; 413 }; 414 }; 415 }; 416 417 i2c0_mux1: i2c@1 { 418 reg = <1>; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 422 /* Page 30 / Audio_Codec */ 423 codec@1a { 424 compatible = "dlg,da7212"; 425 426 #sound-dai-cells = <0>; 427 reg = <0x1a>; 428 429 clocks = <&rcar_sound>; 430 clock-names = "mclk"; 431 432 VDDA-supply = <®_1p8v>; 433 VDDMIC-supply = <®_3p3v>; 434 VDDIO-supply = <®_3p3v>; 435 436 port { 437 da7212_endpoint: endpoint { 438 bitclock-master; 439 frame-master; 440 remote-endpoint = <&msiof1_snd_endpoint>; 441 }; 442 }; 443 }; 444 }; 445 446 i2c0_mux2: i2c@2 { 447 reg = <2>; 448 #address-cells = <1>; 449 #size-cells = <0>; 450 451 /* Page 26 / PCIe.0/1 CLK */ 452 pcie_clk: clk@68 { 453 compatible = "renesas,9fgv0441"; 454 reg = <0x68>; 455 clocks = <&pcie_refclk>; 456 #clock-cells = <1>; 457 }; 458 }; 459 460 i2c0_mux3: i2c@3 { 461 reg = <3>; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 }; 465 }; 466}; 467 468/* Page 29 / CSI_IF_CN / CAM_CN0 */ 469&i2c1 { 470 #address-cells = <1>; 471 #size-cells = <0>; 472 pinctrl-0 = <&i2c1_pins>; 473 pinctrl-names = "default"; 474}; 475 476/* Page 29 / CSI_IF_CN / CAM_CN1 */ 477&i2c2 { 478 #address-cells = <1>; 479 #size-cells = <0>; 480 pinctrl-0 = <&i2c2_pins>; 481 pinctrl-names = "default"; 482}; 483 484/* Page 31 / IO_CN */ 485&i2c3 { 486 #address-cells = <1>; 487 #size-cells = <0>; 488 pinctrl-0 = <&i2c3_pins>; 489 pinctrl-names = "default"; 490}; 491 492/* Page 31 / IO_CN */ 493&i2c4 { 494 #address-cells = <1>; 495 #size-cells = <0>; 496 pinctrl-0 = <&i2c4_pins>; 497 pinctrl-names = "default"; 498}; 499 500/* Page 18 / POWER_CORE and Page 19 / POWER_PMIC */ 501&i2c5 { 502 #address-cells = <1>; 503 #size-cells = <0>; 504 pinctrl-0 = <&i2c5_pins>; 505 pinctrl-names = "default"; 506}; 507 508/* Page 17 uSD-Slot */ 509&mmc0 { 510 pinctrl-0 = <&sd_pins>; 511 pinctrl-1 = <&sd_uhs_pins>; 512 pinctrl-names = "default", "state_uhs"; 513 bus-width = <4>; 514 cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; /* SD_CD */ 515 sd-uhs-sdr50; 516 sd-uhs-sdr104; 517 vmmc-supply = <®_3p3v>; 518 vqmmc-supply = <&vcc_sdhi>; 519 status = "okay"; 520}; 521 522&msiof1 { 523 pinctrl-0 = <&msiof1_pins>; 524 pinctrl-names = "default"; 525 526 status = "okay"; 527 528 /* ignore DT warning */ 529 /delete-property/#address-cells; 530 /delete-property/#size-cells; 531 532 msiof1_snd: port { 533 msiof1_snd_endpoint: endpoint { 534 remote-endpoint = <&da7212_endpoint>; 535 }; 536 }; 537}; 538 539/* Page 26 / 2230 Key M M.2 */ 540&pcie0_clkref { 541 status = "disabled"; 542}; 543 544&pciec0 { 545 clocks = <&cpg CPG_MOD 624>, <&pcie_clk 0>; 546 reset-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 547 status = "okay"; 548}; 549 550&pciec0_rp { 551 clocks = <&pcie_clk 1>; 552 vpcie3v3-supply = <®_3p3v>; 553}; 554 555/* Page 25 / PCIe to USB */ 556&pcie1_clkref { 557 status = "disabled"; 558}; 559 560&pciec1 { 561 clocks = <&cpg CPG_MOD 625>, <&pcie_clk 2>; 562 /* uPD720201 is PCIe Gen2 x1 device */ 563 num-lanes = <1>; 564 reset-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 565 status = "okay"; 566}; 567 568&pciec1_rp { 569 clocks = <&pcie_clk 3>; 570 vpcie3v3-supply = <®_3p3v>; 571}; 572 573&pfc { 574 pinctrl-0 = <&scif_clk_pins>; 575 pinctrl-names = "default"; 576 577 /* Page 22 / Ether_AVB0 */ 578 avb0_pins: avb0 { 579 mux { 580 groups = "avb0_link", "avb0_mdio", "avb0_rgmii", 581 "avb0_txcrefclk"; 582 function = "avb0"; 583 }; 584 585 pins-mdio { 586 groups = "avb0_mdio"; 587 drive-strength = <21>; 588 }; 589 590 pins-mii { 591 groups = "avb0_rgmii"; 592 drive-strength = <21>; 593 }; 594 595 pins-vddq18-25-avb { 596 pins = "PIN_VDDQ_AVB0", "PIN_VDDQ_AVB1", "PIN_VDDQ_AVB2", "PIN_VDDQ_TSN0"; 597 power-source = <1800>; 598 }; 599 }; 600 601 /* Page 28 / CANFD_IF */ 602 can_clk_pins: can-clk { 603 groups = "can_clk"; 604 function = "can_clk"; 605 }; 606 607 /* Page 28 / CANFD_IF */ 608 canfd3_pins: canfd3 { 609 groups = "canfd3_data"; 610 function = "canfd3"; 611 }; 612 613 /* Page 28 / CANFD_IF */ 614 canfd4_pins: canfd4 { 615 groups = "canfd4_data"; 616 function = "canfd4"; 617 }; 618 619 /* Page 23 / DEBUG */ 620 hscif0_pins: hscif0 { 621 groups = "hscif0_data", "hscif0_ctrl"; 622 function = "hscif0"; 623 }; 624 625 /* Page 23 / DEBUG */ 626 hscif1_pins: hscif1 { 627 groups = "hscif1_data_a", "hscif1_ctrl_a"; 628 function = "hscif1"; 629 }; 630 631 /* Page 24 / UART */ 632 hscif3_pins: hscif3 { 633 groups = "hscif3_data_a"; 634 function = "hscif3"; 635 }; 636 637 /* Page 24 / I2C SWITCH */ 638 i2c0_pins: i2c0 { 639 groups = "i2c0"; 640 function = "i2c0"; 641 }; 642 643 /* Page 29 / CSI_IF_CN / CAM_CN0 */ 644 i2c1_pins: i2c1 { 645 groups = "i2c1"; 646 function = "i2c1"; 647 }; 648 649 /* Page 29 / CSI_IF_CN / CAM_CN1 */ 650 i2c2_pins: i2c2 { 651 groups = "i2c2"; 652 function = "i2c2"; 653 }; 654 655 /* Page 31 / IO_CN */ 656 i2c3_pins: i2c3 { 657 groups = "i2c3"; 658 function = "i2c3"; 659 }; 660 661 /* Page 31 / IO_CN */ 662 i2c4_pins: i2c4 { 663 groups = "i2c4"; 664 function = "i2c4"; 665 }; 666 667 /* Page 18 / POWER_CORE */ 668 i2c5_pins: i2c5 { 669 groups = "i2c5"; 670 function = "i2c5"; 671 }; 672 673 /* Page 27 / DSI to Display */ 674 irq0_pins: irq0 { 675 groups = "intc_ex_irq0_a"; 676 function = "intc_ex"; 677 }; 678 679 /* Page 31 / FAN */ 680 irq4_pins: irq4 { 681 groups = "intc_ex_irq4_b"; 682 function = "intc_ex"; 683 }; 684 685 /* Page 31 / FAN */ 686 pwm0_pins: pwm0 { 687 groups = "pwm0"; 688 function = "pwm0"; 689 }; 690 691 /* Page 31 / CN7 pin 12 */ 692 pwm1_pins: pwm1 { 693 groups = "pwm1_b"; 694 function = "pwm1"; 695 }; 696 697 /* Page 31 / CN7 pin 32 */ 698 pwm6_pins: pwm6 { 699 groups = "pwm6"; 700 function = "pwm6"; 701 }; 702 703 /* Page 31 / CN7 pin 33 */ 704 pwm7_pins: pwm7 { 705 groups = "pwm7"; 706 function = "pwm7"; 707 }; 708 709 /* Page 16 / QSPI_FLASH */ 710 qspi0_pins: qspi0 { 711 groups = "qspi0_ctrl", "qspi0_data4"; 712 function = "qspi0"; 713 bootph-all; 714 }; 715 716 /* Page 6 / SCIF_CLK_SOC_V */ 717 scif_clk_pins: scif-clk { 718 groups = "scif_clk"; 719 function = "scif_clk"; 720 }; 721 722 /* Page 17 uSD-Slot */ 723 sd_pins: sd { 724 groups = "mmc_data4", "mmc_ctrl"; 725 function = "mmc"; 726 power-source = <3300>; 727 }; 728 729 /* Page 17 uSD-Slot */ 730 sd_uhs_pins: sd-uhs { 731 groups = "mmc_data4", "mmc_ctrl"; 732 function = "mmc"; 733 power-source = <1800>; 734 }; 735 736 /* Page 30 / Audio_Codec */ 737 msiof1_pins: sound { 738 groups = "msiof1_clk", "msiof1_sync", "msiof1_txd", "msiof1_rxd"; 739 function = "msiof1"; 740 }; 741 742 /* Page 30 / Audio_Codec */ 743 sound_clk_pins: sound-clk { 744 groups = "audio_clkin", "audio_clkout"; 745 function = "audio_clk"; 746 }; 747}; 748 749/* Page 31 / FAN */ 750&pwm0 { 751 pinctrl-0 = <&pwm0_pins>; 752 pinctrl-names = "default"; 753 status = "okay"; 754}; 755 756/* Page 31 / CN7 pin 12 */ 757&pwm1 { 758 pinctrl-0 = <&pwm1_pins>; 759 pinctrl-names = "default"; 760 status = "okay"; 761}; 762 763/* Page 31 / CN7 pin 32 */ 764&pwm6 { 765 pinctrl-0 = <&pwm6_pins>; 766 pinctrl-names = "default"; 767 status = "okay"; 768}; 769 770/* Page 31 / CN7 pin 33 */ 771&pwm7 { 772 pinctrl-0 = <&pwm7_pins>; 773 pinctrl-names = "default"; 774 status = "okay"; 775}; 776 777/* Page 30 / Audio_Codec */ 778&rcar_sound { 779 pinctrl-0 = <&sound_clk_pins>; 780 pinctrl-names = "default"; 781 782 /* It is used for ADG output as DA7212_MCLK */ 783 784 /* audio_clkout */ 785 clock-frequency = <12288000>; /* 48 kHz groups */ 786 787 status = "okay"; 788}; 789 790/* Page 16 / QSPI_FLASH */ 791&rpc { 792 pinctrl-0 = <&qspi0_pins>; 793 pinctrl-names = "default"; 794 bootph-all; 795 796 status = "okay"; 797 798 flash@0 { 799 /* 800 * EVTA1 is populated with Spansion S25FS512S 801 * EVTB1 is populated with Winbond W77Q51NW 802 */ 803 compatible = "jedec,spi-nor"; 804 reg = <0>; 805 spi-max-frequency = <40000000>; 806 spi-rx-bus-width = <4>; 807 spi-tx-bus-width = <4>; 808 bootph-all; 809 810 partitions { 811 compatible = "fixed-partitions"; 812 #address-cells = <1>; 813 #size-cells = <1>; 814 815 boot@0 { 816 reg = <0x0 0x1000000>; 817 read-only; 818 }; 819 820 user@1000000 { 821 reg = <0x1000000 0x2f80000>; 822 }; 823 824 env1@3f80000 { 825 reg = <0x3f80000 0x40000>; 826 }; 827 828 env2@3fc0000 { 829 reg = <0x3fc0000 0x40000>; 830 }; 831 }; 832 }; 833}; 834 835&rwdt { 836 timeout-sec = <60>; 837 status = "okay"; 838}; 839 840/* Page 6 / SCIF_CLK_SOC_V */ 841&scif_clk { /* X12 */ 842 clock-frequency = <24000000>; 843}; 844 845/* THS sensors in SoC, critical temperature trip point is 100C */ 846&sensor1_crit { 847 temperature = <100000>; 848}; 849 850&sensor2_crit { 851 temperature = <100000>; 852}; 853 854&sensor3_crit { 855 temperature = <100000>; 856}; 857 858&sensor4_crit { 859 temperature = <100000>; 860}; 861 862/* THS sensor in SoC near CA76 cores does more progressive cooling. */ 863&sensor_thermal_ca76 { 864 critical-action = "shutdown"; 865 866 cooling-maps { 867 /* 868 * The cooling-device minimum and maximum parameters inversely 869 * match opp-table-0 {} node entries in r8a779g0.dtsi, in other 870 * words, 0 refers to 1.8 GHz OPP and 4 refers to 500 MHz OPP. 871 * This is because they refer to cooling levels, where maximum 872 * cooling level happens at 500 MHz OPP, when the CPU core is 873 * running slowly and therefore generates least heat. 874 */ 875 map0 { 876 /* At 68C, inhibit 1.7 GHz and 1.8 GHz modes */ 877 trip = <&sensor3_passive_low>; 878 cooling-device = <&a76_0 2 4>; 879 contribution = <128>; 880 }; 881 882 map1 { 883 /* At 72C, inhibit 1.5 GHz mode */ 884 trip = <&sensor3_passive_mid>; 885 cooling-device = <&a76_0 3 4>; 886 contribution = <256>; 887 }; 888 889 map2 { 890 /* At 76C, start injecting idle states 0..80% of time */ 891 trip = <&sensor3_passive_hi>; 892 cooling-device = <&a76_0_thermal_idle 0 80>, 893 <&a76_1_thermal_idle 0 80>, 894 <&a76_2_thermal_idle 0 80>, 895 <&a76_3_thermal_idle 0 80>; 896 contribution = <512>; 897 }; 898 899 map3 { 900 /* At 80C, inhibit 1.0 GHz mode */ 901 trip = <&sensor3_passive_crit>; 902 cooling-device = <&a76_0 4 4>; 903 contribution = <1024>; 904 }; 905 }; 906 907 trips { 908 sensor3_passive_low: sensor3-passive-low { 909 temperature = <68000>; 910 hysteresis = <2000>; 911 type = "passive"; 912 }; 913 914 sensor3_passive_mid: sensor3-passive-mid { 915 temperature = <72000>; 916 hysteresis = <2000>; 917 type = "passive"; 918 }; 919 920 sensor3_passive_hi: sensor3-passive-hi { 921 temperature = <76000>; 922 hysteresis = <2000>; 923 type = "passive"; 924 }; 925 926 sensor3_passive_crit: sensor3-passive-crit { 927 temperature = <80000>; 928 hysteresis = <2000>; 929 type = "passive"; 930 }; 931 }; 932}; 933 934&sensor_thermal_cnn { 935 critical-action = "shutdown"; 936}; 937 938&sensor_thermal_cr52 { 939 critical-action = "shutdown"; 940}; 941 942&sensor_thermal_ddr1 { 943 critical-action = "shutdown"; 944}; 945