1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the R-Car V4H ES3.0 Sparrow Hawk board 4 * 5 * Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org> 6 */ 7/* 8 * DA7212 Codec settings 9 * 10 * for Playback 11 * > amixer set "Headphone" 40% 12 * > amixer set "Headphone" on 13 * > amixer set "Mixout Left DAC Left" on 14 * > amixer set "Mixout Right DAC Right" on 15 * > aplay xxx.wav 16 * 17 * for Capture (Aux/Mic) 18 * 19 * on/off (B) 20 * CONN3 (HeadSet) ---+----> MSIOF1 21 * | 22 * CONN4 AUX ---------+ on/off (A) 23 * 24 * > amixer set "Mixin PGA" on 25 * > amixer set "Mixin PGA" 50% 26 * > amixer set "ADC" on 27 * > amixer set "ADC" 80% 28 * > amixer set "Aux" on ^ 29 * > amixer set "Aux" 80% | (A) 30 * > amixer set "Mixin Left Aux Left" on | 31 * > amixer set "Mixin Right Aux Right" on v 32 * > amixer set "Mic 1" on ^ 33 * > amixer set "Mic 1" 80% | (B) 34 * > amixer set "Mixin Left Mic 1" on | 35 * > amixer set "Mixin Right Mic 1" on v 36 * > arecord -f cd xxx.wav 37 */ 38 39/dts-v1/; 40#include <dt-bindings/gpio/gpio.h> 41 42#include "r8a779g3.dtsi" 43 44/ { 45 model = "Retronix Sparrow Hawk board based on r8a779g3"; 46 compatible = "retronix,sparrow-hawk", "renesas,r8a779g3", 47 "renesas,r8a779g0"; 48 49 aliases { 50 ethernet0 = &avb0; 51 i2c0 = &i2c0; 52 i2c1 = &i2c1; 53 i2c2 = &i2c2; 54 i2c3 = &i2c3; 55 i2c4 = &i2c4; 56 i2c5 = &i2c5; 57 serial0 = &hscif0; 58 serial1 = &hscif1; 59 serial2 = &hscif3; 60 spi0 = &rpc; 61 }; 62 63 chosen { 64 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 65 stdout-path = "serial0:921600n8"; 66 }; 67 68 /* Page 31 / FAN */ 69 fan: pwm-fan { 70 pinctrl-0 = <&irq4_pins>; 71 pinctrl-names = "default"; 72 compatible = "pwm-fan"; 73 #cooling-cells = <2>; 74 interrupts-extended = <&intc_ex 4 IRQ_TYPE_EDGE_FALLING>; 75 /* 76 * The fan model connected to this device can be selected 77 * by user. Set "cooling-levels" DT property to single 255 78 * entry to force the fan PWM into constant HIGH, which 79 * forces the fan to spin at maximum RPM, thus providing 80 * maximum cooling to this device and protection against 81 * misconfigured PWM duty cycle to the fan. 82 * 83 * User has to configure "pwms" and "pulses-per-revolution" 84 * DT properties according to fan datasheet first, and then 85 * extend "cooling-levels = <0 m n ... 255>" property to 86 * achieve proper fan control compatible with fan model 87 * installed by user. 88 */ 89 cooling-levels = <255>; 90 pulses-per-revolution = <2>; 91 pwms = <&pwm0 0 50000>; 92 }; 93 94 /* 95 * Page 15 / LPDDR5 96 * 97 * This configuration listed below is for the 8 GiB board variant 98 * with MT62F1G64D8EK-023 WT:C LPDDR5 part populated on the board. 99 * 100 * A variant with 16 GiB MT62F2G64D8EK-023 WT:C part populated on 101 * the board is automatically handled by the bootloader, which 102 * adjusts the correct DRAM size into the memory nodes below. 103 */ 104 memory@48000000 { 105 device_type = "memory"; 106 /* first 128MB is reserved for secure area. */ 107 reg = <0x0 0x48000000 0x0 0x78000000>; 108 }; 109 110 memory@480000000 { 111 device_type = "memory"; 112 reg = <0x4 0x80000000 0x0 0x80000000>; 113 }; 114 115 memory@600000000 { 116 device_type = "memory"; 117 reg = <0x6 0x00000000 0x1 0x00000000>; 118 }; 119 120 /* Page 27 / DSI to Display */ 121 mini-dp-con { 122 compatible = "dp-connector"; 123 label = "CN6"; 124 type = "full-size"; 125 126 port { 127 mini_dp_con_in: endpoint { 128 remote-endpoint = <&sn65dsi86_out>; 129 }; 130 }; 131 }; 132 133 /* Page 26 / PCIe.0/1 CLK */ 134 pcie_refclk: clk-x8 { 135 compatible = "fixed-clock"; 136 #clock-cells = <0>; 137 clock-frequency = <25000000>; 138 }; 139 140 reg_1p2v: regulator-1p2v { 141 compatible = "regulator-fixed"; 142 regulator-name = "fixed-1.2V"; 143 regulator-min-microvolt = <1200000>; 144 regulator-max-microvolt = <1200000>; 145 regulator-boot-on; 146 regulator-always-on; 147 }; 148 149 reg_1p8v: regulator-1p8v { 150 compatible = "regulator-fixed"; 151 regulator-name = "fixed-1.8V"; 152 regulator-min-microvolt = <1800000>; 153 regulator-max-microvolt = <1800000>; 154 regulator-boot-on; 155 regulator-always-on; 156 }; 157 158 reg_3p3v: regulator-3p3v { 159 compatible = "regulator-fixed"; 160 regulator-name = "fixed-3.3V"; 161 regulator-min-microvolt = <3300000>; 162 regulator-max-microvolt = <3300000>; 163 regulator-boot-on; 164 regulator-always-on; 165 }; 166 167 /* Page 27 / DSI to Display */ 168 sn65dsi86_refclk: clk-x9 { 169 compatible = "fixed-clock"; 170 #clock-cells = <0>; 171 clock-frequency = <38400000>; 172 }; 173 174 /* Page 30 / Audio_Codec */ 175 sound_card: sound { 176 compatible = "audio-graph-card2"; 177 links = <&msiof1_snd>; 178 }; 179 180 /* Page 17 uSD-Slot */ 181 vcc_sdhi: regulator-vcc-sdhi { 182 compatible = "regulator-gpio"; 183 regulator-name = "SDHI VccQ"; 184 regulator-min-microvolt = <1800000>; 185 regulator-max-microvolt = <3300000>; 186 gpios = <&gpio8 13 GPIO_ACTIVE_HIGH>; 187 gpios-states = <1>; 188 states = <3300000 0>, <1800000 1>; 189 }; 190}; 191 192&audio_clkin { 193 clock-frequency = <24576000>; 194}; 195 196/* Page 22 / Ether_AVB0 */ 197&avb0 { 198 pinctrl-0 = <&avb0_pins>; 199 pinctrl-names = "default"; 200 phy-handle = <&avb0_phy>; 201 tx-internal-delay-ps = <2000>; 202 status = "okay"; 203 204 mdio { 205 #address-cells = <1>; 206 #size-cells = <0>; 207 208 avb0_phy: ethernet-phy@0 { /* KSZ9031RNXVB */ 209 compatible = "ethernet-phy-id0022.1622", 210 "ethernet-phy-ieee802.3-c22"; 211 rxc-skew-ps = <1500>; 212 reg = <0>; 213 /* AVB0_PHY_INT_V */ 214 interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>; 215 /* GP7_10/AVB0_RESETN_V */ 216 reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; 217 reset-assert-us = <10000>; 218 reset-deassert-us = <300>; 219 }; 220 }; 221}; 222 223/* Page 28 / CANFD_IF */ 224&can_clk { 225 clock-frequency = <40000000>; 226}; 227 228/* Page 28 / CANFD_IF */ 229&canfd { 230 pinctrl-0 = <&canfd3_pins>, <&canfd4_pins>, <&can_clk_pins>; 231 pinctrl-names = "default"; 232 233 status = "okay"; 234 235 channel3 { 236 status = "okay"; 237 }; 238 239 channel4 { 240 status = "okay"; 241 }; 242}; 243 244/* Page 27 / DSI to Display */ 245&dsi1 { 246 status = "okay"; 247 248 ports { 249 port@1 { 250 dsi1_out: endpoint { 251 remote-endpoint = <&sn65dsi86_in>; 252 data-lanes = <1 2 3 4>; 253 }; 254 }; 255 }; 256}; 257 258/* Page 27 / DSI to Display */ 259&du { 260 status = "okay"; 261}; 262 263/* Page 5 / R-Car V4H_INT_I2C */ 264&extal_clk { /* X3 */ 265 clock-frequency = <16666666>; 266}; 267 268/* Page 5 / R-Car V4H_INT_I2C */ 269&extalr_clk { /* X2 */ 270 clock-frequency = <32768>; 271}; 272 273/* Page 26 / 2230 Key M M.2 */ 274&gpio4 { 275 /* 9FGV0441 nOE inputs 0 and 1 */ 276 pcie-m2-oe-hog { 277 gpio-hog; 278 gpios = <21 GPIO_ACTIVE_HIGH>; 279 output-low; 280 line-name = "PCIe-CLK-nOE-M2"; 281 }; 282 283 /* 9FGV0441 nOE inputs 2 and 3 */ 284 pcie-usb-oe-hog { 285 gpio-hog; 286 gpios = <22 GPIO_ACTIVE_HIGH>; 287 output-low; 288 line-name = "PCIe-CLK-nOE-USB"; 289 }; 290}; 291 292/* Page 23 / DEBUG */ 293&hscif0 { /* FTDI ADBUS[3:0] */ 294 pinctrl-0 = <&hscif0_pins>; 295 pinctrl-names = "default"; 296 uart-has-rtscts; 297 bootph-all; 298 299 status = "okay"; 300}; 301 302/* Page 23 / DEBUG */ 303&hscif1 { /* FTDI BDBUS[3:0] */ 304 pinctrl-0 = <&hscif1_pins>; 305 pinctrl-names = "default"; 306 uart-has-rtscts; 307 308 status = "okay"; 309}; 310 311/* Page 24 / UART */ 312&hscif3 { /* CN7 pins 8 (TX) and 10 (RX) */ 313 pinctrl-0 = <&hscif3_pins>; 314 pinctrl-names = "default"; 315 316 status = "okay"; 317}; 318 319/* Page 24 / I2C SWITCH */ 320&i2c0 { 321 #address-cells = <1>; 322 #size-cells = <0>; 323 pinctrl-0 = <&i2c0_pins>; 324 pinctrl-names = "default"; 325 clock-frequency = <400000>; 326 status = "okay"; 327 328 mux@71 { 329 compatible = "nxp,pca9544"; /* TCA9544 */ 330 reg = <0x71>; 331 #address-cells = <1>; 332 #size-cells = <0>; 333 vdd-supply = <®_3p3v>; 334 335 i2c0_mux0: i2c@0 { 336 reg = <0>; 337 #address-cells = <1>; 338 #size-cells = <0>; 339 340 /* Page 27 / DSI to Display */ 341 bridge@2c { 342 pinctrl-0 = <&irq0_pins>; 343 pinctrl-names = "default"; 344 345 compatible = "ti,sn65dsi86"; 346 reg = <0x2c>; 347 348 clocks = <&sn65dsi86_refclk>; 349 clock-names = "refclk"; 350 351 interrupts-extended = <&intc_ex 0 IRQ_TYPE_LEVEL_HIGH>; 352 353 enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; 354 355 vccio-supply = <®_1p8v>; 356 vpll-supply = <®_1p8v>; 357 vcca-supply = <®_1p2v>; 358 vcc-supply = <®_1p2v>; 359 360 ports { 361 #address-cells = <1>; 362 #size-cells = <0>; 363 364 port@0 { 365 reg = <0>; 366 sn65dsi86_in: endpoint { 367 remote-endpoint = <&dsi1_out>; 368 }; 369 }; 370 371 port@1 { 372 reg = <1>; 373 sn65dsi86_out: endpoint { 374 remote-endpoint = <&mini_dp_con_in>; 375 }; 376 }; 377 }; 378 }; 379 }; 380 381 i2c0_mux1: i2c@1 { 382 reg = <1>; 383 #address-cells = <1>; 384 #size-cells = <0>; 385 386 /* Page 30 / Audio_Codec */ 387 codec@1a { 388 compatible = "dlg,da7212"; 389 390 #sound-dai-cells = <0>; 391 reg = <0x1a>; 392 393 clocks = <&rcar_sound>; 394 clock-names = "mclk"; 395 396 VDDA-supply = <®_1p8v>; 397 VDDMIC-supply = <®_3p3v>; 398 VDDIO-supply = <®_3p3v>; 399 400 port { 401 da7212_endpoint: endpoint { 402 bitclock-master; 403 frame-master; 404 remote-endpoint = <&msiof1_snd_endpoint>; 405 }; 406 }; 407 }; 408 }; 409 410 i2c0_mux2: i2c@2 { 411 reg = <2>; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 415 /* Page 26 / PCIe.0/1 CLK */ 416 pcie_clk: clk@68 { 417 compatible = "renesas,9fgv0441"; 418 reg = <0x68>; 419 clocks = <&pcie_refclk>; 420 #clock-cells = <1>; 421 }; 422 }; 423 424 i2c0_mux3: i2c@3 { 425 reg = <3>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 }; 429 }; 430}; 431 432/* Page 29 / CSI_IF_CN / CAM_CN0 */ 433&i2c1 { 434 #address-cells = <1>; 435 #size-cells = <0>; 436 pinctrl-0 = <&i2c1_pins>; 437 pinctrl-names = "default"; 438}; 439 440/* Page 29 / CSI_IF_CN / CAM_CN1 */ 441&i2c2 { 442 #address-cells = <1>; 443 #size-cells = <0>; 444 pinctrl-0 = <&i2c2_pins>; 445 pinctrl-names = "default"; 446}; 447 448/* Page 31 / IO_CN */ 449&i2c3 { 450 #address-cells = <1>; 451 #size-cells = <0>; 452 pinctrl-0 = <&i2c3_pins>; 453 pinctrl-names = "default"; 454}; 455 456/* Page 31 / IO_CN */ 457&i2c4 { 458 #address-cells = <1>; 459 #size-cells = <0>; 460 pinctrl-0 = <&i2c4_pins>; 461 pinctrl-names = "default"; 462}; 463 464/* Page 18 / POWER_CORE and Page 19 / POWER_PMIC */ 465&i2c5 { 466 #address-cells = <1>; 467 #size-cells = <0>; 468 pinctrl-0 = <&i2c5_pins>; 469 pinctrl-names = "default"; 470}; 471 472/* Page 17 uSD-Slot */ 473&mmc0 { 474 pinctrl-0 = <&sd_pins>; 475 pinctrl-1 = <&sd_uhs_pins>; 476 pinctrl-names = "default", "state_uhs"; 477 bus-width = <4>; 478 cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; /* SD_CD */ 479 sd-uhs-sdr50; 480 sd-uhs-sdr104; 481 vmmc-supply = <®_3p3v>; 482 vqmmc-supply = <&vcc_sdhi>; 483 status = "okay"; 484}; 485 486&msiof1 { 487 pinctrl-0 = <&msiof1_pins>; 488 pinctrl-names = "default"; 489 490 status = "okay"; 491 492 /* ignore DT warning */ 493 /delete-property/#address-cells; 494 /delete-property/#size-cells; 495 496 msiof1_snd: port { 497 msiof1_snd_endpoint: endpoint { 498 remote-endpoint = <&da7212_endpoint>; 499 }; 500 }; 501}; 502 503/* Page 26 / 2230 Key M M.2 */ 504&pcie0_clkref { 505 status = "disabled"; 506}; 507 508&pciec0 { 509 clocks = <&cpg CPG_MOD 624>, <&pcie_clk 0>; 510 reset-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 511 status = "okay"; 512}; 513 514&pciec0_rp { 515 clocks = <&pcie_clk 1>; 516 vpcie3v3-supply = <®_3p3v>; 517}; 518 519/* Page 25 / PCIe to USB */ 520&pcie1_clkref { 521 status = "disabled"; 522}; 523 524&pciec1 { 525 clocks = <&cpg CPG_MOD 625>, <&pcie_clk 2>; 526 /* uPD720201 is PCIe Gen2 x1 device */ 527 num-lanes = <1>; 528 reset-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 529 status = "okay"; 530}; 531 532&pciec1_rp { 533 clocks = <&pcie_clk 3>; 534 vpcie3v3-supply = <®_3p3v>; 535}; 536 537&pfc { 538 pinctrl-0 = <&scif_clk_pins>; 539 pinctrl-names = "default"; 540 541 /* Page 22 / Ether_AVB0 */ 542 avb0_pins: avb0 { 543 mux { 544 groups = "avb0_link", "avb0_mdio", "avb0_rgmii", 545 "avb0_txcrefclk"; 546 function = "avb0"; 547 }; 548 549 pins-mdio { 550 groups = "avb0_mdio"; 551 drive-strength = <21>; 552 }; 553 554 pins-mii { 555 groups = "avb0_rgmii"; 556 drive-strength = <21>; 557 }; 558 559 }; 560 561 /* Page 28 / CANFD_IF */ 562 can_clk_pins: can-clk { 563 groups = "can_clk"; 564 function = "can_clk"; 565 }; 566 567 /* Page 28 / CANFD_IF */ 568 canfd3_pins: canfd3 { 569 groups = "canfd3_data"; 570 function = "canfd3"; 571 }; 572 573 /* Page 28 / CANFD_IF */ 574 canfd4_pins: canfd4 { 575 groups = "canfd4_data"; 576 function = "canfd4"; 577 }; 578 579 /* Page 23 / DEBUG */ 580 hscif0_pins: hscif0 { 581 groups = "hscif0_data", "hscif0_ctrl"; 582 function = "hscif0"; 583 }; 584 585 /* Page 23 / DEBUG */ 586 hscif1_pins: hscif1 { 587 groups = "hscif1_data_a", "hscif1_ctrl_a"; 588 function = "hscif1"; 589 }; 590 591 /* Page 24 / UART */ 592 hscif3_pins: hscif3 { 593 groups = "hscif3_data_a"; 594 function = "hscif3"; 595 }; 596 597 /* Page 24 / I2C SWITCH */ 598 i2c0_pins: i2c0 { 599 groups = "i2c0"; 600 function = "i2c0"; 601 }; 602 603 /* Page 29 / CSI_IF_CN / CAM_CN0 */ 604 i2c1_pins: i2c1 { 605 groups = "i2c1"; 606 function = "i2c1"; 607 }; 608 609 /* Page 29 / CSI_IF_CN / CAM_CN1 */ 610 i2c2_pins: i2c2 { 611 groups = "i2c2"; 612 function = "i2c2"; 613 }; 614 615 /* Page 31 / IO_CN */ 616 i2c3_pins: i2c3 { 617 groups = "i2c3"; 618 function = "i2c3"; 619 }; 620 621 /* Page 31 / IO_CN */ 622 i2c4_pins: i2c4 { 623 groups = "i2c4"; 624 function = "i2c4"; 625 }; 626 627 /* Page 18 / POWER_CORE */ 628 i2c5_pins: i2c5 { 629 groups = "i2c5"; 630 function = "i2c5"; 631 }; 632 633 /* Page 27 / DSI to Display */ 634 irq0_pins: irq0 { 635 groups = "intc_ex_irq0_a"; 636 function = "intc_ex"; 637 }; 638 639 /* Page 31 / FAN */ 640 irq4_pins: irq4 { 641 groups = "intc_ex_irq4_b"; 642 function = "intc_ex"; 643 }; 644 645 /* Page 31 / FAN */ 646 pwm0_pins: pwm0 { 647 groups = "pwm0"; 648 function = "pwm0"; 649 }; 650 651 /* Page 31 / CN7 pin 12 */ 652 pwm1_pins: pwm1 { 653 groups = "pwm1_b"; 654 function = "pwm1"; 655 }; 656 657 /* Page 31 / CN7 pin 32 */ 658 pwm6_pins: pwm6 { 659 groups = "pwm6"; 660 function = "pwm6"; 661 }; 662 663 /* Page 31 / CN7 pin 33 */ 664 pwm7_pins: pwm7 { 665 groups = "pwm7"; 666 function = "pwm7"; 667 }; 668 669 /* Page 16 / QSPI_FLASH */ 670 qspi0_pins: qspi0 { 671 groups = "qspi0_ctrl", "qspi0_data4"; 672 function = "qspi0"; 673 bootph-all; 674 }; 675 676 /* Page 6 / SCIF_CLK_SOC_V */ 677 scif_clk_pins: scif-clk { 678 groups = "scif_clk"; 679 function = "scif_clk"; 680 }; 681 682 /* Page 17 uSD-Slot */ 683 sd_pins: sd { 684 groups = "mmc_data4", "mmc_ctrl"; 685 function = "mmc"; 686 power-source = <3300>; 687 }; 688 689 /* Page 17 uSD-Slot */ 690 sd_uhs_pins: sd-uhs { 691 groups = "mmc_data4", "mmc_ctrl"; 692 function = "mmc"; 693 power-source = <1800>; 694 }; 695 696 /* Page 30 / Audio_Codec */ 697 msiof1_pins: sound { 698 groups = "msiof1_clk", "msiof1_sync", "msiof1_txd", "msiof1_rxd"; 699 function = "msiof1"; 700 }; 701 702 /* Page 30 / Audio_Codec */ 703 sound_clk_pins: sound-clk { 704 groups = "audio_clkin", "audio_clkout"; 705 function = "audio_clk"; 706 }; 707}; 708 709/* Page 31 / FAN */ 710&pwm0 { 711 pinctrl-0 = <&pwm0_pins>; 712 pinctrl-names = "default"; 713 status = "okay"; 714}; 715 716/* Page 31 / CN7 pin 12 */ 717&pwm1 { 718 pinctrl-0 = <&pwm1_pins>; 719 pinctrl-names = "default"; 720 status = "okay"; 721}; 722 723/* Page 31 / CN7 pin 32 */ 724&pwm6 { 725 pinctrl-0 = <&pwm6_pins>; 726 pinctrl-names = "default"; 727 status = "okay"; 728}; 729 730/* Page 31 / CN7 pin 33 */ 731&pwm7 { 732 pinctrl-0 = <&pwm7_pins>; 733 pinctrl-names = "default"; 734 status = "okay"; 735}; 736 737/* Page 30 / Audio_Codec */ 738&rcar_sound { 739 pinctrl-0 = <&sound_clk_pins>; 740 pinctrl-names = "default"; 741 742 /* It is used for ADG output as DA7212_MCLK */ 743 744 /* audio_clkout */ 745 clock-frequency = <12288000>; /* 48 kHz groups */ 746 747 status = "okay"; 748}; 749 750/* Page 16 / QSPI_FLASH */ 751&rpc { 752 pinctrl-0 = <&qspi0_pins>; 753 pinctrl-names = "default"; 754 bootph-all; 755 756 status = "okay"; 757 758 flash@0 { 759 compatible = "spansion,s25fs512s", "jedec,spi-nor"; 760 reg = <0>; 761 spi-max-frequency = <40000000>; 762 spi-rx-bus-width = <4>; 763 spi-tx-bus-width = <4>; 764 bootph-all; 765 766 partitions { 767 compatible = "fixed-partitions"; 768 #address-cells = <1>; 769 #size-cells = <1>; 770 771 boot@0 { 772 reg = <0x0 0x1000000>; 773 read-only; 774 }; 775 776 user@1000000 { 777 reg = <0x1000000 0x2f80000>; 778 }; 779 780 env1@3f80000 { 781 reg = <0x3f80000 0x40000>; 782 }; 783 784 env2@3fc0000 { 785 reg = <0x3fc0000 0x40000>; 786 }; 787 }; 788 }; 789}; 790 791&rwdt { 792 timeout-sec = <60>; 793 status = "okay"; 794}; 795 796/* Page 6 / SCIF_CLK_SOC_V */ 797&scif_clk { /* X12 */ 798 clock-frequency = <24000000>; 799}; 800