1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the White Hawk board with ARD-AUDIO-DA7212 Board 4 * 5 * You can find and buy "ARD-AUDIO-DA7212" at Digi-Key 6 * 7 * https://www.digikey.jp/en/products/detail/ARD-AUDIO-DA7212/1564-1021-ND/5456357 8 * 9 * Copyright (C) 2022 Renesas Electronics Corp. 10 * 11 * 12 * [Connection] 13 * 14 * White Hawk ARD-AUDIO-DA7212 15 * +----------------------------+ 16 * |CPU board | 17 * | | 18 * |CN40 (IO PIN HEADER) | 19 * | AUDIO_CLKIN_V pin1 |<--\ +---------------+ 20 * |(*) GP1_25/SL_SW2_V pin2 |<--/ |J2 | 21 * | AUDIO_CLKOUT_V pin5 |<----->| pin7 MCLK | 22 * | SSI_SCK_V pin9 |<----->| pin1 BCLK | 23 * | SSI_WS_V pin13 |<----->| pin3 WCLK | 24 * | SSI_SD_V pin15 |<----->| pin5 DATIN | (@) 25 * | | \-->| pin15 DATOUT | [CAPTURE] 26 * +----------------------------+ +---------------+ 27 * +----------------------------+ 28 * |Breakout board | 29 * | | +---------------+ 30 * |CN34 (I2C CN) | |J1 | 31 * | I2C0_SCL pin3 |<----->| pin20 SCL | 32 * | I2C0_SDA pin5 |<----->| pin18 SDA | 33 * | | +---------------+ 34 * | | +-----------------------+ 35 * |CN4 (Power) | |J7 | 36 * | 3v3 (v) pin9 |<----->| pin4 / pin8 3.3v | 37 * | GND (v) pin3 / pin4 |<----->| pin12 / pin14 GND | 38 * +----------------------------+ +-----------------------+ 39 * (*) GP1_25/SL_SW2_V is used as TPU 40 * (@) Connect to pin5 (DATIN = playback) or pin15 (DATOUT = capture) 41 * (v) These are just sample pins. You can find many 3v3 / GND pins on 42 * White Hawk board, not only CN4. You can use other pins for it. 43 * 44 * [How to enable] 45 * 46 * You need these configs 47 * 48 * CONFIG_PWM 49 * CONFIG_PWM_RENESAS_TPU 50 * CONFIG_COMMON_CLK_PWM 51 * CONFIG_SND_SOC_DA7213 52 * 53 * [How to use] 54 * 55 * 44.1kHz groups sound is available by default. 56 * You need to update audio_clkin settings to switch to 48kHz groups sound. 57 * see 58 * [(C) clock] 59 * 60 * You can use capture if you change the settings 61 * see 62 * [CAPTURE] 63 * 64 * You need to setup Headphone 65 * 66 * > amixer set "Headphone" 40% 67 * > amixer set "Headphone" on 68 * > amixer set "Mixout Left DAC Left" on 69 * > amixer set "Mixout Right DAC Right" on 70 */ 71 72/dts-v1/; 73/plugin/; 74#include <dt-bindings/clock/r8a779g0-cpg-mssr.h> 75 76&{/} { 77 sound_card: sound { 78 compatible = "audio-graph-card"; 79 label = "rcar-sound"; 80 81 dais = <&rsnd_port>; /* DA7212 Audio Codec */ 82 }; 83 84 tpu_clk: tpu-clk { 85 compatible = "pwm-clock"; 86 #clock-cells = <0>; 87 88 /* 44.1kHz groups [(C) clock] */ 89 clock-frequency = <11289600>; 90 pwms = <&tpu 0 88 0>; /* 1000000000 / 88 =~ 11289600 */ 91 92 /* 48 kHz groups [(C) clock] */ 93// clock-frequency = <12288000>; 94// pwms = <&tpu 0 81 0>; /* 1000000000 / 81 =~ 12288000 */ 95 }; 96 97}; 98 99&pfc { 100 sound_pins: sound { 101 groups = "ssi_ctrl", "ssi_data"; 102 function = "ssi"; 103 }; 104 105 sound_clk_pins: sound-clk { 106 groups = "audio_clkin", "audio_clkout"; 107 function = "audio_clk"; 108 }; 109 110 tpu0_pins: tpu0 { 111 groups = "tpu_to0_a"; 112 function = "tpu"; 113 }; 114}; 115 116&tpu { 117 pinctrl-0 = <&tpu0_pins>; 118 pinctrl-names = "default"; 119 120 status = "okay"; 121}; 122 123&i2c0 { 124 #address-cells = <1>; 125 #size-cells = <0>; 126 127 codec@1a { 128 compatible = "dlg,da7212"; 129 130 #sound-dai-cells = <0>; 131 reg = <0x1a>; 132 133 clocks = <&rcar_sound>; 134 clock-names = "mclk"; 135 136 dlg,micbias1-lvl = <2500>; 137 dlg,micbias2-lvl = <2500>; 138 dlg,dmic-data-sel = "lrise_rfall"; 139 dlg,dmic-samplephase = "between_clkedge"; 140 dlg,dmic-clkrate = <3000000>; 141 142 VDDA-supply = <®_1p8v>; 143 VDDMIC-supply = <®_3p3v>; 144 VDDIO-supply = <®_3p3v>; 145 146 port { 147 da7212_endpoint: endpoint { 148 remote-endpoint = <&rsnd_endpoint>; 149 }; 150 }; 151 }; 152}; 153 154&rcar_sound { 155 pinctrl-0 = <&sound_clk_pins>, <&sound_pins>; 156 pinctrl-names = "default"; 157 158 /* Single DAI */ 159 #sound-dai-cells = <0>; 160 161 /* audio_clkout */ 162 #clock-cells = <0>; 163 clock-frequency = <5644800>; /* 44.1kHz groups [(C) clock] */ 164// clock-frequency = <6144000>; /* 48 kHz groups [(C) clock] */ 165 166 status = "okay"; 167 168 /* Update <clkin> to <tpu_clk> */ 169 clocks = <&cpg CPG_MOD 2926>, <&cpg CPG_MOD 2927>, <&tpu_clk>; 170 171 ports { 172 rsnd_port: port { 173 rsnd_endpoint: endpoint { 174 remote-endpoint = <&da7212_endpoint>; 175 176 dai-format = "i2s"; 177 bitclock-master = <&rsnd_endpoint>; 178 frame-master = <&rsnd_endpoint>; 179 180 /* Mutually exclusive with 'capture' */ 181 playback = <&ssi0>; 182 /* [CAPTURE] */ 183 /* capture = <&ssi0>; */ 184 }; 185 }; 186 }; 187}; 188