1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a779f0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a779f0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a779f0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cluster01_opp: opp-table-0 { 18 compatible = "operating-points-v2"; 19 opp-shared; 20 21 opp-500000000 { 22 opp-hz = /bits/ 64 <500000000>; 23 opp-microvolt = <880000>; 24 clock-latency-ns = <500000>; 25 }; 26 opp-800000000 { 27 opp-hz = /bits/ 64 <800000000>; 28 opp-microvolt = <880000>; 29 clock-latency-ns = <500000>; 30 }; 31 opp-1000000000 { 32 opp-hz = /bits/ 64 <1000000000>; 33 opp-microvolt = <880000>; 34 clock-latency-ns = <500000>; 35 }; 36 opp-1200000000 { 37 opp-hz = /bits/ 64 <1200000000>; 38 opp-microvolt = <880000>; 39 clock-latency-ns = <500000>; 40 opp-suspend; 41 }; 42 }; 43 44 cluster23_opp: opp-table-1 { 45 compatible = "operating-points-v2"; 46 opp-shared; 47 48 opp-500000000 { 49 opp-hz = /bits/ 64 <500000000>; 50 opp-microvolt = <880000>; 51 clock-latency-ns = <500000>; 52 }; 53 opp-800000000 { 54 opp-hz = /bits/ 64 <800000000>; 55 opp-microvolt = <880000>; 56 clock-latency-ns = <500000>; 57 }; 58 opp-1000000000 { 59 opp-hz = /bits/ 64 <1000000000>; 60 opp-microvolt = <880000>; 61 clock-latency-ns = <500000>; 62 }; 63 opp-1200000000 { 64 opp-hz = /bits/ 64 <1200000000>; 65 opp-microvolt = <880000>; 66 clock-latency-ns = <500000>; 67 opp-suspend; 68 }; 69 }; 70 71 cpus { 72 #address-cells = <1>; 73 #size-cells = <0>; 74 75 cpu-map { 76 cluster0 { 77 core0 { 78 cpu = <&a55_0>; 79 }; 80 core1 { 81 cpu = <&a55_1>; 82 }; 83 }; 84 85 cluster1 { 86 core0 { 87 cpu = <&a55_2>; 88 }; 89 core1 { 90 cpu = <&a55_3>; 91 }; 92 }; 93 94 cluster2 { 95 core0 { 96 cpu = <&a55_4>; 97 }; 98 core1 { 99 cpu = <&a55_5>; 100 }; 101 }; 102 103 cluster3 { 104 core0 { 105 cpu = <&a55_6>; 106 }; 107 core1 { 108 cpu = <&a55_7>; 109 }; 110 }; 111 }; 112 113 a55_0: cpu@0 { 114 compatible = "arm,cortex-a55"; 115 reg = <0>; 116 device_type = "cpu"; 117 power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; 118 next-level-cache = <&L3_CA55_0>; 119 enable-method = "psci"; 120 cpu-idle-states = <&CPU_SLEEP_0>; 121 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 122 operating-points-v2 = <&cluster01_opp>; 123 }; 124 125 a55_1: cpu@100 { 126 compatible = "arm,cortex-a55"; 127 reg = <0x100>; 128 device_type = "cpu"; 129 power-domains = <&sysc R8A779F0_PD_A1E0D0C1>; 130 next-level-cache = <&L3_CA55_0>; 131 enable-method = "psci"; 132 cpu-idle-states = <&CPU_SLEEP_0>; 133 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 134 operating-points-v2 = <&cluster01_opp>; 135 }; 136 137 a55_2: cpu@10000 { 138 compatible = "arm,cortex-a55"; 139 reg = <0x10000>; 140 device_type = "cpu"; 141 power-domains = <&sysc R8A779F0_PD_A1E0D1C0>; 142 next-level-cache = <&L3_CA55_1>; 143 enable-method = "psci"; 144 cpu-idle-states = <&CPU_SLEEP_0>; 145 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 146 operating-points-v2 = <&cluster01_opp>; 147 }; 148 149 a55_3: cpu@10100 { 150 compatible = "arm,cortex-a55"; 151 reg = <0x10100>; 152 device_type = "cpu"; 153 power-domains = <&sysc R8A779F0_PD_A1E0D1C1>; 154 next-level-cache = <&L3_CA55_1>; 155 enable-method = "psci"; 156 cpu-idle-states = <&CPU_SLEEP_0>; 157 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 158 operating-points-v2 = <&cluster01_opp>; 159 }; 160 161 a55_4: cpu@20000 { 162 compatible = "arm,cortex-a55"; 163 reg = <0x20000>; 164 device_type = "cpu"; 165 power-domains = <&sysc R8A779F0_PD_A1E1D0C0>; 166 next-level-cache = <&L3_CA55_2>; 167 enable-method = "psci"; 168 cpu-idle-states = <&CPU_SLEEP_0>; 169 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 170 operating-points-v2 = <&cluster23_opp>; 171 }; 172 173 a55_5: cpu@20100 { 174 compatible = "arm,cortex-a55"; 175 reg = <0x20100>; 176 device_type = "cpu"; 177 power-domains = <&sysc R8A779F0_PD_A1E1D0C1>; 178 next-level-cache = <&L3_CA55_2>; 179 enable-method = "psci"; 180 cpu-idle-states = <&CPU_SLEEP_0>; 181 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 182 operating-points-v2 = <&cluster23_opp>; 183 }; 184 185 a55_6: cpu@30000 { 186 compatible = "arm,cortex-a55"; 187 reg = <0x30000>; 188 device_type = "cpu"; 189 power-domains = <&sysc R8A779F0_PD_A1E1D1C0>; 190 next-level-cache = <&L3_CA55_3>; 191 enable-method = "psci"; 192 cpu-idle-states = <&CPU_SLEEP_0>; 193 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 194 operating-points-v2 = <&cluster23_opp>; 195 }; 196 197 a55_7: cpu@30100 { 198 compatible = "arm,cortex-a55"; 199 reg = <0x30100>; 200 device_type = "cpu"; 201 power-domains = <&sysc R8A779F0_PD_A1E1D1C1>; 202 next-level-cache = <&L3_CA55_3>; 203 enable-method = "psci"; 204 cpu-idle-states = <&CPU_SLEEP_0>; 205 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 206 operating-points-v2 = <&cluster23_opp>; 207 }; 208 209 L3_CA55_0: cache-controller-0 { 210 compatible = "cache"; 211 power-domains = <&sysc R8A779F0_PD_A2E0D0>; 212 cache-unified; 213 cache-level = <3>; 214 }; 215 216 L3_CA55_1: cache-controller-1 { 217 compatible = "cache"; 218 power-domains = <&sysc R8A779F0_PD_A2E0D1>; 219 cache-unified; 220 cache-level = <3>; 221 }; 222 223 L3_CA55_2: cache-controller-2 { 224 compatible = "cache"; 225 power-domains = <&sysc R8A779F0_PD_A2E1D0>; 226 cache-unified; 227 cache-level = <3>; 228 }; 229 230 L3_CA55_3: cache-controller-3 { 231 compatible = "cache"; 232 power-domains = <&sysc R8A779F0_PD_A2E1D1>; 233 cache-unified; 234 cache-level = <3>; 235 }; 236 237 idle-states { 238 entry-method = "psci"; 239 240 CPU_SLEEP_0: cpu-sleep-0 { 241 compatible = "arm,idle-state"; 242 arm,psci-suspend-param = <0x0010000>; 243 local-timer-stop; 244 entry-latency-us = <400>; 245 exit-latency-us = <500>; 246 min-residency-us = <4000>; 247 }; 248 }; 249 }; 250 251 extal_clk: extal { 252 compatible = "fixed-clock"; 253 #clock-cells = <0>; 254 /* This value must be overridden by the board */ 255 clock-frequency = <0>; 256 }; 257 258 extalr_clk: extalr { 259 compatible = "fixed-clock"; 260 #clock-cells = <0>; 261 /* This value must be overridden by the board */ 262 clock-frequency = <0>; 263 }; 264 265 pcie0_clkref: pcie0-clkref { 266 compatible = "fixed-clock"; 267 #clock-cells = <0>; 268 /* This value must be overridden by the board */ 269 clock-frequency = <0>; 270 }; 271 272 pcie1_clkref: pcie1-clkref { 273 compatible = "fixed-clock"; 274 #clock-cells = <0>; 275 /* This value must be overridden by the board */ 276 clock-frequency = <0>; 277 }; 278 279 pmu_a55 { 280 compatible = "arm,cortex-a55-pmu"; 281 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 282 }; 283 284 psci { 285 compatible = "arm,psci-1.0", "arm,psci-0.2"; 286 method = "smc"; 287 }; 288 289 /* External SCIF clock - to be overridden by boards that provide it */ 290 scif_clk: scif { 291 compatible = "fixed-clock"; 292 #clock-cells = <0>; 293 clock-frequency = <0>; 294 }; 295 296 soc: soc { 297 compatible = "simple-bus"; 298 interrupt-parent = <&gic>; 299 #address-cells = <2>; 300 #size-cells = <2>; 301 ranges; 302 303 rwdt: watchdog@e6020000 { 304 compatible = "renesas,r8a779f0-wdt", 305 "renesas,rcar-gen4-wdt"; 306 reg = <0 0xe6020000 0 0x0c>; 307 interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&cpg CPG_MOD 907>; 309 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 310 resets = <&cpg 907>; 311 status = "disabled"; 312 }; 313 314 pfc: pinctrl@e6050000 { 315 compatible = "renesas,pfc-r8a779f0"; 316 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, 317 <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>; 318 }; 319 320 gpio0: gpio@e6050180 { 321 compatible = "renesas,gpio-r8a779f0", 322 "renesas,rcar-gen4-gpio"; 323 reg = <0 0xe6050180 0 0x54>; 324 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&cpg CPG_MOD 915>; 326 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 327 resets = <&cpg 915>; 328 gpio-controller; 329 #gpio-cells = <2>; 330 gpio-ranges = <&pfc 0 0 21>; 331 interrupt-controller; 332 #interrupt-cells = <2>; 333 }; 334 335 gpio1: gpio@e6050980 { 336 compatible = "renesas,gpio-r8a779f0", 337 "renesas,rcar-gen4-gpio"; 338 reg = <0 0xe6050980 0 0x54>; 339 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&cpg CPG_MOD 915>; 341 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 342 resets = <&cpg 915>; 343 gpio-controller; 344 #gpio-cells = <2>; 345 gpio-ranges = <&pfc 0 32 25>; 346 interrupt-controller; 347 #interrupt-cells = <2>; 348 }; 349 350 gpio2: gpio@e6051180 { 351 compatible = "renesas,gpio-r8a779f0", 352 "renesas,rcar-gen4-gpio"; 353 reg = <0 0xe6051180 0 0x54>; 354 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&cpg CPG_MOD 915>; 356 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 357 resets = <&cpg 915>; 358 gpio-controller; 359 #gpio-cells = <2>; 360 gpio-ranges = <&pfc 0 64 17>; 361 interrupt-controller; 362 #interrupt-cells = <2>; 363 }; 364 365 gpio3: gpio@e6051980 { 366 compatible = "renesas,gpio-r8a779f0", 367 "renesas,rcar-gen4-gpio"; 368 reg = <0 0xe6051980 0 0x54>; 369 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&cpg CPG_MOD 915>; 371 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 372 resets = <&cpg 915>; 373 gpio-controller; 374 #gpio-cells = <2>; 375 gpio-ranges = <&pfc 0 96 19>; 376 interrupt-controller; 377 #interrupt-cells = <2>; 378 }; 379 380 fuse: fuse@e6078800 { 381 compatible = "renesas,r8a779f0-efuse"; 382 reg = <0 0xe6078800 0 0x200>; 383 clocks = <&cpg CPG_MOD 915>; 384 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 385 resets = <&cpg 915>; 386 }; 387 388 cmt0: timer@e60f0000 { 389 compatible = "renesas,r8a779f0-cmt0", 390 "renesas,rcar-gen4-cmt0"; 391 reg = <0 0xe60f0000 0 0x1004>; 392 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&cpg CPG_MOD 910>; 395 clock-names = "fck"; 396 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 397 resets = <&cpg 910>; 398 status = "disabled"; 399 }; 400 401 cmt1: timer@e6130000 { 402 compatible = "renesas,r8a779f0-cmt1", 403 "renesas,rcar-gen4-cmt1"; 404 reg = <0 0xe6130000 0 0x1004>; 405 interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>; 413 clocks = <&cpg CPG_MOD 911>; 414 clock-names = "fck"; 415 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 416 resets = <&cpg 911>; 417 status = "disabled"; 418 }; 419 420 cmt2: timer@e6140000 { 421 compatible = "renesas,r8a779f0-cmt1", 422 "renesas,rcar-gen4-cmt1"; 423 reg = <0 0xe6140000 0 0x1004>; 424 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&cpg CPG_MOD 912>; 433 clock-names = "fck"; 434 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 435 resets = <&cpg 912>; 436 status = "disabled"; 437 }; 438 439 cmt3: timer@e6148000 { 440 compatible = "renesas,r8a779f0-cmt1", 441 "renesas,rcar-gen4-cmt1"; 442 reg = <0 0xe6148000 0 0x1004>; 443 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&cpg CPG_MOD 913>; 452 clock-names = "fck"; 453 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 454 resets = <&cpg 913>; 455 status = "disabled"; 456 }; 457 458 cpg: clock-controller@e6150000 { 459 compatible = "renesas,r8a779f0-cpg-mssr"; 460 reg = <0 0xe6150000 0 0x4000>; 461 clocks = <&extal_clk>, <&extalr_clk>; 462 clock-names = "extal", "extalr"; 463 #clock-cells = <2>; 464 #power-domain-cells = <0>; 465 #reset-cells = <1>; 466 }; 467 468 rst: reset-controller@e6160000 { 469 compatible = "renesas,r8a779f0-rst"; 470 reg = <0 0xe6160000 0 0x4000>; 471 }; 472 473 sysc: system-controller@e6180000 { 474 compatible = "renesas,r8a779f0-sysc"; 475 reg = <0 0xe6180000 0 0x4000>; 476 #power-domain-cells = <1>; 477 }; 478 479 tsc: thermal@e6198000 { 480 compatible = "renesas,r8a779f0-thermal"; 481 /* The 4th sensor is in control domain and not for Linux */ 482 reg = <0 0xe6198000 0 0x200>, 483 <0 0xe61a0000 0 0x200>, 484 <0 0xe61a8000 0 0x200>; 485 clocks = <&cpg CPG_MOD 919>; 486 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 487 resets = <&cpg 919>; 488 #thermal-sensor-cells = <1>; 489 }; 490 491 intc_ex: interrupt-controller@e61c0000 { 492 compatible = "renesas,intc-ex-r8a779f0", "renesas,irqc"; 493 #interrupt-cells = <2>; 494 interrupt-controller; 495 reg = <0 0xe61c0000 0 0x200>; 496 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&cpg CPG_CORE R8A779F0_CLK_CL16M>; 503 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 504 }; 505 506 tmu0: timer@e61e0000 { 507 compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; 508 reg = <0 0xe61e0000 0 0x30>; 509 interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>; 512 interrupt-names = "tuni0", "tuni1", "tuni2"; 513 clocks = <&cpg CPG_MOD 713>; 514 clock-names = "fck"; 515 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 516 resets = <&cpg 713>; 517 status = "disabled"; 518 }; 519 520 tmu1: timer@e6fc0000 { 521 compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; 522 reg = <0 0xe6fc0000 0 0x30>; 523 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 480 IRQ_TYPE_LEVEL_HIGH>; 527 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 528 clocks = <&cpg CPG_MOD 714>; 529 clock-names = "fck"; 530 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 531 resets = <&cpg 714>; 532 status = "disabled"; 533 }; 534 535 tmu2: timer@e6fd0000 { 536 compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; 537 reg = <0 0xe6fd0000 0 0x30>; 538 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 484 IRQ_TYPE_LEVEL_HIGH>; 542 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 543 clocks = <&cpg CPG_MOD 715>; 544 clock-names = "fck"; 545 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 546 resets = <&cpg 715>; 547 status = "disabled"; 548 }; 549 550 tmu3: timer@e6fe0000 { 551 compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; 552 reg = <0 0xe6fe0000 0 0x30>; 553 interrupts = <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>; 557 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 558 clocks = <&cpg CPG_MOD 716>; 559 clock-names = "fck"; 560 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 561 resets = <&cpg 716>; 562 status = "disabled"; 563 }; 564 565 tmu4: timer@ffc00000 { 566 compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; 567 reg = <0 0xffc00000 0 0x30>; 568 interrupts = <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>; 572 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 573 clocks = <&cpg CPG_MOD 717>; 574 clock-names = "fck"; 575 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 576 resets = <&cpg 717>; 577 status = "disabled"; 578 }; 579 580 eth_serdes: phy@e6444000 { 581 compatible = "renesas,r8a779f0-ether-serdes"; 582 reg = <0 0xe6444000 0 0x2800>; 583 clocks = <&cpg CPG_MOD 1506>; 584 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 585 resets = <&cpg 1506>; 586 #phy-cells = <1>; 587 status = "disabled"; 588 }; 589 590 i2c0: i2c@e6500000 { 591 compatible = "renesas,i2c-r8a779f0", 592 "renesas,rcar-gen4-i2c"; 593 reg = <0 0xe6500000 0 0x40>; 594 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&cpg CPG_MOD 518>; 596 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 597 resets = <&cpg 518>; 598 dmas = <&dmac0 0x91>, <&dmac0 0x90>, 599 <&dmac1 0x91>, <&dmac1 0x90>; 600 dma-names = "tx", "rx", "tx", "rx"; 601 i2c-scl-internal-delay-ns = <110>; 602 #address-cells = <1>; 603 #size-cells = <0>; 604 status = "disabled"; 605 }; 606 607 i2c1: i2c@e6508000 { 608 compatible = "renesas,i2c-r8a779f0", 609 "renesas,rcar-gen4-i2c"; 610 reg = <0 0xe6508000 0 0x40>; 611 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&cpg CPG_MOD 519>; 613 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 614 resets = <&cpg 519>; 615 dmas = <&dmac0 0x93>, <&dmac0 0x92>, 616 <&dmac1 0x93>, <&dmac1 0x92>; 617 dma-names = "tx", "rx", "tx", "rx"; 618 i2c-scl-internal-delay-ns = <110>; 619 #address-cells = <1>; 620 #size-cells = <0>; 621 status = "disabled"; 622 }; 623 624 i2c2: i2c@e6510000 { 625 compatible = "renesas,i2c-r8a779f0", 626 "renesas,rcar-gen4-i2c"; 627 reg = <0 0xe6510000 0 0x40>; 628 interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&cpg CPG_MOD 520>; 630 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 631 resets = <&cpg 520>; 632 dmas = <&dmac0 0x95>, <&dmac0 0x94>, 633 <&dmac1 0x95>, <&dmac1 0x94>; 634 dma-names = "tx", "rx", "tx", "rx"; 635 i2c-scl-internal-delay-ns = <110>; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 status = "disabled"; 639 }; 640 641 i2c3: i2c@e66d0000 { 642 compatible = "renesas,i2c-r8a779f0", 643 "renesas,rcar-gen4-i2c"; 644 reg = <0 0xe66d0000 0 0x40>; 645 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&cpg CPG_MOD 521>; 647 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 648 resets = <&cpg 521>; 649 dmas = <&dmac0 0x97>, <&dmac0 0x96>, 650 <&dmac1 0x97>, <&dmac1 0x96>; 651 dma-names = "tx", "rx", "tx", "rx"; 652 i2c-scl-internal-delay-ns = <110>; 653 #address-cells = <1>; 654 #size-cells = <0>; 655 status = "disabled"; 656 }; 657 658 i2c4: i2c@e66d8000 { 659 compatible = "renesas,i2c-r8a779f0", 660 "renesas,rcar-gen4-i2c"; 661 reg = <0 0xe66d8000 0 0x40>; 662 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 663 clocks = <&cpg CPG_MOD 522>; 664 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 665 resets = <&cpg 522>; 666 dmas = <&dmac0 0x99>, <&dmac0 0x98>, 667 <&dmac1 0x99>, <&dmac1 0x98>; 668 dma-names = "tx", "rx", "tx", "rx"; 669 i2c-scl-internal-delay-ns = <110>; 670 #address-cells = <1>; 671 #size-cells = <0>; 672 status = "disabled"; 673 }; 674 675 i2c5: i2c@e66e0000 { 676 compatible = "renesas,i2c-r8a779f0", 677 "renesas,rcar-gen4-i2c"; 678 reg = <0 0xe66e0000 0 0x40>; 679 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 680 clocks = <&cpg CPG_MOD 523>; 681 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 682 resets = <&cpg 523>; 683 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>, 684 <&dmac1 0x9b>, <&dmac1 0x9a>; 685 dma-names = "tx", "rx", "tx", "rx"; 686 i2c-scl-internal-delay-ns = <110>; 687 #address-cells = <1>; 688 #size-cells = <0>; 689 status = "disabled"; 690 }; 691 692 hscif0: serial@e6540000 { 693 compatible = "renesas,hscif-r8a779f0", 694 "renesas,rcar-gen4-hscif", "renesas,hscif"; 695 reg = <0 0xe6540000 0 0x60>; 696 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&cpg CPG_MOD 514>, 698 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 699 <&scif_clk>; 700 clock-names = "fck", "brg_int", "scif_clk"; 701 dmas = <&dmac0 0x31>, <&dmac0 0x30>, 702 <&dmac1 0x31>, <&dmac1 0x30>; 703 dma-names = "tx", "rx", "tx", "rx"; 704 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 705 resets = <&cpg 514>; 706 status = "disabled"; 707 }; 708 709 hscif1: serial@e6550000 { 710 compatible = "renesas,hscif-r8a779f0", 711 "renesas,rcar-gen4-hscif", "renesas,hscif"; 712 reg = <0 0xe6550000 0 0x60>; 713 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&cpg CPG_MOD 515>, 715 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 716 <&scif_clk>; 717 clock-names = "fck", "brg_int", "scif_clk"; 718 dmas = <&dmac0 0x33>, <&dmac0 0x32>, 719 <&dmac1 0x33>, <&dmac1 0x32>; 720 dma-names = "tx", "rx", "tx", "rx"; 721 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 722 resets = <&cpg 515>; 723 status = "disabled"; 724 }; 725 726 hscif2: serial@e6560000 { 727 compatible = "renesas,hscif-r8a779f0", 728 "renesas,rcar-gen4-hscif", "renesas,hscif"; 729 reg = <0 0xe6560000 0 0x60>; 730 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&cpg CPG_MOD 516>, 732 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 733 <&scif_clk>; 734 clock-names = "fck", "brg_int", "scif_clk"; 735 dmas = <&dmac0 0x35>, <&dmac0 0x34>, 736 <&dmac1 0x35>, <&dmac1 0x34>; 737 dma-names = "tx", "rx", "tx", "rx"; 738 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 739 resets = <&cpg 516>; 740 status = "disabled"; 741 }; 742 743 hscif3: serial@e66a0000 { 744 compatible = "renesas,hscif-r8a779f0", 745 "renesas,rcar-gen4-hscif", "renesas,hscif"; 746 reg = <0 0xe66a0000 0 0x60>; 747 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&cpg CPG_MOD 517>, 749 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 750 <&scif_clk>; 751 clock-names = "fck", "brg_int", "scif_clk"; 752 dmas = <&dmac0 0x37>, <&dmac0 0x36>, 753 <&dmac1 0x37>, <&dmac1 0x36>; 754 dma-names = "tx", "rx", "tx", "rx"; 755 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 756 resets = <&cpg 517>; 757 status = "disabled"; 758 }; 759 760 pciec0: pcie@e65d0000 { 761 compatible = "renesas,r8a779f0-pcie", 762 "renesas,rcar-gen4-pcie"; 763 reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>, 764 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>, 765 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>, 766 <0 0xfe000000 0 0x400000>; 767 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config"; 768 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 772 interrupt-names = "msi", "dma", "sft_ce", "app"; 773 clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; 774 clock-names = "core", "ref"; 775 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 776 resets = <&cpg 624>; 777 reset-names = "pwr"; 778 max-link-speed = <4>; 779 num-lanes = <2>; 780 #address-cells = <3>; 781 #size-cells = <2>; 782 bus-range = <0x00 0xff>; 783 device_type = "pci"; 784 ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>, 785 <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>; 786 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; 787 #interrupt-cells = <1>; 788 interrupt-map-mask = <0 0 0 7>; 789 interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 790 <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 791 <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 792 <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>; 793 snps,enable-cdm-check; 794 status = "disabled"; 795 }; 796 797 pciec1: pcie@e65d8000 { 798 compatible = "renesas,r8a779f0-pcie", 799 "renesas,rcar-gen4-pcie"; 800 reg = <0 0xe65d8000 0 0x1000>, <0 0xe65da000 0 0x0800>, 801 <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>, 802 <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>, 803 <0 0xee900000 0 0x400000>; 804 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config"; 805 interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; 809 interrupt-names = "msi", "dma", "sft_ce", "app"; 810 clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>; 811 clock-names = "core", "ref"; 812 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 813 resets = <&cpg 625>; 814 reset-names = "pwr"; 815 max-link-speed = <4>; 816 num-lanes = <2>; 817 #address-cells = <3>; 818 #size-cells = <2>; 819 bus-range = <0x00 0xff>; 820 device_type = "pci"; 821 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00400000>, 822 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x10000000>; 823 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; 824 #interrupt-cells = <1>; 825 interrupt-map-mask = <0 0 0 7>; 826 interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 827 <0 0 0 2 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 828 <0 0 0 3 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 829 <0 0 0 4 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>; 830 snps,enable-cdm-check; 831 status = "disabled"; 832 }; 833 834 pciec0_ep: pcie-ep@e65d0000 { 835 compatible = "renesas,r8a779f0-pcie-ep", 836 "renesas,rcar-gen4-pcie-ep"; 837 reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>, 838 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>, 839 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>, 840 <0 0xfe000000 0 0x400000>; 841 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space"; 842 interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 845 interrupt-names = "dma", "sft_ce", "app"; 846 clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; 847 clock-names = "core", "ref"; 848 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 849 resets = <&cpg 624>; 850 reset-names = "pwr"; 851 max-link-speed = <4>; 852 num-lanes = <2>; 853 max-functions = /bits/ 8 <2>; 854 status = "disabled"; 855 }; 856 857 pciec1_ep: pcie-ep@e65d8000 { 858 compatible = "renesas,r8a779f0-pcie-ep", 859 "renesas,rcar-gen4-pcie-ep"; 860 reg = <0 0xe65d8000 0 0x2000>, <0 0xe65da000 0 0x1000>, 861 <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>, 862 <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>, 863 <0 0xee900000 0 0x400000>; 864 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space"; 865 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; 868 interrupt-names = "dma", "sft_ce", "app"; 869 clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>; 870 clock-names = "core", "ref"; 871 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 872 resets = <&cpg 625>; 873 reset-names = "pwr"; 874 max-link-speed = <4>; 875 num-lanes = <2>; 876 max-functions = /bits/ 8 <2>; 877 status = "disabled"; 878 }; 879 880 ufs: ufs@e6860000 { 881 compatible = "renesas,r8a779f0-ufs"; 882 reg = <0 0xe6860000 0 0x100>; 883 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 884 clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>; 885 clock-names = "fck", "ref_clk"; 886 freq-table-hz = <200000000 200000000>, <38400000 38400000>; 887 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 888 resets = <&cpg 1514>; 889 status = "disabled"; 890 }; 891 892 rswitch: ethernet@e6880000 { 893 compatible = "renesas,r8a779f0-ether-switch"; 894 reg = <0 0xe6880000 0 0x20000>, <0 0xe68c0000 0 0x20000>; 895 reg-names = "base", "secure_base"; 896 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 918 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 919 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 920 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 921 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 943 interrupt-names = "mfwd_error", "race_error", 944 "coma_error", "gwca0_error", 945 "gwca1_error", "etha0_error", 946 "etha1_error", "etha2_error", 947 "gptp0_status", "gptp1_status", 948 "mfwd_status", "race_status", 949 "coma_status", "gwca0_status", 950 "gwca1_status", "etha0_status", 951 "etha1_status", "etha2_status", 952 "rmac0_status", "rmac1_status", 953 "rmac2_status", 954 "gwca0_rxtx0", "gwca0_rxtx1", 955 "gwca0_rxtx2", "gwca0_rxtx3", 956 "gwca0_rxtx4", "gwca0_rxtx5", 957 "gwca0_rxtx6", "gwca0_rxtx7", 958 "gwca1_rxtx0", "gwca1_rxtx1", 959 "gwca1_rxtx2", "gwca1_rxtx3", 960 "gwca1_rxtx4", "gwca1_rxtx5", 961 "gwca1_rxtx6", "gwca1_rxtx7", 962 "gwca0_rxts0", "gwca0_rxts1", 963 "gwca1_rxts0", "gwca1_rxts1", 964 "rmac0_mdio", "rmac1_mdio", 965 "rmac2_mdio", 966 "rmac0_phy", "rmac1_phy", 967 "rmac2_phy"; 968 clocks = <&cpg CPG_MOD 1505>; 969 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 970 resets = <&cpg 1505>; 971 status = "disabled"; 972 973 ethernet-ports { 974 #address-cells = <1>; 975 #size-cells = <0>; 976 977 port@0 { 978 reg = <0>; 979 phys = <ð_serdes 0>; 980 }; 981 port@1 { 982 reg = <1>; 983 phys = <ð_serdes 1>; 984 }; 985 port@2 { 986 reg = <2>; 987 phys = <ð_serdes 2>; 988 }; 989 }; 990 }; 991 992 scif0: serial@e6e60000 { 993 compatible = "renesas,scif-r8a779f0", 994 "renesas,rcar-gen4-scif", "renesas,scif"; 995 reg = <0 0xe6e60000 0 64>; 996 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 997 clocks = <&cpg CPG_MOD 702>, 998 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 999 <&scif_clk>; 1000 clock-names = "fck", "brg_int", "scif_clk"; 1001 dmas = <&dmac0 0x51>, <&dmac0 0x50>, 1002 <&dmac1 0x51>, <&dmac1 0x50>; 1003 dma-names = "tx", "rx", "tx", "rx"; 1004 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1005 resets = <&cpg 702>; 1006 status = "disabled"; 1007 }; 1008 1009 scif1: serial@e6e68000 { 1010 compatible = "renesas,scif-r8a779f0", 1011 "renesas,rcar-gen4-scif", "renesas,scif"; 1012 reg = <0 0xe6e68000 0 64>; 1013 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>; 1014 clocks = <&cpg CPG_MOD 703>, 1015 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 1016 <&scif_clk>; 1017 clock-names = "fck", "brg_int", "scif_clk"; 1018 dmas = <&dmac0 0x53>, <&dmac0 0x52>, 1019 <&dmac1 0x53>, <&dmac1 0x52>; 1020 dma-names = "tx", "rx", "tx", "rx"; 1021 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1022 resets = <&cpg 703>; 1023 status = "disabled"; 1024 }; 1025 1026 scif3: serial@e6c50000 { 1027 compatible = "renesas,scif-r8a779f0", 1028 "renesas,rcar-gen4-scif", "renesas,scif"; 1029 reg = <0 0xe6c50000 0 64>; 1030 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 1031 clocks = <&cpg CPG_MOD 704>, 1032 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 1033 <&scif_clk>; 1034 clock-names = "fck", "brg_int", "scif_clk"; 1035 dmas = <&dmac0 0x57>, <&dmac0 0x56>, 1036 <&dmac1 0x57>, <&dmac1 0x56>; 1037 dma-names = "tx", "rx", "tx", "rx"; 1038 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1039 resets = <&cpg 704>; 1040 status = "disabled"; 1041 }; 1042 1043 scif4: serial@e6c40000 { 1044 compatible = "renesas,scif-r8a779f0", 1045 "renesas,rcar-gen4-scif", "renesas,scif"; 1046 reg = <0 0xe6c40000 0 64>; 1047 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 1048 clocks = <&cpg CPG_MOD 705>, 1049 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 1050 <&scif_clk>; 1051 clock-names = "fck", "brg_int", "scif_clk"; 1052 dmas = <&dmac0 0x59>, <&dmac0 0x58>, 1053 <&dmac1 0x59>, <&dmac1 0x58>; 1054 dma-names = "tx", "rx", "tx", "rx"; 1055 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1056 resets = <&cpg 705>; 1057 status = "disabled"; 1058 }; 1059 1060 msiof0: spi@e6e90000 { 1061 compatible = "renesas,msiof-r8a779f0", 1062 "renesas,rcar-gen4-msiof"; 1063 reg = <0 0xe6e90000 0 0x0064>; 1064 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 1065 clocks = <&cpg CPG_MOD 618>; 1066 dmas = <&dmac0 0x41>, <&dmac0 0x40>, 1067 <&dmac1 0x41>, <&dmac1 0x40>; 1068 dma-names = "tx", "rx", "tx", "rx"; 1069 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1070 resets = <&cpg 618>; 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 status = "disabled"; 1074 }; 1075 1076 msiof1: spi@e6ea0000 { 1077 compatible = "renesas,msiof-r8a779f0", 1078 "renesas,rcar-gen4-msiof"; 1079 reg = <0 0xe6ea0000 0 0x0064>; 1080 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1081 clocks = <&cpg CPG_MOD 619>; 1082 dmas = <&dmac0 0x43>, <&dmac0 0x42>, 1083 <&dmac1 0x43>, <&dmac1 0x42>; 1084 dma-names = "tx", "rx", "tx", "rx"; 1085 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1086 resets = <&cpg 619>; 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 status = "disabled"; 1090 }; 1091 1092 msiof2: spi@e6c00000 { 1093 compatible = "renesas,msiof-r8a779f0", 1094 "renesas,rcar-gen4-msiof"; 1095 reg = <0 0xe6c00000 0 0x0064>; 1096 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 1097 clocks = <&cpg CPG_MOD 620>; 1098 dmas = <&dmac0 0x45>, <&dmac0 0x44>, 1099 <&dmac1 0x45>, <&dmac1 0x44>; 1100 dma-names = "tx", "rx", "tx", "rx"; 1101 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1102 resets = <&cpg 620>; 1103 #address-cells = <1>; 1104 #size-cells = <0>; 1105 status = "disabled"; 1106 }; 1107 1108 msiof3: spi@e6c10000 { 1109 compatible = "renesas,msiof-r8a779f0", 1110 "renesas,rcar-gen4-msiof"; 1111 reg = <0 0xe6c10000 0 0x0064>; 1112 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 1113 clocks = <&cpg CPG_MOD 621>; 1114 dmas = <&dmac0 0x47>, <&dmac0 0x46>, 1115 <&dmac1 0x47>, <&dmac1 0x46>; 1116 dma-names = "tx", "rx", "tx", "rx"; 1117 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1118 resets = <&cpg 621>; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 status = "disabled"; 1122 }; 1123 1124 dmac0: dma-controller@e7350000 { 1125 compatible = "renesas,dmac-r8a779f0", 1126 "renesas,rcar-gen4-dmac"; 1127 reg = <0 0xe7350000 0 0x1000>, 1128 <0 0xe7300000 0 0x10000>; 1129 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1139 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1146 interrupt-names = "error", 1147 "ch0", "ch1", "ch2", "ch3", "ch4", 1148 "ch5", "ch6", "ch7", "ch8", "ch9", 1149 "ch10", "ch11", "ch12", "ch13", 1150 "ch14", "ch15"; 1151 clocks = <&cpg CPG_MOD 709>; 1152 clock-names = "fck"; 1153 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1154 resets = <&cpg 709>; 1155 #dma-cells = <1>; 1156 dma-channels = <16>; 1157 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 1158 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 1159 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 1160 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 1161 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 1162 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 1163 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 1164 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 1165 }; 1166 1167 dmac1: dma-controller@e7351000 { 1168 compatible = "renesas,dmac-r8a779f0", 1169 "renesas,rcar-gen4-dmac"; 1170 reg = <0 0xe7351000 0 0x1000>, 1171 <0 0xe7310000 0 0x10000>; 1172 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1189 interrupt-names = "error", 1190 "ch0", "ch1", "ch2", "ch3", "ch4", 1191 "ch5", "ch6", "ch7", "ch8", "ch9", 1192 "ch10", "ch11", "ch12", "ch13", 1193 "ch14", "ch15"; 1194 clocks = <&cpg CPG_MOD 710>; 1195 clock-names = "fck"; 1196 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1197 resets = <&cpg 710>; 1198 #dma-cells = <1>; 1199 dma-channels = <16>; 1200 iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>, 1201 <&ipmmu_ds0 18>, <&ipmmu_ds0 19>, 1202 <&ipmmu_ds0 20>, <&ipmmu_ds0 21>, 1203 <&ipmmu_ds0 22>, <&ipmmu_ds0 23>, 1204 <&ipmmu_ds0 24>, <&ipmmu_ds0 25>, 1205 <&ipmmu_ds0 26>, <&ipmmu_ds0 27>, 1206 <&ipmmu_ds0 28>, <&ipmmu_ds0 29>, 1207 <&ipmmu_ds0 30>, <&ipmmu_ds0 31>; 1208 }; 1209 1210 mmc0: mmc@ee140000 { 1211 compatible = "renesas,sdhi-r8a779f0", 1212 "renesas,rcar-gen4-sdhi"; 1213 reg = <0 0xee140000 0 0x2000>; 1214 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 1215 clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779F0_CLK_SD0H>; 1216 clock-names = "core", "clkh"; 1217 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1218 resets = <&cpg 706>; 1219 max-frequency = <200000000>; 1220 iommus = <&ipmmu_ds0 32>; 1221 status = "disabled"; 1222 }; 1223 1224 ipmmu_rt0: iommu@ee480000 { 1225 compatible = "renesas,ipmmu-r8a779f0", 1226 "renesas,rcar-gen4-ipmmu-vmsa"; 1227 reg = <0 0xee480000 0 0x20000>; 1228 renesas,ipmmu-main = <&ipmmu_mm>; 1229 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1230 #iommu-cells = <1>; 1231 }; 1232 1233 ipmmu_rt1: iommu@ee4c0000 { 1234 compatible = "renesas,ipmmu-r8a779f0", 1235 "renesas,rcar-gen4-ipmmu-vmsa"; 1236 reg = <0 0xee4c0000 0 0x20000>; 1237 renesas,ipmmu-main = <&ipmmu_mm>; 1238 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1239 #iommu-cells = <1>; 1240 }; 1241 1242 ipmmu_ds0: iommu@eed00000 { 1243 compatible = "renesas,ipmmu-r8a779f0", 1244 "renesas,rcar-gen4-ipmmu-vmsa"; 1245 reg = <0 0xeed00000 0 0x20000>; 1246 renesas,ipmmu-main = <&ipmmu_mm>; 1247 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1248 #iommu-cells = <1>; 1249 }; 1250 1251 ipmmu_hc: iommu@eed40000 { 1252 compatible = "renesas,ipmmu-r8a779f0", 1253 "renesas,rcar-gen4-ipmmu-vmsa"; 1254 reg = <0 0xeed40000 0 0x20000>; 1255 renesas,ipmmu-main = <&ipmmu_mm>; 1256 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1257 #iommu-cells = <1>; 1258 }; 1259 1260 ipmmu_mm: iommu@eefc0000 { 1261 compatible = "renesas,ipmmu-r8a779f0", 1262 "renesas,rcar-gen4-ipmmu-vmsa"; 1263 reg = <0 0xeefc0000 0 0x20000>; 1264 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1266 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1267 #iommu-cells = <1>; 1268 }; 1269 1270 gic: interrupt-controller@f1000000 { 1271 compatible = "arm,gic-v3"; 1272 #interrupt-cells = <3>; 1273 #address-cells = <0>; 1274 interrupt-controller; 1275 reg = <0x0 0xf1000000 0 0x20000>, 1276 <0x0 0xf1060000 0 0x110000>; 1277 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1278 }; 1279 1280 prr: chipid@fff00044 { 1281 compatible = "renesas,prr"; 1282 reg = <0 0xfff00044 0 4>; 1283 }; 1284 }; 1285 1286 thermal-zones { 1287 sensor_thermal_rtcore: sensor1-thermal { 1288 polling-delay-passive = <250>; 1289 polling-delay = <1000>; 1290 thermal-sensors = <&tsc 0>; 1291 1292 trips { 1293 sensor1_crit: sensor1-crit { 1294 temperature = <120000>; 1295 hysteresis = <1000>; 1296 type = "critical"; 1297 }; 1298 }; 1299 }; 1300 1301 sensor_thermal_apcore0: sensor2-thermal { 1302 polling-delay-passive = <250>; 1303 polling-delay = <1000>; 1304 thermal-sensors = <&tsc 1>; 1305 1306 trips { 1307 sensor2_crit: sensor2-crit { 1308 temperature = <120000>; 1309 hysteresis = <1000>; 1310 type = "critical"; 1311 }; 1312 }; 1313 }; 1314 1315 sensor_thermal_apcore4: sensor3-thermal { 1316 polling-delay-passive = <250>; 1317 polling-delay = <1000>; 1318 thermal-sensors = <&tsc 2>; 1319 1320 trips { 1321 sensor3_crit: sensor3-crit { 1322 temperature = <120000>; 1323 hysteresis = <1000>; 1324 type = "critical"; 1325 }; 1326 }; 1327 }; 1328 }; 1329 1330 timer { 1331 compatible = "arm,armv8-timer"; 1332 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1333 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1334 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1335 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 1336 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 1337 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", 1338 "hyp-virt"; 1339 }; 1340 1341 ufs30_clk: ufs30-clk { 1342 compatible = "fixed-clock"; 1343 #clock-cells = <0>; 1344 /* This value must be overridden by the board */ 1345 clock-frequency = <0>; 1346 }; 1347}; 1348