1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car D3 (R8A77995) SoC 4 * 5 * Copyright (C) 2016 Renesas Electronics Corp. 6 * Copyright (C) 2017 Glider bvba 7 */ 8 9#include <dt-bindings/clock/r8a77995-cpg-mssr.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/r8a77995-sysc.h> 12 13/ { 14 compatible = "renesas,r8a77995"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 /* 19 * The external audio clocks are configured as 0 Hz fixed frequency 20 * clocks by default. 21 * Boards that provide audio clocks should override them. 22 */ 23 audio_clk_a: audio_clk_a { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 clock-frequency = <0>; 27 }; 28 29 audio_clk_b: audio_clk_b { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <0>; 33 }; 34 35 /* External CAN clock - to be overridden by boards that provide it */ 36 can_clk: can { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <0>; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 a53_0: cpu@0 { 47 compatible = "arm,cortex-a53"; 48 reg = <0x0>; 49 device_type = "cpu"; 50 power-domains = <&sysc R8A77995_PD_CA53_CPU0>; 51 next-level-cache = <&L2_CA53>; 52 enable-method = "psci"; 53 }; 54 55 L2_CA53: cache-controller-1 { 56 compatible = "cache"; 57 power-domains = <&sysc R8A77995_PD_CA53_SCU>; 58 cache-unified; 59 cache-level = <2>; 60 }; 61 }; 62 63 extal_clk: extal { 64 compatible = "fixed-clock"; 65 #clock-cells = <0>; 66 /* This value must be overridden by the board */ 67 clock-frequency = <0>; 68 }; 69 70 pmu_a53 { 71 compatible = "arm,cortex-a53-pmu"; 72 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 73 }; 74 75 psci { 76 compatible = "arm,psci-1.0", "arm,psci-0.2"; 77 method = "smc"; 78 }; 79 80 scif_clk: scif { 81 compatible = "fixed-clock"; 82 #clock-cells = <0>; 83 clock-frequency = <0>; 84 }; 85 86 soc { 87 compatible = "simple-bus"; 88 interrupt-parent = <&gic>; 89 #address-cells = <2>; 90 #size-cells = <2>; 91 ranges; 92 93 rwdt: watchdog@e6020000 { 94 compatible = "renesas,r8a77995-wdt", 95 "renesas,rcar-gen3-wdt"; 96 reg = <0 0xe6020000 0 0x0c>; 97 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 98 clocks = <&cpg CPG_MOD 402>; 99 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 100 resets = <&cpg 402>; 101 status = "disabled"; 102 }; 103 104 gpio0: gpio@e6050000 { 105 compatible = "renesas,gpio-r8a77995", 106 "renesas,rcar-gen3-gpio"; 107 reg = <0 0xe6050000 0 0x50>; 108 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 109 #gpio-cells = <2>; 110 gpio-controller; 111 gpio-ranges = <&pfc 0 0 9>; 112 #interrupt-cells = <2>; 113 interrupt-controller; 114 clocks = <&cpg CPG_MOD 912>; 115 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 116 resets = <&cpg 912>; 117 }; 118 119 gpio1: gpio@e6051000 { 120 compatible = "renesas,gpio-r8a77995", 121 "renesas,rcar-gen3-gpio"; 122 reg = <0 0xe6051000 0 0x50>; 123 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 124 #gpio-cells = <2>; 125 gpio-controller; 126 gpio-ranges = <&pfc 0 32 32>; 127 #interrupt-cells = <2>; 128 interrupt-controller; 129 clocks = <&cpg CPG_MOD 911>; 130 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 131 resets = <&cpg 911>; 132 }; 133 134 gpio2: gpio@e6052000 { 135 compatible = "renesas,gpio-r8a77995", 136 "renesas,rcar-gen3-gpio"; 137 reg = <0 0xe6052000 0 0x50>; 138 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 139 #gpio-cells = <2>; 140 gpio-controller; 141 gpio-ranges = <&pfc 0 64 32>; 142 #interrupt-cells = <2>; 143 interrupt-controller; 144 clocks = <&cpg CPG_MOD 910>; 145 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 146 resets = <&cpg 910>; 147 }; 148 149 gpio3: gpio@e6053000 { 150 compatible = "renesas,gpio-r8a77995", 151 "renesas,rcar-gen3-gpio"; 152 reg = <0 0xe6053000 0 0x50>; 153 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 154 #gpio-cells = <2>; 155 gpio-controller; 156 gpio-ranges = <&pfc 0 96 10>; 157 #interrupt-cells = <2>; 158 interrupt-controller; 159 clocks = <&cpg CPG_MOD 909>; 160 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 161 resets = <&cpg 909>; 162 }; 163 164 gpio4: gpio@e6054000 { 165 compatible = "renesas,gpio-r8a77995", 166 "renesas,rcar-gen3-gpio"; 167 reg = <0 0xe6054000 0 0x50>; 168 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 169 #gpio-cells = <2>; 170 gpio-controller; 171 gpio-ranges = <&pfc 0 128 32>; 172 #interrupt-cells = <2>; 173 interrupt-controller; 174 clocks = <&cpg CPG_MOD 908>; 175 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 176 resets = <&cpg 908>; 177 }; 178 179 gpio5: gpio@e6055000 { 180 compatible = "renesas,gpio-r8a77995", 181 "renesas,rcar-gen3-gpio"; 182 reg = <0 0xe6055000 0 0x50>; 183 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 184 #gpio-cells = <2>; 185 gpio-controller; 186 gpio-ranges = <&pfc 0 160 21>; 187 #interrupt-cells = <2>; 188 interrupt-controller; 189 clocks = <&cpg CPG_MOD 907>; 190 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 191 resets = <&cpg 907>; 192 }; 193 194 gpio6: gpio@e6055400 { 195 compatible = "renesas,gpio-r8a77995", 196 "renesas,rcar-gen3-gpio"; 197 reg = <0 0xe6055400 0 0x50>; 198 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 199 #gpio-cells = <2>; 200 gpio-controller; 201 gpio-ranges = <&pfc 0 192 14>; 202 #interrupt-cells = <2>; 203 interrupt-controller; 204 clocks = <&cpg CPG_MOD 906>; 205 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 206 resets = <&cpg 906>; 207 }; 208 209 pfc: pinctrl@e6060000 { 210 compatible = "renesas,pfc-r8a77995"; 211 reg = <0 0xe6060000 0 0x508>; 212 }; 213 214 cmt0: timer@e60f0000 { 215 compatible = "renesas,r8a77995-cmt0", 216 "renesas,rcar-gen3-cmt0"; 217 reg = <0 0xe60f0000 0 0x1004>; 218 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&cpg CPG_MOD 303>; 221 clock-names = "fck"; 222 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 223 resets = <&cpg 303>; 224 status = "disabled"; 225 }; 226 227 cmt1: timer@e6130000 { 228 compatible = "renesas,r8a77995-cmt1", 229 "renesas,rcar-gen3-cmt1"; 230 reg = <0 0xe6130000 0 0x1004>; 231 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&cpg CPG_MOD 302>; 240 clock-names = "fck"; 241 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 242 resets = <&cpg 302>; 243 status = "disabled"; 244 }; 245 246 cmt2: timer@e6140000 { 247 compatible = "renesas,r8a77995-cmt1", 248 "renesas,rcar-gen3-cmt1"; 249 reg = <0 0xe6140000 0 0x1004>; 250 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&cpg CPG_MOD 301>; 259 clock-names = "fck"; 260 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 261 resets = <&cpg 301>; 262 status = "disabled"; 263 }; 264 265 cmt3: timer@e6148000 { 266 compatible = "renesas,r8a77995-cmt1", 267 "renesas,rcar-gen3-cmt1"; 268 reg = <0 0xe6148000 0 0x1004>; 269 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&cpg CPG_MOD 300>; 278 clock-names = "fck"; 279 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 280 resets = <&cpg 300>; 281 status = "disabled"; 282 }; 283 284 cpg: clock-controller@e6150000 { 285 compatible = "renesas,r8a77995-cpg-mssr"; 286 reg = <0 0xe6150000 0 0x1000>; 287 clocks = <&extal_clk>; 288 clock-names = "extal"; 289 #clock-cells = <2>; 290 #power-domain-cells = <0>; 291 #reset-cells = <1>; 292 }; 293 294 rst: reset-controller@e6160000 { 295 compatible = "renesas,r8a77995-rst"; 296 reg = <0 0xe6160000 0 0x0200>; 297 }; 298 299 sysc: system-controller@e6180000 { 300 compatible = "renesas,r8a77995-sysc"; 301 reg = <0 0xe6180000 0 0x0400>; 302 #power-domain-cells = <1>; 303 }; 304 305 thermal: thermal@e6190000 { 306 compatible = "renesas,thermal-r8a77995"; 307 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; 308 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&cpg CPG_MOD 522>; 312 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 313 resets = <&cpg 522>; 314 #thermal-sensor-cells = <0>; 315 }; 316 317 intc_ex: interrupt-controller@e61c0000 { 318 compatible = "renesas,intc-ex-r8a77995", "renesas,irqc"; 319 #interrupt-cells = <2>; 320 interrupt-controller; 321 reg = <0 0xe61c0000 0 0x200>; 322 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&cpg CPG_MOD 407>; 329 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 330 resets = <&cpg 407>; 331 }; 332 333 tmu0: timer@e61e0000 { 334 compatible = "renesas,tmu-r8a77995", "renesas,tmu"; 335 reg = <0 0xe61e0000 0 0x30>; 336 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&cpg CPG_MOD 125>; 340 clock-names = "fck"; 341 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 342 resets = <&cpg 125>; 343 status = "disabled"; 344 }; 345 346 tmu1: timer@e6fc0000 { 347 compatible = "renesas,tmu-r8a77995", "renesas,tmu"; 348 reg = <0 0xe6fc0000 0 0x30>; 349 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 352 clocks = <&cpg CPG_MOD 124>; 353 clock-names = "fck"; 354 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 355 resets = <&cpg 124>; 356 status = "disabled"; 357 }; 358 359 tmu2: timer@e6fd0000 { 360 compatible = "renesas,tmu-r8a77995", "renesas,tmu"; 361 reg = <0 0xe6fd0000 0 0x30>; 362 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&cpg CPG_MOD 123>; 366 clock-names = "fck"; 367 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 368 resets = <&cpg 123>; 369 status = "disabled"; 370 }; 371 372 tmu3: timer@e6fe0000 { 373 compatible = "renesas,tmu-r8a77995", "renesas,tmu"; 374 reg = <0 0xe6fe0000 0 0x30>; 375 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&cpg CPG_MOD 122>; 379 clock-names = "fck"; 380 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 381 resets = <&cpg 122>; 382 status = "disabled"; 383 }; 384 385 tmu4: timer@ffc00000 { 386 compatible = "renesas,tmu-r8a77995", "renesas,tmu"; 387 reg = <0 0xffc00000 0 0x30>; 388 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 391 clocks = <&cpg CPG_MOD 121>; 392 clock-names = "fck"; 393 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 394 resets = <&cpg 121>; 395 status = "disabled"; 396 }; 397 398 i2c0: i2c@e6500000 { 399 #address-cells = <1>; 400 #size-cells = <0>; 401 compatible = "renesas,i2c-r8a77995", 402 "renesas,rcar-gen3-i2c"; 403 reg = <0 0xe6500000 0 0x40>; 404 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&cpg CPG_MOD 931>; 406 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 407 resets = <&cpg 931>; 408 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 409 <&dmac2 0x91>, <&dmac2 0x90>; 410 dma-names = "tx", "rx", "tx", "rx"; 411 i2c-scl-internal-delay-ns = <6>; 412 status = "disabled"; 413 }; 414 415 i2c1: i2c@e6508000 { 416 #address-cells = <1>; 417 #size-cells = <0>; 418 compatible = "renesas,i2c-r8a77995", 419 "renesas,rcar-gen3-i2c"; 420 reg = <0 0xe6508000 0 0x40>; 421 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&cpg CPG_MOD 930>; 423 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 424 resets = <&cpg 930>; 425 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 426 <&dmac2 0x93>, <&dmac2 0x92>; 427 dma-names = "tx", "rx", "tx", "rx"; 428 i2c-scl-internal-delay-ns = <6>; 429 status = "disabled"; 430 }; 431 432 i2c2: i2c@e6510000 { 433 #address-cells = <1>; 434 #size-cells = <0>; 435 compatible = "renesas,i2c-r8a77995", 436 "renesas,rcar-gen3-i2c"; 437 reg = <0 0xe6510000 0 0x40>; 438 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&cpg CPG_MOD 929>; 440 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 441 resets = <&cpg 929>; 442 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 443 <&dmac2 0x95>, <&dmac2 0x94>; 444 dma-names = "tx", "rx", "tx", "rx"; 445 i2c-scl-internal-delay-ns = <6>; 446 status = "disabled"; 447 }; 448 449 i2c3: i2c@e66d0000 { 450 #address-cells = <1>; 451 #size-cells = <0>; 452 compatible = "renesas,i2c-r8a77995", 453 "renesas,rcar-gen3-i2c"; 454 reg = <0 0xe66d0000 0 0x40>; 455 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&cpg CPG_MOD 928>; 457 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 458 resets = <&cpg 928>; 459 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 460 dma-names = "tx", "rx"; 461 i2c-scl-internal-delay-ns = <6>; 462 status = "disabled"; 463 }; 464 465 hscif0: serial@e6540000 { 466 compatible = "renesas,hscif-r8a77995", 467 "renesas,rcar-gen3-hscif", 468 "renesas,hscif"; 469 reg = <0 0xe6540000 0 0x60>; 470 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&cpg CPG_MOD 520>, 472 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 473 <&scif_clk>; 474 clock-names = "fck", "brg_int", "scif_clk"; 475 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 476 <&dmac2 0x31>, <&dmac2 0x30>; 477 dma-names = "tx", "rx", "tx", "rx"; 478 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 479 resets = <&cpg 520>; 480 status = "disabled"; 481 }; 482 483 hscif3: serial@e66a0000 { 484 compatible = "renesas,hscif-r8a77995", 485 "renesas,rcar-gen3-hscif", 486 "renesas,hscif"; 487 reg = <0 0xe66a0000 0 0x60>; 488 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&cpg CPG_MOD 517>, 490 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 491 <&scif_clk>; 492 clock-names = "fck", "brg_int", "scif_clk"; 493 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 494 dma-names = "tx", "rx"; 495 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 496 resets = <&cpg 517>; 497 status = "disabled"; 498 }; 499 500 hsusb: usb@e6590000 { 501 compatible = "renesas,usbhs-r8a77995", 502 "renesas,rcar-gen3-usbhs"; 503 reg = <0 0xe6590000 0 0x200>; 504 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 506 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 507 <&usb_dmac1 0>, <&usb_dmac1 1>; 508 dma-names = "ch0", "ch1", "ch2", "ch3"; 509 renesas,buswait = <11>; 510 phys = <&usb2_phy0 3>; 511 phy-names = "usb"; 512 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 513 resets = <&cpg 704>, <&cpg 703>; 514 status = "disabled"; 515 }; 516 517 usb_dmac0: dma-controller@e65a0000 { 518 compatible = "renesas,r8a77995-usb-dmac", 519 "renesas,usb-dmac"; 520 reg = <0 0xe65a0000 0 0x100>; 521 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 523 interrupt-names = "ch0", "ch1"; 524 clocks = <&cpg CPG_MOD 330>; 525 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 526 resets = <&cpg 330>; 527 #dma-cells = <1>; 528 dma-channels = <2>; 529 }; 530 531 usb_dmac1: dma-controller@e65b0000 { 532 compatible = "renesas,r8a77995-usb-dmac", 533 "renesas,usb-dmac"; 534 reg = <0 0xe65b0000 0 0x100>; 535 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 537 interrupt-names = "ch0", "ch1"; 538 clocks = <&cpg CPG_MOD 331>; 539 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 540 resets = <&cpg 331>; 541 #dma-cells = <1>; 542 dma-channels = <2>; 543 }; 544 545 arm_cc630p: crypto@e6601000 { 546 compatible = "arm,cryptocell-630p-ree"; 547 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 548 reg = <0x0 0xe6601000 0 0x1000>; 549 clocks = <&cpg CPG_MOD 229>; 550 resets = <&cpg 229>; 551 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 552 }; 553 554 canfd: can@e66c0000 { 555 compatible = "renesas,r8a77995-canfd", 556 "renesas,rcar-gen3-canfd"; 557 reg = <0 0xe66c0000 0 0x8000>; 558 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&cpg CPG_MOD 914>, 561 <&cpg CPG_CORE R8A77995_CLK_CANFD>, 562 <&can_clk>; 563 clock-names = "fck", "canfd", "can_clk"; 564 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; 565 assigned-clock-rates = <40000000>; 566 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 567 resets = <&cpg 914>; 568 status = "disabled"; 569 570 channel0 { 571 status = "disabled"; 572 }; 573 574 channel1 { 575 status = "disabled"; 576 }; 577 }; 578 579 dmac0: dma-controller@e6700000 { 580 compatible = "renesas,dmac-r8a77995", 581 "renesas,rcar-dmac"; 582 reg = <0 0xe6700000 0 0x10000>; 583 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 592 interrupt-names = "error", 593 "ch0", "ch1", "ch2", "ch3", 594 "ch4", "ch5", "ch6", "ch7"; 595 clocks = <&cpg CPG_MOD 219>; 596 clock-names = "fck"; 597 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 598 resets = <&cpg 219>; 599 #dma-cells = <1>; 600 dma-channels = <8>; 601 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 602 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 603 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 604 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>; 605 }; 606 607 dmac1: dma-controller@e7300000 { 608 compatible = "renesas,dmac-r8a77995", 609 "renesas,rcar-dmac"; 610 reg = <0 0xe7300000 0 0x10000>; 611 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 620 interrupt-names = "error", 621 "ch0", "ch1", "ch2", "ch3", 622 "ch4", "ch5", "ch6", "ch7"; 623 clocks = <&cpg CPG_MOD 218>; 624 clock-names = "fck"; 625 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 626 resets = <&cpg 218>; 627 #dma-cells = <1>; 628 dma-channels = <8>; 629 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 630 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 631 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 632 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; 633 }; 634 635 dmac2: dma-controller@e7310000 { 636 compatible = "renesas,dmac-r8a77995", 637 "renesas,rcar-dmac"; 638 reg = <0 0xe7310000 0 0x10000>; 639 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; 648 interrupt-names = "error", 649 "ch0", "ch1", "ch2", "ch3", 650 "ch4", "ch5", "ch6", "ch7"; 651 clocks = <&cpg CPG_MOD 217>; 652 clock-names = "fck"; 653 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 654 resets = <&cpg 217>; 655 #dma-cells = <1>; 656 dma-channels = <8>; 657 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 658 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 659 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 660 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; 661 }; 662 663 ipmmu_ds0: iommu@e6740000 { 664 compatible = "renesas,ipmmu-r8a77995"; 665 reg = <0 0xe6740000 0 0x1000>; 666 renesas,ipmmu-main = <&ipmmu_mm 0>; 667 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 668 #iommu-cells = <1>; 669 }; 670 671 ipmmu_ds1: iommu@e7740000 { 672 compatible = "renesas,ipmmu-r8a77995"; 673 reg = <0 0xe7740000 0 0x1000>; 674 renesas,ipmmu-main = <&ipmmu_mm 1>; 675 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 676 #iommu-cells = <1>; 677 }; 678 679 ipmmu_hc: iommu@e6570000 { 680 compatible = "renesas,ipmmu-r8a77995"; 681 reg = <0 0xe6570000 0 0x1000>; 682 renesas,ipmmu-main = <&ipmmu_mm 2>; 683 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 684 #iommu-cells = <1>; 685 }; 686 687 ipmmu_mm: iommu@e67b0000 { 688 compatible = "renesas,ipmmu-r8a77995"; 689 reg = <0 0xe67b0000 0 0x1000>; 690 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 692 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 693 #iommu-cells = <1>; 694 }; 695 696 ipmmu_mp: iommu@ec670000 { 697 compatible = "renesas,ipmmu-r8a77995"; 698 reg = <0 0xec670000 0 0x1000>; 699 renesas,ipmmu-main = <&ipmmu_mm 4>; 700 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 701 #iommu-cells = <1>; 702 }; 703 704 ipmmu_pv0: iommu@fd800000 { 705 compatible = "renesas,ipmmu-r8a77995"; 706 reg = <0 0xfd800000 0 0x1000>; 707 renesas,ipmmu-main = <&ipmmu_mm 6>; 708 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 709 #iommu-cells = <1>; 710 }; 711 712 ipmmu_rt: iommu@ffc80000 { 713 compatible = "renesas,ipmmu-r8a77995"; 714 reg = <0 0xffc80000 0 0x1000>; 715 renesas,ipmmu-main = <&ipmmu_mm 10>; 716 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 717 #iommu-cells = <1>; 718 }; 719 720 ipmmu_vc0: iommu@fe6b0000 { 721 compatible = "renesas,ipmmu-r8a77995"; 722 reg = <0 0xfe6b0000 0 0x1000>; 723 renesas,ipmmu-main = <&ipmmu_mm 12>; 724 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 725 #iommu-cells = <1>; 726 }; 727 728 ipmmu_vi0: iommu@febd0000 { 729 compatible = "renesas,ipmmu-r8a77995"; 730 reg = <0 0xfebd0000 0 0x1000>; 731 renesas,ipmmu-main = <&ipmmu_mm 14>; 732 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 733 #iommu-cells = <1>; 734 }; 735 736 ipmmu_vp0: iommu@fe990000 { 737 compatible = "renesas,ipmmu-r8a77995"; 738 reg = <0 0xfe990000 0 0x1000>; 739 renesas,ipmmu-main = <&ipmmu_mm 16>; 740 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 741 #iommu-cells = <1>; 742 }; 743 744 avb: ethernet@e6800000 { 745 compatible = "renesas,etheravb-r8a77995", 746 "renesas,etheravb-rcar-gen3"; 747 reg = <0 0xe6800000 0 0x800>; 748 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 773 interrupt-names = "ch0", "ch1", "ch2", "ch3", 774 "ch4", "ch5", "ch6", "ch7", 775 "ch8", "ch9", "ch10", "ch11", 776 "ch12", "ch13", "ch14", "ch15", 777 "ch16", "ch17", "ch18", "ch19", 778 "ch20", "ch21", "ch22", "ch23", 779 "ch24"; 780 clocks = <&cpg CPG_MOD 812>; 781 clock-names = "fck"; 782 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 783 resets = <&cpg 812>; 784 phy-mode = "rgmii"; 785 rx-internal-delay-ps = <1800>; 786 iommus = <&ipmmu_ds0 16>; 787 #address-cells = <1>; 788 #size-cells = <0>; 789 status = "disabled"; 790 }; 791 792 can0: can@e6c30000 { 793 compatible = "renesas,can-r8a77995", 794 "renesas,rcar-gen3-can"; 795 reg = <0 0xe6c30000 0 0x1000>; 796 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 797 clocks = <&cpg CPG_MOD 916>, 798 <&cpg CPG_CORE R8A77995_CLK_CANFD>, 799 <&can_clk>; 800 clock-names = "clkp1", "clkp2", "can_clk"; 801 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; 802 assigned-clock-rates = <40000000>; 803 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 804 resets = <&cpg 916>; 805 status = "disabled"; 806 }; 807 808 can1: can@e6c38000 { 809 compatible = "renesas,can-r8a77995", 810 "renesas,rcar-gen3-can"; 811 reg = <0 0xe6c38000 0 0x1000>; 812 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&cpg CPG_MOD 915>, 814 <&cpg CPG_CORE R8A77995_CLK_CANFD>, 815 <&can_clk>; 816 clock-names = "clkp1", "clkp2", "can_clk"; 817 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; 818 assigned-clock-rates = <40000000>; 819 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 820 resets = <&cpg 915>; 821 status = "disabled"; 822 }; 823 824 pwm0: pwm@e6e30000 { 825 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 826 reg = <0 0xe6e30000 0 0x8>; 827 #pwm-cells = <2>; 828 clocks = <&cpg CPG_MOD 523>; 829 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 830 resets = <&cpg 523>; 831 status = "disabled"; 832 }; 833 834 pwm1: pwm@e6e31000 { 835 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 836 reg = <0 0xe6e31000 0 0x8>; 837 #pwm-cells = <2>; 838 clocks = <&cpg CPG_MOD 523>; 839 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 840 resets = <&cpg 523>; 841 status = "disabled"; 842 }; 843 844 pwm2: pwm@e6e32000 { 845 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 846 reg = <0 0xe6e32000 0 0x8>; 847 #pwm-cells = <2>; 848 clocks = <&cpg CPG_MOD 523>; 849 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 850 resets = <&cpg 523>; 851 status = "disabled"; 852 }; 853 854 pwm3: pwm@e6e33000 { 855 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 856 reg = <0 0xe6e33000 0 0x8>; 857 #pwm-cells = <2>; 858 clocks = <&cpg CPG_MOD 523>; 859 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 860 resets = <&cpg 523>; 861 status = "disabled"; 862 }; 863 864 scif0: serial@e6e60000 { 865 compatible = "renesas,scif-r8a77995", 866 "renesas,rcar-gen3-scif", "renesas,scif"; 867 reg = <0 0xe6e60000 0 64>; 868 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&cpg CPG_MOD 207>, 870 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 871 <&scif_clk>; 872 clock-names = "fck", "brg_int", "scif_clk"; 873 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 874 <&dmac2 0x51>, <&dmac2 0x50>; 875 dma-names = "tx", "rx", "tx", "rx"; 876 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 877 resets = <&cpg 207>; 878 status = "disabled"; 879 }; 880 881 scif1: serial@e6e68000 { 882 compatible = "renesas,scif-r8a77995", 883 "renesas,rcar-gen3-scif", "renesas,scif"; 884 reg = <0 0xe6e68000 0 64>; 885 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 886 clocks = <&cpg CPG_MOD 206>, 887 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 888 <&scif_clk>; 889 clock-names = "fck", "brg_int", "scif_clk"; 890 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 891 <&dmac2 0x53>, <&dmac2 0x52>; 892 dma-names = "tx", "rx", "tx", "rx"; 893 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 894 resets = <&cpg 206>; 895 status = "disabled"; 896 }; 897 898 scif2: serial@e6e88000 { 899 compatible = "renesas,scif-r8a77995", 900 "renesas,rcar-gen3-scif", "renesas,scif"; 901 reg = <0 0xe6e88000 0 64>; 902 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 903 clocks = <&cpg CPG_MOD 310>, 904 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 905 <&scif_clk>; 906 clock-names = "fck", "brg_int", "scif_clk"; 907 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 908 <&dmac2 0x13>, <&dmac2 0x12>; 909 dma-names = "tx", "rx", "tx", "rx"; 910 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 911 resets = <&cpg 310>; 912 status = "disabled"; 913 }; 914 915 scif3: serial@e6c50000 { 916 compatible = "renesas,scif-r8a77995", 917 "renesas,rcar-gen3-scif", "renesas,scif"; 918 reg = <0 0xe6c50000 0 64>; 919 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 920 clocks = <&cpg CPG_MOD 204>, 921 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 922 <&scif_clk>; 923 clock-names = "fck", "brg_int", "scif_clk"; 924 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 925 dma-names = "tx", "rx"; 926 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 927 resets = <&cpg 204>; 928 status = "disabled"; 929 }; 930 931 scif4: serial@e6c40000 { 932 compatible = "renesas,scif-r8a77995", 933 "renesas,rcar-gen3-scif", "renesas,scif"; 934 reg = <0 0xe6c40000 0 64>; 935 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 936 clocks = <&cpg CPG_MOD 203>, 937 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 938 <&scif_clk>; 939 clock-names = "fck", "brg_int", "scif_clk"; 940 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 941 dma-names = "tx", "rx"; 942 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 943 resets = <&cpg 203>; 944 status = "disabled"; 945 }; 946 947 scif5: serial@e6f30000 { 948 compatible = "renesas,scif-r8a77995", 949 "renesas,rcar-gen3-scif", "renesas,scif"; 950 reg = <0 0xe6f30000 0 64>; 951 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 952 clocks = <&cpg CPG_MOD 202>, 953 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 954 <&scif_clk>; 955 clock-names = "fck", "brg_int", "scif_clk"; 956 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 957 <&dmac2 0x5b>, <&dmac2 0x5a>; 958 dma-names = "tx", "rx", "tx", "rx"; 959 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 960 resets = <&cpg 202>; 961 status = "disabled"; 962 }; 963 964 msiof0: spi@e6e90000 { 965 compatible = "renesas,msiof-r8a77995", 966 "renesas,rcar-gen3-msiof"; 967 reg = <0 0xe6e90000 0 0x64>; 968 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 969 clocks = <&cpg CPG_MOD 211>; 970 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 971 <&dmac2 0x41>, <&dmac2 0x40>; 972 dma-names = "tx", "rx", "tx", "rx"; 973 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 974 resets = <&cpg 211>; 975 #address-cells = <1>; 976 #size-cells = <0>; 977 status = "disabled"; 978 }; 979 980 msiof1: spi@e6ea0000 { 981 compatible = "renesas,msiof-r8a77995", 982 "renesas,rcar-gen3-msiof"; 983 reg = <0 0xe6ea0000 0 0x64>; 984 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 985 clocks = <&cpg CPG_MOD 210>; 986 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 987 <&dmac2 0x43>, <&dmac2 0x42>; 988 dma-names = "tx", "rx", "tx", "rx"; 989 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 990 resets = <&cpg 210>; 991 #address-cells = <1>; 992 #size-cells = <0>; 993 status = "disabled"; 994 }; 995 996 msiof2: spi@e6c00000 { 997 compatible = "renesas,msiof-r8a77995", 998 "renesas,rcar-gen3-msiof"; 999 reg = <0 0xe6c00000 0 0x64>; 1000 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1001 clocks = <&cpg CPG_MOD 209>; 1002 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1003 dma-names = "tx", "rx"; 1004 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1005 resets = <&cpg 209>; 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 status = "disabled"; 1009 }; 1010 1011 msiof3: spi@e6c10000 { 1012 compatible = "renesas,msiof-r8a77995", 1013 "renesas,rcar-gen3-msiof"; 1014 reg = <0 0xe6c10000 0 0x64>; 1015 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1016 clocks = <&cpg CPG_MOD 208>; 1017 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1018 dma-names = "tx", "rx"; 1019 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1020 resets = <&cpg 208>; 1021 #address-cells = <1>; 1022 #size-cells = <0>; 1023 status = "disabled"; 1024 }; 1025 1026 vin4: video@e6ef4000 { 1027 compatible = "renesas,vin-r8a77995"; 1028 reg = <0 0xe6ef4000 0 0x1000>; 1029 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1030 clocks = <&cpg CPG_MOD 807>; 1031 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1032 resets = <&cpg 807>; 1033 renesas,id = <4>; 1034 status = "disabled"; 1035 }; 1036 1037 rcar_sound: sound@ec500000 { 1038 /* 1039 * #sound-dai-cells is required 1040 * 1041 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1042 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1043 */ 1044 /* 1045 * #clock-cells is required for audio_clkout0/1/2/3 1046 * 1047 * clkout : #clock-cells = <0>; <&rcar_sound>; 1048 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1049 */ 1050 compatible = "renesas,rcar_sound-r8a77995", "renesas,rcar_sound-gen3"; 1051 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1052 <0 0xec5a0000 0 0x100>, /* ADG */ 1053 <0 0xec540000 0 0x1000>, /* SSIU */ 1054 <0 0xec541000 0 0x280>, /* SSI */ 1055 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ 1056 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1057 1058 clocks = <&cpg CPG_MOD 1005>, 1059 <&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>, 1060 <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, 1061 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1062 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1063 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1064 <&audio_clk_a>, <&audio_clk_b>, 1065 <&cpg CPG_CORE R8A77995_CLK_ZA2>; 1066 clock-names = "ssi-all", 1067 "ssi.4", "ssi.3", 1068 "src.6", "src.5", 1069 "mix.1", "mix.0", 1070 "ctu.1", "ctu.0", 1071 "dvc.0", "dvc.1", 1072 "clk_a", "clk_b", "clk_i"; 1073 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1074 resets = <&cpg 1005>, 1075 <&cpg 1011>, <&cpg 1012>; 1076 reset-names = "ssi-all", 1077 "ssi.4", "ssi.3"; 1078 status = "disabled"; 1079 1080 rcar_sound,ctu { 1081 ctu00: ctu-0 { }; 1082 ctu01: ctu-1 { }; 1083 ctu02: ctu-2 { }; 1084 ctu03: ctu-3 { }; 1085 ctu10: ctu-4 { }; 1086 ctu11: ctu-5 { }; 1087 ctu12: ctu-6 { }; 1088 ctu13: ctu-7 { }; 1089 }; 1090 1091 rcar_sound,dvc { 1092 dvc0: dvc-0 { 1093 dmas = <&audma0 0xbc>; 1094 dma-names = "tx"; 1095 }; 1096 dvc1: dvc-1 { 1097 dmas = <&audma0 0xbe>; 1098 dma-names = "tx"; 1099 }; 1100 }; 1101 1102 rcar_sound,mix { 1103 mix0: mix-0 { }; 1104 mix1: mix-1 { }; 1105 }; 1106 1107 rcar_sound,src { 1108 src5: src-5 { 1109 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1110 dmas = <&audma0 0x8f>, <&audma0 0xb2>; 1111 dma-names = "rx", "tx"; 1112 }; 1113 src6: src-6 { 1114 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1115 dmas = <&audma0 0x91>, <&audma0 0xb4>; 1116 dma-names = "rx", "tx"; 1117 }; 1118 }; 1119 1120 rcar_sound,ssi { 1121 ssi3: ssi-3 { 1122 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1123 dmas = <&audma0 0x07>, <&audma0 0x08>, 1124 <&audma0 0x6f>, <&audma0 0x70>; 1125 dma-names = "rx", "tx", "rxu", "txu"; 1126 }; 1127 ssi4: ssi-4 { 1128 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1129 dmas = <&audma0 0x09>, <&audma0 0x0a>, 1130 <&audma0 0x71>, <&audma0 0x72>; 1131 dma-names = "rx", "tx", "rxu", "txu"; 1132 }; 1133 }; 1134 }; 1135 1136 mlp: mlp@ec520000 { 1137 compatible = "renesas,r8a77995-mlp", 1138 "renesas,rcar-gen3-mlp"; 1139 reg = <0 0xec520000 0 0x800>; 1140 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>; 1142 clocks = <&cpg CPG_MOD 802>; 1143 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1144 resets = <&cpg 802>; 1145 status = "disabled"; 1146 }; 1147 1148 audma0: dma-controller@ec700000 { 1149 compatible = "renesas,dmac-r8a77995", 1150 "renesas,rcar-dmac"; 1151 reg = <0 0xec700000 0 0x10000>; 1152 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1169 interrupt-names = "error", 1170 "ch0", "ch1", "ch2", "ch3", 1171 "ch4", "ch5", "ch6", "ch7", 1172 "ch8", "ch9", "ch10", "ch11", 1173 "ch12", "ch13", "ch14", "ch15"; 1174 clocks = <&cpg CPG_MOD 502>; 1175 clock-names = "fck"; 1176 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1177 resets = <&cpg 502>; 1178 #dma-cells = <1>; 1179 dma-channels = <16>; 1180 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 1181 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 1182 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 1183 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 1184 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 1185 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 1186 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 1187 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 1188 }; 1189 1190 ohci0: usb@ee080000 { 1191 compatible = "generic-ohci"; 1192 reg = <0 0xee080000 0 0x100>; 1193 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1194 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1195 phys = <&usb2_phy0 1>; 1196 phy-names = "usb"; 1197 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1198 resets = <&cpg 703>, <&cpg 704>; 1199 status = "disabled"; 1200 }; 1201 1202 ehci0: usb@ee080100 { 1203 compatible = "generic-ehci"; 1204 reg = <0 0xee080100 0 0x100>; 1205 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1206 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1207 phys = <&usb2_phy0 2>; 1208 phy-names = "usb"; 1209 companion = <&ohci0>; 1210 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1211 resets = <&cpg 703>, <&cpg 704>; 1212 status = "disabled"; 1213 }; 1214 1215 usb2_phy0: usb-phy@ee080200 { 1216 compatible = "renesas,usb2-phy-r8a77995", 1217 "renesas,rcar-gen3-usb2-phy"; 1218 reg = <0 0xee080200 0 0x700>; 1219 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1220 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1221 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1222 resets = <&cpg 703>, <&cpg 704>; 1223 #phy-cells = <1>; 1224 status = "disabled"; 1225 }; 1226 1227 sdhi2: mmc@ee140000 { 1228 compatible = "renesas,sdhi-r8a77995", 1229 "renesas,rcar-gen3-sdhi"; 1230 reg = <0 0xee140000 0 0x2000>; 1231 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1232 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77995_CLK_SD0H>; 1233 clock-names = "core", "clkh"; 1234 max-frequency = <200000000>; 1235 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1236 resets = <&cpg 312>; 1237 iommus = <&ipmmu_ds1 34>; 1238 status = "disabled"; 1239 }; 1240 1241 gic: interrupt-controller@f1010000 { 1242 compatible = "arm,gic-400"; 1243 #interrupt-cells = <3>; 1244 #address-cells = <0>; 1245 interrupt-controller; 1246 reg = <0x0 0xf1010000 0 0x1000>, 1247 <0x0 0xf1020000 0 0x20000>, 1248 <0x0 0xf1040000 0 0x20000>, 1249 <0x0 0xf1060000 0 0x20000>; 1250 interrupts = <GIC_PPI 9 1251 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 1252 clocks = <&cpg CPG_MOD 408>; 1253 clock-names = "clk"; 1254 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1255 resets = <&cpg 408>; 1256 }; 1257 1258 vspbs: vsp@fe960000 { 1259 compatible = "renesas,vsp2"; 1260 reg = <0 0xfe960000 0 0x8000>; 1261 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1262 clocks = <&cpg CPG_MOD 627>; 1263 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1264 resets = <&cpg 627>; 1265 renesas,fcp = <&fcpvb0>; 1266 }; 1267 1268 vspd0: vsp@fea20000 { 1269 compatible = "renesas,vsp2"; 1270 reg = <0 0xfea20000 0 0x5000>; 1271 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1272 clocks = <&cpg CPG_MOD 623>; 1273 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1274 resets = <&cpg 623>; 1275 renesas,fcp = <&fcpvd0>; 1276 }; 1277 1278 vspd1: vsp@fea28000 { 1279 compatible = "renesas,vsp2"; 1280 reg = <0 0xfea28000 0 0x5000>; 1281 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1282 clocks = <&cpg CPG_MOD 622>; 1283 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1284 resets = <&cpg 622>; 1285 renesas,fcp = <&fcpvd1>; 1286 }; 1287 1288 fcpvb0: fcp@fe96f000 { 1289 compatible = "renesas,fcpv"; 1290 reg = <0 0xfe96f000 0 0x200>; 1291 clocks = <&cpg CPG_MOD 607>; 1292 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1293 resets = <&cpg 607>; 1294 iommus = <&ipmmu_vp0 5>; 1295 }; 1296 1297 fcpvd0: fcp@fea27000 { 1298 compatible = "renesas,fcpv"; 1299 reg = <0 0xfea27000 0 0x200>; 1300 clocks = <&cpg CPG_MOD 603>; 1301 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1302 resets = <&cpg 603>; 1303 iommus = <&ipmmu_vi0 8>; 1304 }; 1305 1306 fcpvd1: fcp@fea2f000 { 1307 compatible = "renesas,fcpv"; 1308 reg = <0 0xfea2f000 0 0x200>; 1309 clocks = <&cpg CPG_MOD 602>; 1310 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1311 resets = <&cpg 602>; 1312 iommus = <&ipmmu_vi0 9>; 1313 }; 1314 1315 cmm0: cmm@fea40000 { 1316 compatible = "renesas,r8a77995-cmm", 1317 "renesas,rcar-gen3-cmm"; 1318 reg = <0 0xfea40000 0 0x1000>; 1319 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1320 clocks = <&cpg CPG_MOD 711>; 1321 resets = <&cpg 711>; 1322 }; 1323 1324 cmm1: cmm@fea50000 { 1325 compatible = "renesas,r8a77995-cmm", 1326 "renesas,rcar-gen3-cmm"; 1327 reg = <0 0xfea50000 0 0x1000>; 1328 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1329 clocks = <&cpg CPG_MOD 710>; 1330 resets = <&cpg 710>; 1331 }; 1332 1333 du: display@feb00000 { 1334 compatible = "renesas,du-r8a77995"; 1335 reg = <0 0xfeb00000 0 0x40000>; 1336 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1337 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1338 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; 1339 clock-names = "du.0", "du.1"; 1340 resets = <&cpg 724>; 1341 reset-names = "du.0"; 1342 1343 renesas,cmms = <&cmm0>, <&cmm1>; 1344 renesas,vsps = <&vspd0 0>, <&vspd1 0>; 1345 1346 status = "disabled"; 1347 1348 ports { 1349 #address-cells = <1>; 1350 #size-cells = <0>; 1351 1352 port@0 { 1353 reg = <0>; 1354 du_out_rgb: endpoint { 1355 }; 1356 }; 1357 1358 port@1 { 1359 reg = <1>; 1360 du_out_lvds0: endpoint { 1361 remote-endpoint = <&lvds0_in>; 1362 }; 1363 }; 1364 1365 port@2 { 1366 reg = <2>; 1367 du_out_lvds1: endpoint { 1368 remote-endpoint = <&lvds1_in>; 1369 }; 1370 }; 1371 }; 1372 }; 1373 1374 lvds0: lvds-encoder@feb90000 { 1375 compatible = "renesas,r8a77995-lvds"; 1376 reg = <0 0xfeb90000 0 0x20>; 1377 clocks = <&cpg CPG_MOD 727>; 1378 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1379 resets = <&cpg 727>; 1380 status = "disabled"; 1381 1382 renesas,companion = <&lvds1>; 1383 1384 ports { 1385 #address-cells = <1>; 1386 #size-cells = <0>; 1387 1388 port@0 { 1389 reg = <0>; 1390 lvds0_in: endpoint { 1391 remote-endpoint = <&du_out_lvds0>; 1392 }; 1393 }; 1394 1395 port@1 { 1396 reg = <1>; 1397 lvds0_out: endpoint { 1398 }; 1399 }; 1400 }; 1401 }; 1402 1403 lvds1: lvds-encoder@feb90100 { 1404 compatible = "renesas,r8a77995-lvds"; 1405 reg = <0 0xfeb90100 0 0x20>; 1406 clocks = <&cpg CPG_MOD 727>; 1407 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1408 resets = <&cpg 726>; 1409 status = "disabled"; 1410 1411 ports { 1412 #address-cells = <1>; 1413 #size-cells = <0>; 1414 1415 port@0 { 1416 reg = <0>; 1417 lvds1_in: endpoint { 1418 remote-endpoint = <&du_out_lvds1>; 1419 }; 1420 }; 1421 1422 port@1 { 1423 reg = <1>; 1424 lvds1_out: endpoint { 1425 }; 1426 }; 1427 }; 1428 }; 1429 1430 prr: chipid@fff00044 { 1431 compatible = "renesas,prr"; 1432 reg = <0 0xfff00044 0 4>; 1433 }; 1434 }; 1435 1436 thermal-zones { 1437 cpu_thermal: cpu-thermal { 1438 polling-delay-passive = <250>; 1439 polling-delay = <1000>; 1440 thermal-sensors = <&thermal>; 1441 1442 cooling-maps { 1443 }; 1444 1445 trips { 1446 cpu-crit { 1447 temperature = <120000>; 1448 hysteresis = <2000>; 1449 type = "critical"; 1450 }; 1451 }; 1452 }; 1453 }; 1454 1455 timer { 1456 compatible = "arm,armv8-timer"; 1457 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 1458 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 1459 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 1460 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 1461 }; 1462}; 1463