1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the Draak board 4 * 5 * Copyright (C) 2016-2018 Renesas Electronics Corp. 6 * Copyright (C) 2017 Glider bvba 7 */ 8 9/dts-v1/; 10#include "r8a77995.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12 13/ { 14 model = "Renesas Draak board based on r8a77995"; 15 compatible = "renesas,draak", "renesas,r8a77995"; 16 17 aliases { 18 serial0 = &scif2; 19 ethernet0 = &avb; 20 }; 21 22 backlight: backlight { 23 compatible = "pwm-backlight"; 24 pwms = <&pwm1 0 50000>; 25 26 brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>; 27 default-brightness-level = <10>; 28 29 power-supply = <®_12p0v>; 30 enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; 31 }; 32 33 chosen { 34 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 35 stdout-path = "serial0:115200n8"; 36 }; 37 38 composite-in { 39 compatible = "composite-video-connector"; 40 41 port { 42 composite_con_in: endpoint { 43 remote-endpoint = <&adv7180_in>; 44 }; 45 }; 46 }; 47 48 hdmi-in { 49 compatible = "hdmi-connector"; 50 type = "a"; 51 52 port { 53 hdmi_con_in: endpoint { 54 remote-endpoint = <&adv7612_in>; 55 }; 56 }; 57 }; 58 59 hdmi-out { 60 compatible = "hdmi-connector"; 61 type = "a"; 62 63 port { 64 hdmi_con_out: endpoint { 65 remote-endpoint = <&adv7511_out>; 66 }; 67 }; 68 }; 69 70 lvds-decoder { 71 compatible = "thine,thc63lvd1024"; 72 vcc-supply = <®_3p3v>; 73 74 ports { 75 #address-cells = <1>; 76 #size-cells = <0>; 77 78 port@0 { 79 reg = <0>; 80 thc63lvd1024_in: endpoint { 81 remote-endpoint = <&lvds0_out>; 82 }; 83 }; 84 85 port@2 { 86 reg = <2>; 87 thc63lvd1024_out: endpoint { 88 remote-endpoint = <&adv7511_in>; 89 }; 90 }; 91 }; 92 }; 93 94 memory@48000000 { 95 device_type = "memory"; 96 /* first 128MB is reserved for secure area. */ 97 reg = <0x0 0x48000000 0x0 0x18000000>; 98 }; 99 100 reg_1p8v: regulator-1p8v { 101 compatible = "regulator-fixed"; 102 regulator-name = "fixed-1.8V"; 103 regulator-min-microvolt = <1800000>; 104 regulator-max-microvolt = <1800000>; 105 regulator-boot-on; 106 regulator-always-on; 107 }; 108 109 reg_3p3v: regulator-3p3v { 110 compatible = "regulator-fixed"; 111 regulator-name = "fixed-3.3V"; 112 regulator-min-microvolt = <3300000>; 113 regulator-max-microvolt = <3300000>; 114 regulator-boot-on; 115 regulator-always-on; 116 }; 117 118 reg_12p0v: regulator-12p0v { 119 compatible = "regulator-fixed"; 120 regulator-name = "D12.0V"; 121 regulator-min-microvolt = <12000000>; 122 regulator-max-microvolt = <12000000>; 123 regulator-boot-on; 124 regulator-always-on; 125 }; 126 127 vga { 128 compatible = "vga-connector"; 129 130 port { 131 vga_in: endpoint { 132 remote-endpoint = <&adv7123_out>; 133 }; 134 }; 135 }; 136 137 vga-encoder { 138 compatible = "adi,adv7123"; 139 140 ports { 141 #address-cells = <1>; 142 #size-cells = <0>; 143 144 port@0 { 145 reg = <0>; 146 adv7123_in: endpoint { 147 remote-endpoint = <&du_out_rgb>; 148 }; 149 }; 150 port@1 { 151 reg = <1>; 152 adv7123_out: endpoint { 153 remote-endpoint = <&vga_in>; 154 }; 155 }; 156 }; 157 }; 158 159 x12_clk: x12 { 160 compatible = "fixed-clock"; 161 #clock-cells = <0>; 162 clock-frequency = <74250000>; 163 }; 164}; 165 166&avb { 167 pinctrl-0 = <&avb0_pins>; 168 pinctrl-names = "default"; 169 renesas,no-ether-link; 170 phy-handle = <&phy0>; 171 status = "okay"; 172 173 phy0: ethernet-phy@0 { 174 rxc-skew-ps = <1500>; 175 reg = <0>; 176 interrupt-parent = <&gpio5>; 177 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 178 /* 179 * TX clock internal delay mode is required for reliable 180 * 1Gbps communication using the KSZ9031RNX phy present on 181 * the Draak board, however, TX clock internal delay mode 182 * isn't supported on r8a77995. Thus, limit speed to 183 * 100Mbps for reliable communication. 184 */ 185 max-speed = <100>; 186 }; 187}; 188 189&can0 { 190 pinctrl-0 = <&can0_pins>; 191 pinctrl-names = "default"; 192 status = "okay"; 193}; 194 195&can1 { 196 pinctrl-0 = <&can1_pins>; 197 pinctrl-names = "default"; 198 status = "okay"; 199}; 200 201&du { 202 pinctrl-0 = <&du_pins>; 203 pinctrl-names = "default"; 204 status = "okay"; 205 206 clocks = <&cpg CPG_MOD 724>, 207 <&cpg CPG_MOD 723>, 208 <&x12_clk>; 209 clock-names = "du.0", "du.1", "dclkin.0"; 210 211 ports { 212 port@0 { 213 endpoint { 214 remote-endpoint = <&adv7123_in>; 215 }; 216 }; 217 }; 218}; 219 220&ehci0 { 221 dr_mode = "host"; 222 status = "okay"; 223}; 224 225&extal_clk { 226 clock-frequency = <48000000>; 227}; 228 229&hsusb { 230 dr_mode = "host"; 231 status = "okay"; 232}; 233 234&i2c0 { 235 pinctrl-0 = <&i2c0_pins>; 236 pinctrl-names = "default"; 237 status = "okay"; 238 239 composite-in@20 { 240 compatible = "adi,adv7180cp"; 241 reg = <0x20>; 242 243 ports { 244 #address-cells = <1>; 245 #size-cells = <0>; 246 247 port@0 { 248 reg = <0>; 249 adv7180_in: endpoint { 250 remote-endpoint = <&composite_con_in>; 251 }; 252 }; 253 254 port@3 { 255 reg = <3>; 256 257 /* 258 * The VIN4 video input path is shared between 259 * CVBS and HDMI inputs through SW[49-53] 260 * switches. 261 * 262 * CVBS is the default selection, link it to 263 * VIN4 here. 264 */ 265 adv7180_out: endpoint { 266 remote-endpoint = <&vin4_in>; 267 }; 268 }; 269 }; 270 271 }; 272 273 hdmi-encoder@39 { 274 compatible = "adi,adv7511w"; 275 reg = <0x39>, <0x3f>, <0x38>, <0x3c>; 276 reg-names = "main", "edid", "packet", "cec"; 277 interrupt-parent = <&gpio1>; 278 interrupts = <28 IRQ_TYPE_LEVEL_LOW>; 279 280 /* Depends on LVDS */ 281 max-clock = <135000000>; 282 min-vrefresh = <50>; 283 284 adi,input-depth = <8>; 285 adi,input-colorspace = "rgb"; 286 adi,input-clock = "1x"; 287 adi,input-style = <1>; 288 adi,input-justification = "evenly"; 289 290 ports { 291 #address-cells = <1>; 292 #size-cells = <0>; 293 294 port@0 { 295 reg = <0>; 296 adv7511_in: endpoint { 297 remote-endpoint = <&thc63lvd1024_out>; 298 }; 299 }; 300 301 port@1 { 302 reg = <1>; 303 adv7511_out: endpoint { 304 remote-endpoint = <&hdmi_con_out>; 305 }; 306 }; 307 }; 308 }; 309 310 hdmi-decoder@4c { 311 compatible = "adi,adv7612"; 312 reg = <0x4c>; 313 default-input = <0>; 314 315 ports { 316 #address-cells = <1>; 317 #size-cells = <0>; 318 319 port@0 { 320 reg = <0>; 321 322 adv7612_in: endpoint { 323 remote-endpoint = <&hdmi_con_in>; 324 }; 325 }; 326 327 port@2 { 328 reg = <2>; 329 330 /* 331 * The VIN4 video input path is shared between 332 * CVBS and HDMI inputs through SW[49-53] 333 * switches. 334 * 335 * CVBS is the default selection, leave HDMI 336 * not connected here. 337 */ 338 adv7612_out: endpoint { 339 pclk-sample = <0>; 340 hsync-active = <0>; 341 vsync-active = <0>; 342 }; 343 }; 344 }; 345 }; 346 347 eeprom@50 { 348 compatible = "rohm,br24t01", "atmel,24c01"; 349 reg = <0x50>; 350 pagesize = <8>; 351 }; 352}; 353 354&i2c1 { 355 pinctrl-0 = <&i2c1_pins>; 356 pinctrl-names = "default"; 357 status = "okay"; 358}; 359 360&lvds0 { 361 status = "okay"; 362 363 clocks = <&cpg CPG_MOD 727>, 364 <&x12_clk>, 365 <&extal_clk>; 366 clock-names = "fck", "dclkin.0", "extal"; 367 368 ports { 369 port@1 { 370 lvds0_out: endpoint { 371 remote-endpoint = <&thc63lvd1024_in>; 372 }; 373 }; 374 }; 375}; 376 377&lvds1 { 378 /* 379 * Even though the LVDS1 output is not connected, the encoder must be 380 * enabled to supply a pixel clock to the DU for the DPAD output when 381 * LVDS0 is in use. 382 */ 383 status = "okay"; 384 385 clocks = <&cpg CPG_MOD 727>, 386 <&x12_clk>, 387 <&extal_clk>; 388 clock-names = "fck", "dclkin.0", "extal"; 389}; 390 391&ohci0 { 392 dr_mode = "host"; 393 status = "okay"; 394}; 395 396&pfc { 397 avb0_pins: avb { 398 mux { 399 groups = "avb0_link", "avb0_mdio", "avb0_mii"; 400 function = "avb0"; 401 }; 402 }; 403 404 can0_pins: can0 { 405 groups = "can0_data_a"; 406 function = "can0"; 407 }; 408 409 can1_pins: can1 { 410 groups = "can1_data_a"; 411 function = "can1"; 412 }; 413 414 du_pins: du { 415 groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; 416 function = "du"; 417 }; 418 419 i2c0_pins: i2c0 { 420 groups = "i2c0"; 421 function = "i2c0"; 422 }; 423 424 i2c1_pins: i2c1 { 425 groups = "i2c1"; 426 function = "i2c1"; 427 }; 428 429 pwm0_pins: pwm0 { 430 groups = "pwm0_c"; 431 function = "pwm0"; 432 }; 433 434 pwm1_pins: pwm1 { 435 groups = "pwm1_c"; 436 function = "pwm1"; 437 }; 438 439 scif2_pins: scif2 { 440 groups = "scif2_data"; 441 function = "scif2"; 442 }; 443 444 sdhi2_pins: sd2 { 445 groups = "mmc_data8", "mmc_ctrl"; 446 function = "mmc"; 447 power-source = <1800>; 448 }; 449 450 sdhi2_pins_uhs: sd2_uhs { 451 groups = "mmc_data8", "mmc_ctrl"; 452 function = "mmc"; 453 power-source = <1800>; 454 }; 455 456 usb0_pins: usb0 { 457 groups = "usb0"; 458 function = "usb0"; 459 }; 460 461 vin4_pins_cvbs: vin4 { 462 groups = "vin4_data8", "vin4_sync", "vin4_clk"; 463 function = "vin4"; 464 }; 465}; 466 467&pwm0 { 468 pinctrl-0 = <&pwm0_pins>; 469 pinctrl-names = "default"; 470 471 status = "okay"; 472}; 473 474&pwm1 { 475 pinctrl-0 = <&pwm1_pins>; 476 pinctrl-names = "default"; 477 478 status = "okay"; 479}; 480 481&rwdt { 482 timeout-sec = <60>; 483 status = "okay"; 484}; 485 486&scif2 { 487 pinctrl-0 = <&scif2_pins>; 488 pinctrl-names = "default"; 489 490 status = "okay"; 491}; 492 493&sdhi2 { 494 /* used for on-board eMMC */ 495 pinctrl-0 = <&sdhi2_pins>; 496 pinctrl-1 = <&sdhi2_pins_uhs>; 497 pinctrl-names = "default", "state_uhs"; 498 499 vmmc-supply = <®_3p3v>; 500 vqmmc-supply = <®_1p8v>; 501 bus-width = <8>; 502 mmc-hs200-1_8v; 503 non-removable; 504 status = "okay"; 505}; 506 507&usb2_phy0 { 508 pinctrl-0 = <&usb0_pins>; 509 pinctrl-names = "default"; 510 511 renesas,no-otg-pins; 512 status = "okay"; 513}; 514 515&vin4 { 516 pinctrl-0 = <&vin4_pins_cvbs>; 517 pinctrl-names = "default"; 518 519 status = "okay"; 520 521 ports { 522 port { 523 vin4_in: endpoint { 524 remote-endpoint = <&adv7180_out>; 525 }; 526 }; 527 }; 528}; 529