1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Device Tree Source for the R-Car E3 (R8A77990) SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a77990-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a77990-sysc.h> 11 12/ { 13 compatible = "renesas,r8a77990"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 aliases { 18 i2c0 = &i2c0; 19 i2c1 = &i2c1; 20 i2c2 = &i2c2; 21 i2c3 = &i2c3; 22 i2c4 = &i2c4; 23 i2c5 = &i2c5; 24 i2c6 = &i2c6; 25 i2c7 = &i2c7; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 a53_0: cpu@0 { 33 compatible = "arm,cortex-a53", "arm,armv8"; 34 reg = <0>; 35 device_type = "cpu"; 36 power-domains = <&sysc R8A77990_PD_CA53_CPU0>; 37 next-level-cache = <&L2_CA53>; 38 enable-method = "psci"; 39 }; 40 41 a53_1: cpu@1 { 42 compatible = "arm,cortex-a53", "arm,armv8"; 43 reg = <1>; 44 device_type = "cpu"; 45 power-domains = <&sysc R8A77990_PD_CA53_CPU1>; 46 next-level-cache = <&L2_CA53>; 47 enable-method = "psci"; 48 }; 49 50 L2_CA53: cache-controller-0 { 51 compatible = "cache"; 52 power-domains = <&sysc R8A77990_PD_CA53_SCU>; 53 cache-unified; 54 cache-level = <2>; 55 }; 56 }; 57 58 extal_clk: extal { 59 compatible = "fixed-clock"; 60 #clock-cells = <0>; 61 /* This value must be overridden by the board */ 62 clock-frequency = <0>; 63 }; 64 65 pmu_a53 { 66 compatible = "arm,cortex-a53-pmu"; 67 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 68 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-affinity = <&a53_0>, <&a53_1>; 70 }; 71 72 psci { 73 compatible = "arm,psci-1.0", "arm,psci-0.2"; 74 method = "smc"; 75 }; 76 77 /* External SCIF clock - to be overridden by boards that provide it */ 78 scif_clk: scif { 79 compatible = "fixed-clock"; 80 #clock-cells = <0>; 81 clock-frequency = <0>; 82 }; 83 84 soc: soc { 85 compatible = "simple-bus"; 86 interrupt-parent = <&gic>; 87 #address-cells = <2>; 88 #size-cells = <2>; 89 ranges; 90 91 rwdt: watchdog@e6020000 { 92 compatible = "renesas,r8a77990-wdt", 93 "renesas,rcar-gen3-wdt"; 94 reg = <0 0xe6020000 0 0x0c>; 95 clocks = <&cpg CPG_MOD 402>; 96 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 97 resets = <&cpg 402>; 98 status = "disabled"; 99 }; 100 101 gpio0: gpio@e6050000 { 102 compatible = "renesas,gpio-r8a77990", 103 "renesas,rcar-gen3-gpio"; 104 reg = <0 0xe6050000 0 0x50>; 105 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 106 #gpio-cells = <2>; 107 gpio-controller; 108 gpio-ranges = <&pfc 0 0 18>; 109 #interrupt-cells = <2>; 110 interrupt-controller; 111 clocks = <&cpg CPG_MOD 912>; 112 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 113 resets = <&cpg 912>; 114 }; 115 116 gpio1: gpio@e6051000 { 117 compatible = "renesas,gpio-r8a77990", 118 "renesas,rcar-gen3-gpio"; 119 reg = <0 0xe6051000 0 0x50>; 120 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 121 #gpio-cells = <2>; 122 gpio-controller; 123 gpio-ranges = <&pfc 0 32 23>; 124 #interrupt-cells = <2>; 125 interrupt-controller; 126 clocks = <&cpg CPG_MOD 911>; 127 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 128 resets = <&cpg 911>; 129 }; 130 131 gpio2: gpio@e6052000 { 132 compatible = "renesas,gpio-r8a77990", 133 "renesas,rcar-gen3-gpio"; 134 reg = <0 0xe6052000 0 0x50>; 135 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 136 #gpio-cells = <2>; 137 gpio-controller; 138 gpio-ranges = <&pfc 0 64 26>; 139 #interrupt-cells = <2>; 140 interrupt-controller; 141 clocks = <&cpg CPG_MOD 910>; 142 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 143 resets = <&cpg 910>; 144 }; 145 146 gpio3: gpio@e6053000 { 147 compatible = "renesas,gpio-r8a77990", 148 "renesas,rcar-gen3-gpio"; 149 reg = <0 0xe6053000 0 0x50>; 150 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 151 #gpio-cells = <2>; 152 gpio-controller; 153 gpio-ranges = <&pfc 0 96 16>; 154 #interrupt-cells = <2>; 155 interrupt-controller; 156 clocks = <&cpg CPG_MOD 909>; 157 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 158 resets = <&cpg 909>; 159 }; 160 161 gpio4: gpio@e6054000 { 162 compatible = "renesas,gpio-r8a77990", 163 "renesas,rcar-gen3-gpio"; 164 reg = <0 0xe6054000 0 0x50>; 165 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 166 #gpio-cells = <2>; 167 gpio-controller; 168 gpio-ranges = <&pfc 0 128 11>; 169 #interrupt-cells = <2>; 170 interrupt-controller; 171 clocks = <&cpg CPG_MOD 908>; 172 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 173 resets = <&cpg 908>; 174 }; 175 176 gpio5: gpio@e6055000 { 177 compatible = "renesas,gpio-r8a77990", 178 "renesas,rcar-gen3-gpio"; 179 reg = <0 0xe6055000 0 0x50>; 180 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 181 #gpio-cells = <2>; 182 gpio-controller; 183 gpio-ranges = <&pfc 0 160 20>; 184 #interrupt-cells = <2>; 185 interrupt-controller; 186 clocks = <&cpg CPG_MOD 907>; 187 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 188 resets = <&cpg 907>; 189 }; 190 191 gpio6: gpio@e6055400 { 192 compatible = "renesas,gpio-r8a77990", 193 "renesas,rcar-gen3-gpio"; 194 reg = <0 0xe6055400 0 0x50>; 195 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 196 #gpio-cells = <2>; 197 gpio-controller; 198 gpio-ranges = <&pfc 0 192 18>; 199 #interrupt-cells = <2>; 200 interrupt-controller; 201 clocks = <&cpg CPG_MOD 906>; 202 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 203 resets = <&cpg 906>; 204 }; 205 206 i2c0: i2c@e6500000 { 207 #address-cells = <1>; 208 #size-cells = <0>; 209 compatible = "renesas,i2c-r8a77990", 210 "renesas,rcar-gen3-i2c"; 211 reg = <0 0xe6500000 0 0x40>; 212 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 213 clocks = <&cpg CPG_MOD 931>; 214 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 215 resets = <&cpg 931>; 216 i2c-scl-internal-delay-ns = <110>; 217 status = "disabled"; 218 }; 219 220 i2c1: i2c@e6508000 { 221 #address-cells = <1>; 222 #size-cells = <0>; 223 compatible = "renesas,i2c-r8a77990", 224 "renesas,rcar-gen3-i2c"; 225 reg = <0 0xe6508000 0 0x40>; 226 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&cpg CPG_MOD 930>; 228 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 229 resets = <&cpg 930>; 230 i2c-scl-internal-delay-ns = <6>; 231 status = "disabled"; 232 }; 233 234 i2c2: i2c@e6510000 { 235 #address-cells = <1>; 236 #size-cells = <0>; 237 compatible = "renesas,i2c-r8a77990", 238 "renesas,rcar-gen3-i2c"; 239 reg = <0 0xe6510000 0 0x40>; 240 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 241 clocks = <&cpg CPG_MOD 929>; 242 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 243 resets = <&cpg 929>; 244 i2c-scl-internal-delay-ns = <6>; 245 status = "disabled"; 246 }; 247 248 i2c3: i2c@e66d0000 { 249 #address-cells = <1>; 250 #size-cells = <0>; 251 compatible = "renesas,i2c-r8a77990", 252 "renesas,rcar-gen3-i2c"; 253 reg = <0 0xe66d0000 0 0x40>; 254 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 255 clocks = <&cpg CPG_MOD 928>; 256 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 257 resets = <&cpg 928>; 258 i2c-scl-internal-delay-ns = <110>; 259 status = "disabled"; 260 }; 261 262 i2c4: i2c@e66d8000 { 263 #address-cells = <1>; 264 #size-cells = <0>; 265 compatible = "renesas,i2c-r8a77990", 266 "renesas,rcar-gen3-i2c"; 267 reg = <0 0xe66d8000 0 0x40>; 268 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 269 clocks = <&cpg CPG_MOD 927>; 270 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 271 resets = <&cpg 927>; 272 i2c-scl-internal-delay-ns = <6>; 273 status = "disabled"; 274 }; 275 276 i2c5: i2c@e66e0000 { 277 #address-cells = <1>; 278 #size-cells = <0>; 279 compatible = "renesas,i2c-r8a77990", 280 "renesas,rcar-gen3-i2c"; 281 reg = <0 0xe66e0000 0 0x40>; 282 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&cpg CPG_MOD 919>; 284 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 285 resets = <&cpg 919>; 286 i2c-scl-internal-delay-ns = <6>; 287 status = "disabled"; 288 }; 289 290 i2c6: i2c@e66e8000 { 291 #address-cells = <1>; 292 #size-cells = <0>; 293 compatible = "renesas,i2c-r8a77990", 294 "renesas,rcar-gen3-i2c"; 295 reg = <0 0xe66e8000 0 0x40>; 296 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&cpg CPG_MOD 918>; 298 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 299 resets = <&cpg 918>; 300 i2c-scl-internal-delay-ns = <6>; 301 status = "disabled"; 302 }; 303 304 i2c7: i2c@e6690000 { 305 #address-cells = <1>; 306 #size-cells = <0>; 307 compatible = "renesas,i2c-r8a77990", 308 "renesas,rcar-gen3-i2c"; 309 reg = <0 0xe6690000 0 0x40>; 310 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&cpg CPG_MOD 1003>; 312 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 313 resets = <&cpg 1003>; 314 i2c-scl-internal-delay-ns = <6>; 315 status = "disabled"; 316 }; 317 318 pfc: pin-controller@e6060000 { 319 compatible = "renesas,pfc-r8a77990"; 320 reg = <0 0xe6060000 0 0x508>; 321 }; 322 323 cpg: clock-controller@e6150000 { 324 compatible = "renesas,r8a77990-cpg-mssr"; 325 reg = <0 0xe6150000 0 0x1000>; 326 clocks = <&extal_clk>; 327 clock-names = "extal"; 328 #clock-cells = <2>; 329 #power-domain-cells = <0>; 330 #reset-cells = <1>; 331 }; 332 333 rst: reset-controller@e6160000 { 334 compatible = "renesas,r8a77990-rst"; 335 reg = <0 0xe6160000 0 0x0200>; 336 }; 337 338 sysc: system-controller@e6180000 { 339 compatible = "renesas,r8a77990-sysc"; 340 reg = <0 0xe6180000 0 0x0400>; 341 #power-domain-cells = <1>; 342 }; 343 344 intc_ex: interrupt-controller@e61c0000 { 345 compatible = "renesas,intc-ex-r8a77990", "renesas,irqc"; 346 #interrupt-cells = <2>; 347 interrupt-controller; 348 reg = <0 0xe61c0000 0 0x200>; 349 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 350 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 351 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 352 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 353 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 354 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&cpg CPG_MOD 407>; 356 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 357 resets = <&cpg 407>; 358 }; 359 360 dmac0: dma-controller@e6700000 { 361 compatible = "renesas,dmac-r8a77990", 362 "renesas,rcar-dmac"; 363 reg = <0 0xe6700000 0 0x10000>; 364 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 365 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 366 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 367 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 368 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 369 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 370 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 371 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 372 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 373 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 374 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 375 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 376 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 377 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 378 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 379 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 380 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 381 interrupt-names = "error", 382 "ch0", "ch1", "ch2", "ch3", 383 "ch4", "ch5", "ch6", "ch7", 384 "ch8", "ch9", "ch10", "ch11", 385 "ch12", "ch13", "ch14", "ch15"; 386 clocks = <&cpg CPG_MOD 219>; 387 clock-names = "fck"; 388 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 389 resets = <&cpg 219>; 390 #dma-cells = <1>; 391 dma-channels = <16>; 392 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 393 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 394 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 395 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 396 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 397 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 398 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 399 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 400 }; 401 402 dmac1: dma-controller@e7300000 { 403 compatible = "renesas,dmac-r8a77990", 404 "renesas,rcar-dmac"; 405 reg = <0 0xe7300000 0 0x10000>; 406 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 407 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 408 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 409 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 410 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 411 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 412 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 413 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 414 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 415 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 416 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 417 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 418 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 419 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 420 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 421 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 422 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 423 interrupt-names = "error", 424 "ch0", "ch1", "ch2", "ch3", 425 "ch4", "ch5", "ch6", "ch7", 426 "ch8", "ch9", "ch10", "ch11", 427 "ch12", "ch13", "ch14", "ch15"; 428 clocks = <&cpg CPG_MOD 218>; 429 clock-names = "fck"; 430 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 431 resets = <&cpg 218>; 432 #dma-cells = <1>; 433 dma-channels = <16>; 434 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 435 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 436 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 437 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 438 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 439 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 440 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 441 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 442 }; 443 444 dmac2: dma-controller@e7310000 { 445 compatible = "renesas,dmac-r8a77990", 446 "renesas,rcar-dmac"; 447 reg = <0 0xe7310000 0 0x10000>; 448 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 449 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 450 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 451 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 452 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 453 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 454 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 455 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 456 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 457 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 458 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 459 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 460 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 461 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 462 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 463 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 464 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 465 interrupt-names = "error", 466 "ch0", "ch1", "ch2", "ch3", 467 "ch4", "ch5", "ch6", "ch7", 468 "ch8", "ch9", "ch10", "ch11", 469 "ch12", "ch13", "ch14", "ch15"; 470 clocks = <&cpg CPG_MOD 217>; 471 clock-names = "fck"; 472 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 473 resets = <&cpg 217>; 474 #dma-cells = <1>; 475 dma-channels = <16>; 476 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 477 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 478 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 479 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 480 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 481 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 482 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 483 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 484 }; 485 486 ipmmu_ds0: mmu@e6740000 { 487 compatible = "renesas,ipmmu-r8a77990"; 488 reg = <0 0xe6740000 0 0x1000>; 489 renesas,ipmmu-main = <&ipmmu_mm 0>; 490 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 491 #iommu-cells = <1>; 492 }; 493 494 ipmmu_ds1: mmu@e7740000 { 495 compatible = "renesas,ipmmu-r8a77990"; 496 reg = <0 0xe7740000 0 0x1000>; 497 renesas,ipmmu-main = <&ipmmu_mm 1>; 498 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 499 #iommu-cells = <1>; 500 }; 501 502 ipmmu_hc: mmu@e6570000 { 503 compatible = "renesas,ipmmu-r8a77990"; 504 reg = <0 0xe6570000 0 0x1000>; 505 renesas,ipmmu-main = <&ipmmu_mm 2>; 506 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 507 #iommu-cells = <1>; 508 }; 509 510 ipmmu_mm: mmu@e67b0000 { 511 compatible = "renesas,ipmmu-r8a77990"; 512 reg = <0 0xe67b0000 0 0x1000>; 513 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 515 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 516 #iommu-cells = <1>; 517 }; 518 519 ipmmu_mp: mmu@ec670000 { 520 compatible = "renesas,ipmmu-r8a77990"; 521 reg = <0 0xec670000 0 0x1000>; 522 renesas,ipmmu-main = <&ipmmu_mm 4>; 523 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 524 #iommu-cells = <1>; 525 }; 526 527 ipmmu_pv0: mmu@fd800000 { 528 compatible = "renesas,ipmmu-r8a77990"; 529 reg = <0 0xfd800000 0 0x1000>; 530 renesas,ipmmu-main = <&ipmmu_mm 6>; 531 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 532 #iommu-cells = <1>; 533 }; 534 535 ipmmu_rt: mmu@ffc80000 { 536 compatible = "renesas,ipmmu-r8a77990"; 537 reg = <0 0xffc80000 0 0x1000>; 538 renesas,ipmmu-main = <&ipmmu_mm 10>; 539 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 540 #iommu-cells = <1>; 541 }; 542 543 ipmmu_vc0: mmu@fe6b0000 { 544 compatible = "renesas,ipmmu-r8a77990"; 545 reg = <0 0xfe6b0000 0 0x1000>; 546 renesas,ipmmu-main = <&ipmmu_mm 12>; 547 power-domains = <&sysc R8A77990_PD_A3VC>; 548 #iommu-cells = <1>; 549 }; 550 551 ipmmu_vi0: mmu@febd0000 { 552 compatible = "renesas,ipmmu-r8a77990"; 553 reg = <0 0xfebd0000 0 0x1000>; 554 renesas,ipmmu-main = <&ipmmu_mm 14>; 555 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 556 #iommu-cells = <1>; 557 }; 558 559 ipmmu_vp0: mmu@fe990000 { 560 compatible = "renesas,ipmmu-r8a77990"; 561 reg = <0 0xfe990000 0 0x1000>; 562 renesas,ipmmu-main = <&ipmmu_mm 16>; 563 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 564 #iommu-cells = <1>; 565 }; 566 567 avb: ethernet@e6800000 { 568 compatible = "renesas,etheravb-r8a77990", 569 "renesas,etheravb-rcar-gen3"; 570 reg = <0 0xe6800000 0 0x800>; 571 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 596 interrupt-names = "ch0", "ch1", "ch2", "ch3", 597 "ch4", "ch5", "ch6", "ch7", 598 "ch8", "ch9", "ch10", "ch11", 599 "ch12", "ch13", "ch14", "ch15", 600 "ch16", "ch17", "ch18", "ch19", 601 "ch20", "ch21", "ch22", "ch23", 602 "ch24"; 603 clocks = <&cpg CPG_MOD 812>; 604 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 605 resets = <&cpg 812>; 606 phy-mode = "rgmii"; 607 iommus = <&ipmmu_ds0 16>; 608 #address-cells = <1>; 609 #size-cells = <0>; 610 status = "disabled"; 611 }; 612 613 pwm0: pwm@e6e30000 { 614 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 615 reg = <0 0xe6e30000 0 0x8>; 616 clocks = <&cpg CPG_MOD 523>; 617 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 618 resets = <&cpg 523>; 619 #pwm-cells = <2>; 620 status = "disabled"; 621 }; 622 623 pwm1: pwm@e6e31000 { 624 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 625 reg = <0 0xe6e31000 0 0x8>; 626 clocks = <&cpg CPG_MOD 523>; 627 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 628 resets = <&cpg 523>; 629 #pwm-cells = <2>; 630 status = "disabled"; 631 }; 632 633 pwm2: pwm@e6e32000 { 634 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 635 reg = <0 0xe6e32000 0 0x8>; 636 clocks = <&cpg CPG_MOD 523>; 637 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 638 resets = <&cpg 523>; 639 #pwm-cells = <2>; 640 status = "disabled"; 641 }; 642 643 pwm3: pwm@e6e33000 { 644 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 645 reg = <0 0xe6e33000 0 0x8>; 646 clocks = <&cpg CPG_MOD 523>; 647 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 648 resets = <&cpg 523>; 649 #pwm-cells = <2>; 650 status = "disabled"; 651 }; 652 653 pwm4: pwm@e6e34000 { 654 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 655 reg = <0 0xe6e34000 0 0x8>; 656 clocks = <&cpg CPG_MOD 523>; 657 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 658 resets = <&cpg 523>; 659 #pwm-cells = <2>; 660 status = "disabled"; 661 }; 662 663 pwm5: pwm@e6e35000 { 664 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 665 reg = <0 0xe6e35000 0 0x8>; 666 clocks = <&cpg CPG_MOD 523>; 667 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 668 resets = <&cpg 523>; 669 #pwm-cells = <2>; 670 status = "disabled"; 671 }; 672 673 pwm6: pwm@e6e36000 { 674 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 675 reg = <0 0xe6e36000 0 0x8>; 676 clocks = <&cpg CPG_MOD 523>; 677 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 678 resets = <&cpg 523>; 679 #pwm-cells = <2>; 680 status = "disabled"; 681 }; 682 683 scif0: serial@e6e60000 { 684 compatible = "renesas,scif-r8a77990", 685 "renesas,rcar-gen3-scif", "renesas,scif"; 686 reg = <0 0xe6e60000 0 64>; 687 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&cpg CPG_MOD 207>, 689 <&cpg CPG_CORE R8A77990_CLK_S3D1C>, 690 <&scif_clk>; 691 clock-names = "fck", "brg_int", "scif_clk"; 692 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 693 <&dmac2 0x51>, <&dmac2 0x50>; 694 dma-names = "tx", "rx", "tx", "rx"; 695 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 696 resets = <&cpg 207>; 697 status = "disabled"; 698 }; 699 700 scif1: serial@e6e68000 { 701 compatible = "renesas,scif-r8a77990", 702 "renesas,rcar-gen3-scif", "renesas,scif"; 703 reg = <0 0xe6e68000 0 64>; 704 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 705 clocks = <&cpg CPG_MOD 206>, 706 <&cpg CPG_CORE R8A77990_CLK_S3D1C>, 707 <&scif_clk>; 708 clock-names = "fck", "brg_int", "scif_clk"; 709 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 710 <&dmac2 0x53>, <&dmac2 0x52>; 711 dma-names = "tx", "rx", "tx", "rx"; 712 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 713 resets = <&cpg 206>; 714 status = "disabled"; 715 }; 716 717 scif2: serial@e6e88000 { 718 compatible = "renesas,scif-r8a77990", 719 "renesas,rcar-gen3-scif", "renesas,scif"; 720 reg = <0 0xe6e88000 0 64>; 721 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&cpg CPG_MOD 310>, 723 <&cpg CPG_CORE R8A77990_CLK_S3D1C>, 724 <&scif_clk>; 725 clock-names = "fck", "brg_int", "scif_clk"; 726 727 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 728 resets = <&cpg 310>; 729 status = "disabled"; 730 }; 731 732 scif3: serial@e6c50000 { 733 compatible = "renesas,scif-r8a77990", 734 "renesas,rcar-gen3-scif", "renesas,scif"; 735 reg = <0 0xe6c50000 0 64>; 736 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&cpg CPG_MOD 204>, 738 <&cpg CPG_CORE R8A77990_CLK_S3D1C>, 739 <&scif_clk>; 740 clock-names = "fck", "brg_int", "scif_clk"; 741 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 742 dma-names = "tx", "rx"; 743 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 744 resets = <&cpg 204>; 745 status = "disabled"; 746 }; 747 748 scif4: serial@e6c40000 { 749 compatible = "renesas,scif-r8a77990", 750 "renesas,rcar-gen3-scif", "renesas,scif"; 751 reg = <0 0xe6c40000 0 64>; 752 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&cpg CPG_MOD 203>, 754 <&cpg CPG_CORE R8A77990_CLK_S3D1C>, 755 <&scif_clk>; 756 clock-names = "fck", "brg_int", "scif_clk"; 757 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 758 dma-names = "tx", "rx"; 759 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 760 resets = <&cpg 203>; 761 status = "disabled"; 762 }; 763 764 scif5: serial@e6f30000 { 765 compatible = "renesas,scif-r8a77990", 766 "renesas,rcar-gen3-scif", "renesas,scif"; 767 reg = <0 0xe6f30000 0 64>; 768 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 769 clocks = <&cpg CPG_MOD 202>, 770 <&cpg CPG_CORE R8A77990_CLK_S3D1C>, 771 <&scif_clk>; 772 clock-names = "fck", "brg_int", "scif_clk"; 773 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 774 <&dmac2 0x5b>, <&dmac2 0x5a>; 775 dma-names = "tx", "rx", "tx", "rx"; 776 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 777 resets = <&cpg 202>; 778 status = "disabled"; 779 }; 780 781 msiof0: spi@e6e90000 { 782 compatible = "renesas,msiof-r8a77990", 783 "renesas,rcar-gen3-msiof"; 784 reg = <0 0xe6e90000 0 0x0064>; 785 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 786 clocks = <&cpg CPG_MOD 211>; 787 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 788 <&dmac2 0x41>, <&dmac2 0x40>; 789 dma-names = "tx", "rx", "tx", "rx"; 790 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 791 resets = <&cpg 211>; 792 #address-cells = <1>; 793 #size-cells = <0>; 794 status = "disabled"; 795 }; 796 797 msiof1: spi@e6ea0000 { 798 compatible = "renesas,msiof-r8a77990", 799 "renesas,rcar-gen3-msiof"; 800 reg = <0 0xe6ea0000 0 0x0064>; 801 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 802 clocks = <&cpg CPG_MOD 210>; 803 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 804 <&dmac2 0x43>, <&dmac2 0x42>; 805 dma-names = "tx", "rx", "tx", "rx"; 806 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 807 resets = <&cpg 210>; 808 #address-cells = <1>; 809 #size-cells = <0>; 810 status = "disabled"; 811 }; 812 813 msiof2: spi@e6c00000 { 814 compatible = "renesas,msiof-r8a77990", 815 "renesas,rcar-gen3-msiof"; 816 reg = <0 0xe6c00000 0 0x0064>; 817 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 818 clocks = <&cpg CPG_MOD 209>; 819 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 820 dma-names = "tx", "rx"; 821 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 822 resets = <&cpg 209>; 823 #address-cells = <1>; 824 #size-cells = <0>; 825 status = "disabled"; 826 }; 827 828 msiof3: spi@e6c10000 { 829 compatible = "renesas,msiof-r8a77990", 830 "renesas,rcar-gen3-msiof"; 831 reg = <0 0xe6c10000 0 0x0064>; 832 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 833 clocks = <&cpg CPG_MOD 208>; 834 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 835 dma-names = "tx", "rx"; 836 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 837 resets = <&cpg 208>; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 status = "disabled"; 841 }; 842 843 vin4: video@e6ef4000 { 844 compatible = "renesas,vin-r8a77990"; 845 reg = <0 0xe6ef4000 0 0x1000>; 846 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 847 clocks = <&cpg CPG_MOD 807>; 848 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 849 resets = <&cpg 807>; 850 renesas,id = <4>; 851 status = "disabled"; 852 853 ports { 854 #address-cells = <1>; 855 #size-cells = <0>; 856 857 port@1 { 858 reg = <1>; 859 860 vin4csi40: endpoint { 861 remote-endpoint= <&csi40vin4>; 862 }; 863 }; 864 }; 865 }; 866 867 vin5: video@e6ef5000 { 868 compatible = "renesas,vin-r8a77990"; 869 reg = <0 0xe6ef5000 0 0x1000>; 870 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&cpg CPG_MOD 806>; 872 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 873 resets = <&cpg 806>; 874 renesas,id = <5>; 875 status = "disabled"; 876 877 ports { 878 #address-cells = <1>; 879 #size-cells = <0>; 880 881 port@1 { 882 reg = <1>; 883 884 vin5csi40: endpoint { 885 remote-endpoint= <&csi40vin5>; 886 }; 887 }; 888 }; 889 }; 890 891 xhci0: usb@ee000000 { 892 compatible = "renesas,xhci-r8a77990", 893 "renesas,rcar-gen3-xhci"; 894 reg = <0 0xee000000 0 0xc00>; 895 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 896 clocks = <&cpg CPG_MOD 328>; 897 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 898 resets = <&cpg 328>; 899 status = "disabled"; 900 }; 901 902 usb3_peri0: usb@ee020000 { 903 compatible = "renesas,r8a77990-usb3-peri", 904 "renesas,rcar-gen3-usb3-peri"; 905 reg = <0 0xee020000 0 0x400>; 906 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 907 clocks = <&cpg CPG_MOD 328>; 908 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 909 resets = <&cpg 328>; 910 status = "disabled"; 911 }; 912 913 ohci0: usb@ee080000 { 914 compatible = "generic-ohci"; 915 reg = <0 0xee080000 0 0x100>; 916 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 917 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 918 phys = <&usb2_phy0>; 919 phy-names = "usb"; 920 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 921 resets = <&cpg 703>, <&cpg 704>; 922 status = "disabled"; 923 }; 924 925 ehci0: usb@ee080100 { 926 compatible = "generic-ehci"; 927 reg = <0 0xee080100 0 0x100>; 928 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 929 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 930 phys = <&usb2_phy0>; 931 phy-names = "usb"; 932 companion = <&ohci0>; 933 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 934 resets = <&cpg 703>, <&cpg 704>; 935 status = "disabled"; 936 }; 937 938 usb2_phy0: usb-phy@ee080200 { 939 compatible = "renesas,usb2-phy-r8a77990", 940 "renesas,rcar-gen3-usb2-phy"; 941 reg = <0 0xee080200 0 0x700>; 942 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 943 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 944 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 945 resets = <&cpg 703>, <&cpg 704>; 946 #phy-cells = <0>; 947 status = "disabled"; 948 }; 949 950 gic: interrupt-controller@f1010000 { 951 compatible = "arm,gic-400"; 952 #interrupt-cells = <3>; 953 #address-cells = <0>; 954 interrupt-controller; 955 reg = <0x0 0xf1010000 0 0x1000>, 956 <0x0 0xf1020000 0 0x20000>, 957 <0x0 0xf1040000 0 0x20000>, 958 <0x0 0xf1060000 0 0x20000>; 959 interrupts = <GIC_PPI 9 960 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 961 clocks = <&cpg CPG_MOD 408>; 962 clock-names = "clk"; 963 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 964 resets = <&cpg 408>; 965 }; 966 967 vspb0: vsp@fe960000 { 968 compatible = "renesas,vsp2"; 969 reg = <0 0xfe960000 0 0x8000>; 970 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 971 clocks = <&cpg CPG_MOD 626>; 972 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 973 resets = <&cpg 626>; 974 renesas,fcp = <&fcpvb0>; 975 }; 976 977 fcpvb0: fcp@fe96f000 { 978 compatible = "renesas,fcpv"; 979 reg = <0 0xfe96f000 0 0x200>; 980 clocks = <&cpg CPG_MOD 607>; 981 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 982 resets = <&cpg 607>; 983 iommus = <&ipmmu_vp0 5>; 984 }; 985 986 vspi0: vsp@fe9a0000 { 987 compatible = "renesas,vsp2"; 988 reg = <0 0xfe9a0000 0 0x8000>; 989 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 990 clocks = <&cpg CPG_MOD 631>; 991 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 992 resets = <&cpg 631>; 993 renesas,fcp = <&fcpvi0>; 994 }; 995 996 fcpvi0: fcp@fe9af000 { 997 compatible = "renesas,fcpv"; 998 reg = <0 0xfe9af000 0 0x200>; 999 clocks = <&cpg CPG_MOD 611>; 1000 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1001 resets = <&cpg 611>; 1002 iommus = <&ipmmu_vp0 8>; 1003 }; 1004 1005 vspd0: vsp@fea20000 { 1006 compatible = "renesas,vsp2"; 1007 reg = <0 0xfea20000 0 0x7000>; 1008 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1009 clocks = <&cpg CPG_MOD 623>; 1010 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1011 resets = <&cpg 623>; 1012 renesas,fcp = <&fcpvd0>; 1013 }; 1014 1015 fcpvd0: fcp@fea27000 { 1016 compatible = "renesas,fcpv"; 1017 reg = <0 0xfea27000 0 0x200>; 1018 clocks = <&cpg CPG_MOD 603>; 1019 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1020 resets = <&cpg 603>; 1021 iommus = <&ipmmu_vi0 8>; 1022 }; 1023 1024 vspd1: vsp@fea28000 { 1025 compatible = "renesas,vsp2"; 1026 reg = <0 0xfea28000 0 0x7000>; 1027 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1028 clocks = <&cpg CPG_MOD 622>; 1029 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1030 resets = <&cpg 622>; 1031 renesas,fcp = <&fcpvd1>; 1032 }; 1033 1034 fcpvd1: fcp@fea2f000 { 1035 compatible = "renesas,fcpv"; 1036 reg = <0 0xfea2f000 0 0x200>; 1037 clocks = <&cpg CPG_MOD 602>; 1038 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1039 resets = <&cpg 602>; 1040 iommus = <&ipmmu_vi0 9>; 1041 }; 1042 1043 csi40: csi2@feaa0000 { 1044 compatible = "renesas,r8a77990-csi2", "renesas,rcar-gen3-csi2"; 1045 reg = <0 0xfeaa0000 0 0x10000>; 1046 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1047 clocks = <&cpg CPG_MOD 716>; 1048 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1049 resets = <&cpg 716>; 1050 status = "disabled"; 1051 1052 ports { 1053 #address-cells = <1>; 1054 #size-cells = <0>; 1055 1056 port@1 { 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 1060 reg = <1>; 1061 1062 csi40vin4: endpoint@0 { 1063 reg = <0>; 1064 remote-endpoint = <&vin4csi40>; 1065 }; 1066 csi40vin5: endpoint@1 { 1067 reg = <1>; 1068 remote-endpoint = <&vin5csi40>; 1069 }; 1070 }; 1071 }; 1072 }; 1073 1074 du: display@feb00000 { 1075 compatible = "renesas,du-r8a77990"; 1076 reg = <0 0xfeb00000 0 0x80000>; 1077 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1079 clocks = <&cpg CPG_MOD 724>, 1080 <&cpg CPG_MOD 723>; 1081 clock-names = "du.0", "du.1"; 1082 vsps = <&vspd0 0 &vspd1 0>; 1083 status = "disabled"; 1084 1085 ports { 1086 #address-cells = <1>; 1087 #size-cells = <0>; 1088 1089 port@0 { 1090 reg = <0>; 1091 du_out_rgb: endpoint { 1092 }; 1093 }; 1094 1095 port@1 { 1096 reg = <1>; 1097 du_out_lvds0: endpoint { 1098 remote-endpoint = <&lvds0_in>; 1099 }; 1100 }; 1101 1102 port@2 { 1103 reg = <2>; 1104 du_out_lvds1: endpoint { 1105 remote-endpoint = <&lvds1_in>; 1106 }; 1107 }; 1108 }; 1109 }; 1110 1111 lvds0: lvds-encoder@feb90000 { 1112 compatible = "renesas,r8a77990-lvds"; 1113 reg = <0 0xfeb90000 0 0x20>; 1114 clocks = <&cpg CPG_MOD 727>; 1115 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1116 resets = <&cpg 727>; 1117 status = "disabled"; 1118 1119 ports { 1120 #address-cells = <1>; 1121 #size-cells = <0>; 1122 1123 port@0 { 1124 reg = <0>; 1125 lvds0_in: endpoint { 1126 remote-endpoint = <&du_out_lvds0>; 1127 }; 1128 }; 1129 1130 port@1 { 1131 reg = <1>; 1132 lvds0_out: endpoint { 1133 }; 1134 }; 1135 }; 1136 }; 1137 1138 lvds1: lvds-encoder@feb90100 { 1139 compatible = "renesas,r8a77990-lvds"; 1140 reg = <0 0xfeb90100 0 0x20>; 1141 clocks = <&cpg CPG_MOD 727>; 1142 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1143 resets = <&cpg 726>; 1144 status = "disabled"; 1145 1146 ports { 1147 #address-cells = <1>; 1148 #size-cells = <0>; 1149 1150 port@0 { 1151 reg = <0>; 1152 lvds1_in: endpoint { 1153 remote-endpoint = <&du_out_lvds1>; 1154 }; 1155 }; 1156 1157 port@1 { 1158 reg = <1>; 1159 lvds1_out: endpoint { 1160 }; 1161 }; 1162 }; 1163 }; 1164 1165 prr: chipid@fff00044 { 1166 compatible = "renesas,prr"; 1167 reg = <0 0xfff00044 0 4>; 1168 }; 1169 }; 1170 1171 timer { 1172 compatible = "arm,armv8-timer"; 1173 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1174 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1175 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1176 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 1177 }; 1178}; 1179