1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Device Tree Source for the r8a77990 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "renesas,r8a77990"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 a53_0: cpu@0 { 21 compatible = "arm,cortex-a53", "arm,armv8"; 22 reg = <0>; 23 device_type = "cpu"; 24 power-domains = <&sysc 5>; 25 next-level-cache = <&L2_CA53>; 26 enable-method = "psci"; 27 }; 28 29 a53_1: cpu@1 { 30 compatible = "arm,cortex-a53", "arm,armv8"; 31 reg = <1>; 32 device_type = "cpu"; 33 power-domains = <&sysc 6>; 34 next-level-cache = <&L2_CA53>; 35 enable-method = "psci"; 36 }; 37 38 L2_CA53: cache-controller-0 { 39 compatible = "cache"; 40 power-domains = <&sysc 21>; 41 cache-unified; 42 cache-level = <2>; 43 }; 44 }; 45 46 extal_clk: extal { 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 /* This value must be overridden by the board */ 50 clock-frequency = <0>; 51 }; 52 53 pmu_a53 { 54 compatible = "arm,cortex-a53-pmu"; 55 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 56 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 57 interrupt-affinity = <&a53_0>, <&a53_1>; 58 }; 59 60 psci { 61 compatible = "arm,psci-1.0", "arm,psci-0.2"; 62 method = "smc"; 63 }; 64 65 soc: soc { 66 compatible = "simple-bus"; 67 interrupt-parent = <&gic>; 68 #address-cells = <2>; 69 #size-cells = <2>; 70 ranges; 71 72 rwdt: watchdog@e6020000 { 73 compatible = "renesas,r8a77990-wdt", 74 "renesas,rcar-gen3-wdt"; 75 reg = <0 0xe6020000 0 0x0c>; 76 clocks = <&cpg CPG_MOD 402>; 77 power-domains = <&sysc 32>; 78 resets = <&cpg 402>; 79 status = "disabled"; 80 }; 81 82 gpio0: gpio@e6050000 { 83 compatible = "renesas,gpio-r8a77990", 84 "renesas,rcar-gen3-gpio"; 85 reg = <0 0xe6050000 0 0x50>; 86 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 87 #gpio-cells = <2>; 88 gpio-controller; 89 gpio-ranges = <&pfc 0 0 18>; 90 #interrupt-cells = <2>; 91 interrupt-controller; 92 clocks = <&cpg CPG_MOD 912>; 93 power-domains = <&sysc 32>; 94 resets = <&cpg 912>; 95 }; 96 97 gpio1: gpio@e6051000 { 98 compatible = "renesas,gpio-r8a77990", 99 "renesas,rcar-gen3-gpio"; 100 reg = <0 0xe6051000 0 0x50>; 101 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 102 #gpio-cells = <2>; 103 gpio-controller; 104 gpio-ranges = <&pfc 0 32 23>; 105 #interrupt-cells = <2>; 106 interrupt-controller; 107 clocks = <&cpg CPG_MOD 911>; 108 power-domains = <&sysc 32>; 109 resets = <&cpg 911>; 110 }; 111 112 gpio2: gpio@e6052000 { 113 compatible = "renesas,gpio-r8a77990", 114 "renesas,rcar-gen3-gpio"; 115 reg = <0 0xe6052000 0 0x50>; 116 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 117 #gpio-cells = <2>; 118 gpio-controller; 119 gpio-ranges = <&pfc 0 64 26>; 120 #interrupt-cells = <2>; 121 interrupt-controller; 122 clocks = <&cpg CPG_MOD 910>; 123 power-domains = <&sysc 32>; 124 resets = <&cpg 910>; 125 }; 126 127 gpio3: gpio@e6053000 { 128 compatible = "renesas,gpio-r8a77990", 129 "renesas,rcar-gen3-gpio"; 130 reg = <0 0xe6053000 0 0x50>; 131 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 132 #gpio-cells = <2>; 133 gpio-controller; 134 gpio-ranges = <&pfc 0 96 16>; 135 #interrupt-cells = <2>; 136 interrupt-controller; 137 clocks = <&cpg CPG_MOD 909>; 138 power-domains = <&sysc 32>; 139 resets = <&cpg 909>; 140 }; 141 142 gpio4: gpio@e6054000 { 143 compatible = "renesas,gpio-r8a77990", 144 "renesas,rcar-gen3-gpio"; 145 reg = <0 0xe6054000 0 0x50>; 146 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 147 #gpio-cells = <2>; 148 gpio-controller; 149 gpio-ranges = <&pfc 0 128 11>; 150 #interrupt-cells = <2>; 151 interrupt-controller; 152 clocks = <&cpg CPG_MOD 908>; 153 power-domains = <&sysc 32>; 154 resets = <&cpg 908>; 155 }; 156 157 gpio5: gpio@e6055000 { 158 compatible = "renesas,gpio-r8a77990", 159 "renesas,rcar-gen3-gpio"; 160 reg = <0 0xe6055000 0 0x50>; 161 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 162 #gpio-cells = <2>; 163 gpio-controller; 164 gpio-ranges = <&pfc 0 160 20>; 165 #interrupt-cells = <2>; 166 interrupt-controller; 167 clocks = <&cpg CPG_MOD 907>; 168 power-domains = <&sysc 32>; 169 resets = <&cpg 907>; 170 }; 171 172 gpio6: gpio@e6055400 { 173 compatible = "renesas,gpio-r8a77990", 174 "renesas,rcar-gen3-gpio"; 175 reg = <0 0xe6055400 0 0x50>; 176 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 177 #gpio-cells = <2>; 178 gpio-controller; 179 gpio-ranges = <&pfc 0 192 18>; 180 #interrupt-cells = <2>; 181 interrupt-controller; 182 clocks = <&cpg CPG_MOD 906>; 183 power-domains = <&sysc 32>; 184 resets = <&cpg 906>; 185 }; 186 187 pfc: pin-controller@e6060000 { 188 compatible = "renesas,pfc-r8a77990"; 189 reg = <0 0xe6060000 0 0x508>; 190 }; 191 192 cpg: clock-controller@e6150000 { 193 compatible = "renesas,r8a77990-cpg-mssr"; 194 reg = <0 0xe6150000 0 0x1000>; 195 clocks = <&extal_clk>; 196 clock-names = "extal"; 197 #clock-cells = <2>; 198 #power-domain-cells = <0>; 199 #reset-cells = <1>; 200 }; 201 202 rst: reset-controller@e6160000 { 203 compatible = "renesas,r8a77990-rst"; 204 reg = <0 0xe6160000 0 0x0200>; 205 }; 206 207 sysc: system-controller@e6180000 { 208 compatible = "renesas,r8a77990-sysc"; 209 reg = <0 0xe6180000 0 0x0400>; 210 #power-domain-cells = <1>; 211 }; 212 213 avb: ethernet@e6800000 { 214 compatible = "renesas,etheravb-r8a77990", 215 "renesas,etheravb-rcar-gen3"; 216 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 217 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 242 interrupt-names = "ch0", "ch1", "ch2", "ch3", 243 "ch4", "ch5", "ch6", "ch7", 244 "ch8", "ch9", "ch10", "ch11", 245 "ch12", "ch13", "ch14", "ch15", 246 "ch16", "ch17", "ch18", "ch19", 247 "ch20", "ch21", "ch22", "ch23", 248 "ch24"; 249 clocks = <&cpg CPG_MOD 812>; 250 power-domains = <&sysc 32>; 251 resets = <&cpg 812>; 252 phy-mode = "rgmii"; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 status = "disabled"; 256 }; 257 258 scif2: serial@e6e88000 { 259 compatible = "renesas,scif-r8a77990", 260 "renesas,rcar-gen3-scif", "renesas,scif"; 261 reg = <0 0xe6e88000 0 64>; 262 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&cpg CPG_MOD 310>; 264 clock-names = "fck"; 265 power-domains = <&sysc 32>; 266 resets = <&cpg 310>; 267 status = "disabled"; 268 }; 269 270 ohci0: usb@ee080000 { 271 compatible = "generic-ohci"; 272 reg = <0 0xee080000 0 0x100>; 273 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 274 clocks = <&cpg CPG_MOD 703>; 275 phys = <&usb2_phy0>; 276 phy-names = "usb"; 277 power-domains = <&sysc 32>; 278 resets = <&cpg 703>; 279 status = "disabled"; 280 }; 281 282 ehci0: usb@ee080100 { 283 compatible = "generic-ehci"; 284 reg = <0 0xee080100 0 0x100>; 285 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&cpg CPG_MOD 703>; 287 phys = <&usb2_phy0>; 288 phy-names = "usb"; 289 companion = <&ohci0>; 290 power-domains = <&sysc 32>; 291 resets = <&cpg 703>; 292 status = "disabled"; 293 }; 294 295 usb2_phy0: usb-phy@ee080200 { 296 compatible = "renesas,usb2-phy-r8a77990", 297 "renesas,rcar-gen3-usb2-phy"; 298 reg = <0 0xee080200 0 0x700>; 299 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 300 clocks = <&cpg CPG_MOD 703>; 301 power-domains = <&sysc 32>; 302 resets = <&cpg 703>; 303 #phy-cells = <0>; 304 status = "disabled"; 305 }; 306 307 gic: interrupt-controller@f1010000 { 308 compatible = "arm,gic-400"; 309 #interrupt-cells = <3>; 310 #address-cells = <0>; 311 interrupt-controller; 312 reg = <0x0 0xf1010000 0 0x1000>, 313 <0x0 0xf1020000 0 0x20000>, 314 <0x0 0xf1040000 0 0x20000>, 315 <0x0 0xf1060000 0 0x20000>; 316 interrupts = <GIC_PPI 9 317 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 318 clocks = <&cpg CPG_MOD 408>; 319 clock-names = "clk"; 320 power-domains = <&sysc 32>; 321 resets = <&cpg 408>; 322 }; 323 324 prr: chipid@fff00044 { 325 compatible = "renesas,prr"; 326 reg = <0 0xfff00044 0 4>; 327 }; 328 }; 329 330 timer { 331 compatible = "arm,armv8-timer"; 332 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 333 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 334 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 335 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 336 }; 337}; 338