xref: /linux/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts (revision 1913c7f3fc2514e09262baf2267a82dfdb215c39) 
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the ebisu board
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8/dts-v1/;
9#include "r8a77990.dtsi"
10#include <dt-bindings/gpio/gpio.h>
11
12/ {
13	model = "Renesas Ebisu board based on r8a77990";
14	compatible = "renesas,ebisu", "renesas,r8a77990";
15
16	aliases {
17		serial0 = &scif2;
18		ethernet0 = &avb;
19	};
20
21	chosen {
22		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
23		stdout-path = "serial0:115200n8";
24	};
25
26	audio_clkout: audio-clkout {
27		/*
28		 * This is same as <&rcar_sound 0>
29		 * but needed to avoid cs2000/rcar_sound probe dead-lock
30		 */
31		compatible = "fixed-clock";
32		#clock-cells = <0>;
33		clock-frequency = <11289600>;
34	};
35
36	backlight: backlight {
37		compatible = "pwm-backlight";
38		pwms = <&pwm3 0 50000>;
39
40		brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
41		default-brightness-level = <10>;
42
43		power-supply = <&reg_12p0v>;
44	};
45
46	cvbs-in {
47		compatible = "composite-video-connector";
48		label = "CVBS IN";
49
50		port {
51			cvbs_con: endpoint {
52				remote-endpoint = <&adv7482_ain7>;
53			};
54		};
55	};
56
57	hdmi-in {
58		compatible = "hdmi-connector";
59		label = "HDMI IN";
60		type = "a";
61
62		port {
63			hdmi_in_con: endpoint {
64				remote-endpoint = <&adv7482_hdmi>;
65			};
66		};
67	};
68
69	hdmi-out {
70		compatible = "hdmi-connector";
71		type = "a";
72
73		port {
74			hdmi_con_out: endpoint {
75				remote-endpoint = <&adv7511_out>;
76			};
77		};
78	};
79
80	lvds-decoder {
81		compatible = "thine,thc63lvd1024";
82		vcc-supply = <&reg_3p3v>;
83
84		ports {
85			#address-cells = <1>;
86			#size-cells = <0>;
87
88			port@0 {
89				reg = <0>;
90				thc63lvd1024_in: endpoint {
91					remote-endpoint = <&lvds0_out>;
92				};
93			};
94
95			port@2 {
96				reg = <2>;
97				thc63lvd1024_out: endpoint {
98					remote-endpoint = <&adv7511_in>;
99				};
100			};
101		};
102	};
103
104	memory@48000000 {
105		device_type = "memory";
106		/* first 128MB is reserved for secure area. */
107		reg = <0x0 0x48000000 0x0 0x38000000>;
108	};
109
110	reg_1p8v: regulator0 {
111		compatible = "regulator-fixed";
112		regulator-name = "fixed-1.8V";
113		regulator-min-microvolt = <1800000>;
114		regulator-max-microvolt = <1800000>;
115		regulator-boot-on;
116		regulator-always-on;
117	};
118
119	reg_3p3v: regulator1 {
120		compatible = "regulator-fixed";
121		regulator-name = "fixed-3.3V";
122		regulator-min-microvolt = <3300000>;
123		regulator-max-microvolt = <3300000>;
124		regulator-boot-on;
125		regulator-always-on;
126	};
127
128	reg_12p0v: regulator2 {
129		compatible = "regulator-fixed";
130		regulator-name = "D12.0V";
131		regulator-min-microvolt = <12000000>;
132		regulator-max-microvolt = <12000000>;
133		regulator-boot-on;
134		regulator-always-on;
135	};
136
137	rsnd_ak4613: sound {
138		compatible = "simple-audio-card";
139
140		simple-audio-card,name = "rsnd-ak4613";
141		simple-audio-card,format = "left_j";
142		simple-audio-card,bitclock-master = <&sndcpu>;
143		simple-audio-card,frame-master = <&sndcpu>;
144
145		sndcodec: simple-audio-card,codec {
146			sound-dai = <&ak4613>;
147		};
148
149		sndcpu: simple-audio-card,cpu {
150			sound-dai = <&rcar_sound>;
151		};
152	};
153
154	vbus0_usb2: regulator-vbus0-usb2 {
155		compatible = "regulator-fixed";
156
157		regulator-name = "USB20_VBUS_CN";
158		regulator-min-microvolt = <5000000>;
159		regulator-max-microvolt = <5000000>;
160
161		gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>;
162		enable-active-high;
163	};
164
165	vcc_sdhi0: regulator-vcc-sdhi0 {
166		compatible = "regulator-fixed";
167
168		regulator-name = "SDHI0 Vcc";
169		regulator-min-microvolt = <3300000>;
170		regulator-max-microvolt = <3300000>;
171
172		gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
173		enable-active-high;
174	};
175
176	vccq_sdhi0: regulator-vccq-sdhi0 {
177		compatible = "regulator-gpio";
178
179		regulator-name = "SDHI0 VccQ";
180		regulator-min-microvolt = <1800000>;
181		regulator-max-microvolt = <3300000>;
182
183		gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
184		gpios-states = <1>;
185		states = <3300000 1
186			  1800000 0>;
187	};
188
189	vcc_sdhi1: regulator-vcc-sdhi1 {
190		compatible = "regulator-fixed";
191
192		regulator-name = "SDHI1 Vcc";
193		regulator-min-microvolt = <3300000>;
194		regulator-max-microvolt = <3300000>;
195
196		gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
197		enable-active-high;
198	};
199
200	vccq_sdhi1: regulator-vccq-sdhi1 {
201		compatible = "regulator-gpio";
202
203		regulator-name = "SDHI1 VccQ";
204		regulator-min-microvolt = <1800000>;
205		regulator-max-microvolt = <3300000>;
206
207		gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
208		gpios-states = <1>;
209		states = <3300000 1
210			  1800000 0>;
211	};
212
213	vga {
214		compatible = "vga-connector";
215
216		port {
217			vga_in: endpoint {
218				remote-endpoint = <&adv7123_out>;
219			};
220		};
221	};
222
223	vga-encoder {
224		compatible = "adi,adv7123";
225
226		ports {
227			#address-cells = <1>;
228			#size-cells = <0>;
229
230			port@0 {
231				reg = <0>;
232				adv7123_in: endpoint {
233					remote-endpoint = <&du_out_rgb>;
234				};
235			};
236			port@1 {
237				reg = <1>;
238				adv7123_out: endpoint {
239					remote-endpoint = <&vga_in>;
240				};
241			};
242		};
243	};
244
245	x12_clk: x12 {
246		compatible = "fixed-clock";
247		#clock-cells = <0>;
248		clock-frequency = <24576000>;
249	};
250
251	x13_clk: x13 {
252		compatible = "fixed-clock";
253		#clock-cells = <0>;
254		clock-frequency = <74250000>;
255	};
256};
257
258&audio_clk_a {
259	clock-frequency = <22579200>;
260};
261
262&avb {
263	pinctrl-0 = <&avb_pins>;
264	pinctrl-names = "default";
265	phy-handle = <&phy0>;
266	status = "okay";
267
268	phy0: ethernet-phy@0 {
269		rxc-skew-ps = <1500>;
270		reg = <0>;
271		interrupt-parent = <&gpio2>;
272		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
273		reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
274		/*
275		 * TX clock internal delay mode is required for reliable
276		 * 1Gbps communication using the KSZ9031RNX phy present on
277		 * the Ebisu board, however, TX clock internal delay mode
278		 * isn't supported on r8a77990.  Thus, limit speed to
279		 * 100Mbps for reliable communication.
280		 */
281		max-speed = <100>;
282	};
283};
284
285&canfd {
286	pinctrl-0 = <&canfd0_pins>;
287	pinctrl-names = "default";
288	status = "okay";
289
290	channel0 {
291		status = "okay";
292	};
293};
294
295&csi40 {
296	status = "okay";
297
298	ports {
299		port@0 {
300			reg = <0>;
301
302			csi40_in: endpoint {
303				clock-lanes = <0>;
304				data-lanes = <1 2>;
305				remote-endpoint = <&adv7482_txa>;
306			};
307		};
308	};
309};
310
311&du {
312	pinctrl-0 = <&du_pins>;
313	pinctrl-names = "default";
314	status = "okay";
315
316	clocks = <&cpg CPG_MOD 724>,
317		 <&cpg CPG_MOD 723>,
318		 <&x13_clk>;
319	clock-names = "du.0", "du.1", "dclkin.0";
320
321	ports {
322		port@0 {
323			endpoint {
324				remote-endpoint = <&adv7123_in>;
325			};
326		};
327	};
328};
329
330&ehci0 {
331	dr_mode = "otg";
332	status = "okay";
333};
334
335&extal_clk {
336	clock-frequency = <48000000>;
337};
338
339&hsusb {
340	dr_mode = "otg";
341	status = "okay";
342};
343
344&i2c0 {
345	status = "okay";
346
347	io_expander: gpio@20 {
348		compatible = "onnn,pca9654";
349		reg = <0x20>;
350		gpio-controller;
351		#gpio-cells = <2>;
352		interrupt-parent = <&gpio2>;
353		interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
354	};
355
356	hdmi-encoder@39 {
357		compatible = "adi,adv7511w";
358		reg = <0x39>;
359		interrupt-parent = <&gpio1>;
360		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
361
362		adi,input-depth = <8>;
363		adi,input-colorspace = "rgb";
364		adi,input-clock = "1x";
365		adi,input-style = <1>;
366		adi,input-justification = "evenly";
367
368		ports {
369			#address-cells = <1>;
370			#size-cells = <0>;
371
372			port@0 {
373				reg = <0>;
374				adv7511_in: endpoint {
375					remote-endpoint = <&thc63lvd1024_out>;
376				};
377			};
378
379			port@1 {
380				reg = <1>;
381				adv7511_out: endpoint {
382					remote-endpoint = <&hdmi_con_out>;
383				};
384			};
385		};
386	};
387
388	video-receiver@70 {
389		compatible = "adi,adv7482";
390		reg = <0x70>;
391
392		#address-cells = <1>;
393		#size-cells = <0>;
394
395		interrupt-parent = <&gpio0>;
396		interrupt-names = "intrq1", "intrq2";
397		interrupts = <7 IRQ_TYPE_LEVEL_LOW>,
398			     <17 IRQ_TYPE_LEVEL_LOW>;
399
400		port@7 {
401			reg = <7>;
402
403			adv7482_ain7: endpoint {
404				remote-endpoint = <&cvbs_con>;
405			};
406		};
407
408		port@8 {
409			reg = <8>;
410
411			adv7482_hdmi: endpoint {
412				remote-endpoint = <&hdmi_in_con>;
413			};
414		};
415
416		port@a {
417			reg = <10>;
418
419			adv7482_txa: endpoint {
420				clock-lanes = <0>;
421				data-lanes = <1 2>;
422				remote-endpoint = <&csi40_in>;
423			};
424		};
425	};
426};
427
428&i2c3 {
429	status = "okay";
430
431	ak4613: codec@10 {
432		compatible = "asahi-kasei,ak4613";
433		#sound-dai-cells = <0>;
434		reg = <0x10>;
435		clocks = <&rcar_sound 3>;
436
437		asahi-kasei,in1-single-end;
438		asahi-kasei,in2-single-end;
439		asahi-kasei,out1-single-end;
440		asahi-kasei,out2-single-end;
441		asahi-kasei,out3-single-end;
442		asahi-kasei,out4-single-end;
443		asahi-kasei,out5-single-end;
444		asahi-kasei,out6-single-end;
445	};
446
447	cs2000: clk-multiplier@4f {
448		#clock-cells = <0>;
449		compatible = "cirrus,cs2000-cp";
450		reg = <0x4f>;
451		clocks = <&audio_clkout>, <&x12_clk>;
452		clock-names = "clk_in", "ref_clk";
453
454		assigned-clocks = <&cs2000>;
455		assigned-clock-rates = <24576000>; /* 1/1 divide */
456	};
457};
458
459&i2c_dvfs {
460	status = "okay";
461
462	clock-frequency = <400000>;
463
464	pmic: pmic@30 {
465		pinctrl-0 = <&irq0_pins>;
466		pinctrl-names = "default";
467
468		compatible = "rohm,bd9571mwv";
469		reg = <0x30>;
470		interrupt-parent = <&intc_ex>;
471		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
472		interrupt-controller;
473		#interrupt-cells = <2>;
474		gpio-controller;
475		#gpio-cells = <2>;
476		rohm,ddr-backup-power = <0x1>;
477		rohm,rstbmode-level;
478	};
479};
480
481&lvds0 {
482	status = "okay";
483
484	clocks = <&cpg CPG_MOD 727>,
485		 <&x13_clk>,
486		 <&extal_clk>;
487	clock-names = "fck", "dclkin.0", "extal";
488
489	ports {
490		port@1 {
491			lvds0_out: endpoint {
492				remote-endpoint = <&thc63lvd1024_in>;
493			};
494		};
495	};
496};
497
498&lvds1 {
499	/*
500	 * Even though the LVDS1 output is not connected, the encoder must be
501	 * enabled to supply a pixel clock to the DU for the DPAD output when
502	 * LVDS0 is in use.
503	 */
504	status = "okay";
505
506	clocks = <&cpg CPG_MOD 727>,
507		 <&x13_clk>,
508		 <&extal_clk>;
509	clock-names = "fck", "dclkin.0", "extal";
510};
511
512&ohci0 {
513	dr_mode = "otg";
514	status = "okay";
515};
516
517&pcie_bus_clk {
518	clock-frequency = <100000000>;
519};
520
521&pciec0 {
522	status = "okay";
523};
524
525&pfc {
526	avb_pins: avb {
527		mux {
528			groups = "avb_link", "avb_mii";
529			function = "avb";
530		};
531	};
532
533	canfd0_pins: canfd0 {
534		groups = "canfd0_data";
535		function = "canfd0";
536	};
537
538	du_pins: du {
539		groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
540		function = "du";
541	};
542
543	irq0_pins: irq0 {
544		groups = "intc_ex_irq0";
545		function = "intc_ex";
546	};
547
548	pwm3_pins: pwm3 {
549		groups = "pwm3_b";
550		function = "pwm3";
551	};
552
553	pwm5_pins: pwm5 {
554		groups = "pwm5_a";
555		function = "pwm5";
556	};
557
558	scif2_pins: scif2 {
559		groups = "scif2_data_a";
560		function = "scif2";
561	};
562
563	sdhi0_pins: sd0 {
564		groups = "sdhi0_data4", "sdhi0_ctrl";
565		function = "sdhi0";
566		power-source = <3300>;
567	};
568
569	sdhi0_pins_uhs: sd0_uhs {
570		groups = "sdhi0_data4", "sdhi0_ctrl";
571		function = "sdhi0";
572		power-source = <1800>;
573	};
574
575	sdhi1_pins: sd1 {
576		groups = "sdhi1_data4", "sdhi1_ctrl";
577		function = "sdhi1";
578		power-source = <3300>;
579	};
580
581	sdhi1_pins_uhs: sd1_uhs {
582		groups = "sdhi1_data4", "sdhi1_ctrl";
583		function = "sdhi1";
584		power-source = <1800>;
585	};
586
587	sdhi3_pins: sd3 {
588		groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
589		function = "sdhi3";
590		power-source = <1800>;
591	};
592
593	sound_clk_pins: sound_clk {
594		groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a",
595			 "audio_clkout_a", "audio_clkout1_a";
596		function = "audio_clk";
597	};
598
599	sound_pins: sound {
600		groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
601		function = "ssi";
602	};
603
604	usb0_pins: usb {
605		groups = "usb0_b", "usb0_id";
606		function = "usb0";
607	};
608
609	usb30_pins: usb30 {
610		groups = "usb30";
611		function = "usb30";
612	};
613};
614
615&pwm3 {
616	pinctrl-0 = <&pwm3_pins>;
617	pinctrl-names = "default";
618
619	status = "okay";
620};
621
622&pwm5 {
623	pinctrl-0 = <&pwm5_pins>;
624	pinctrl-names = "default";
625
626	status = "okay";
627};
628
629&rcar_sound {
630	pinctrl-0 = <&sound_pins &sound_clk_pins>;
631	pinctrl-names = "default";
632
633	/* Single DAI */
634	#sound-dai-cells = <0>;
635
636	/* audio_clkout0/1/2/3 */
637	#clock-cells = <1>;
638	clock-frequency = <12288000 11289600>;
639	clkout-lr-synchronous;
640
641	status = "okay";
642
643	/* update <audio_clk_b> to <cs2000> */
644	clocks = <&cpg CPG_MOD 1005>,
645		 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
646		 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
647		 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
648		 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
649		 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
650		 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
651		 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
652		 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
653		 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
654		 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
655		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
656		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
657		 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
658		 <&audio_clk_a>, <&cs2000>, <&audio_clk_c>,
659		 <&cpg CPG_CORE R8A77990_CLK_ZA2>;
660
661	rcar_sound,dai {
662		dai0 {
663			playback = <&ssi0 &src0 &dvc0>;
664			capture  = <&ssi1 &src1 &dvc1>;
665		};
666	};
667
668};
669
670&rwdt {
671	timeout-sec = <60>;
672	status = "okay";
673};
674
675&scif2 {
676	pinctrl-0 = <&scif2_pins>;
677	pinctrl-names = "default";
678
679	status = "okay";
680};
681
682&sdhi0 {
683	pinctrl-0 = <&sdhi0_pins>;
684	pinctrl-1 = <&sdhi0_pins_uhs>;
685	pinctrl-names = "default", "state_uhs";
686
687	vmmc-supply = <&vcc_sdhi0>;
688	vqmmc-supply = <&vccq_sdhi0>;
689	cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
690	wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
691	bus-width = <4>;
692	sd-uhs-sdr50;
693	sd-uhs-sdr104;
694	status = "okay";
695};
696
697&sdhi1 {
698	pinctrl-0 = <&sdhi1_pins>;
699	pinctrl-1 = <&sdhi1_pins_uhs>;
700	pinctrl-names = "default", "state_uhs";
701
702	vmmc-supply = <&vcc_sdhi1>;
703	vqmmc-supply = <&vccq_sdhi1>;
704	cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
705	bus-width = <4>;
706	sd-uhs-sdr50;
707	sd-uhs-sdr104;
708	status = "okay";
709};
710
711&sdhi3 {
712	/* used for on-board 8bit eMMC */
713	pinctrl-0 = <&sdhi3_pins>;
714	pinctrl-1 = <&sdhi3_pins>;
715	pinctrl-names = "default", "state_uhs";
716
717	vmmc-supply = <&reg_3p3v>;
718	vqmmc-supply = <&reg_1p8v>;
719	mmc-hs200-1_8v;
720	mmc-hs400-1_8v;
721	bus-width = <8>;
722	non-removable;
723	status = "okay";
724};
725
726&ssi1 {
727	shared-pin;
728};
729
730&usb2_phy0 {
731	pinctrl-0 = <&usb0_pins>;
732	pinctrl-names = "default";
733
734	vbus-supply = <&vbus0_usb2>;
735	status = "okay";
736};
737
738&usb3_peri0 {
739	companion = <&xhci0>;
740	status = "okay";
741};
742
743&vin4 {
744	status = "okay";
745};
746
747&vin5 {
748	status = "okay";
749};
750
751&xhci0 {
752	pinctrl-0 = <&usb30_pins>;
753	pinctrl-names = "default";
754
755	status = "okay";
756};
757