1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car V3H (R8A77980) SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8 9#include <dt-bindings/clock/r8a77980-cpg-mssr.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/r8a77980-sysc.h> 13 14/ { 15 compatible = "renesas,r8a77980"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 i2c0 = &i2c0; 21 i2c1 = &i2c1; 22 i2c2 = &i2c2; 23 i2c3 = &i2c3; 24 i2c4 = &i2c4; 25 i2c5 = &i2c5; 26 }; 27 28 /* External CAN clock - to be overridden by boards that provide it */ 29 can_clk: can { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <0>; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 a53_0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53", "arm,armv8"; 42 reg = <0>; 43 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 44 power-domains = <&sysc R8A77980_PD_CA53_CPU0>; 45 next-level-cache = <&L2_CA53>; 46 enable-method = "psci"; 47 }; 48 49 a53_1: cpu@1 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53", "arm,armv8"; 52 reg = <1>; 53 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 54 power-domains = <&sysc R8A77980_PD_CA53_CPU1>; 55 next-level-cache = <&L2_CA53>; 56 enable-method = "psci"; 57 }; 58 59 a53_2: cpu@2 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53", "arm,armv8"; 62 reg = <2>; 63 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 64 power-domains = <&sysc R8A77980_PD_CA53_CPU2>; 65 next-level-cache = <&L2_CA53>; 66 enable-method = "psci"; 67 }; 68 69 a53_3: cpu@3 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53", "arm,armv8"; 72 reg = <3>; 73 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 74 power-domains = <&sysc R8A77980_PD_CA53_CPU3>; 75 next-level-cache = <&L2_CA53>; 76 enable-method = "psci"; 77 }; 78 79 L2_CA53: cache-controller { 80 compatible = "cache"; 81 power-domains = <&sysc R8A77980_PD_CA53_SCU>; 82 cache-unified; 83 cache-level = <2>; 84 }; 85 }; 86 87 extal_clk: extal { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 /* This value must be overridden by the board */ 91 clock-frequency = <0>; 92 }; 93 94 extalr_clk: extalr { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 /* This value must be overridden by the board */ 98 clock-frequency = <0>; 99 }; 100 101 /* External PCIe clock - can be overridden by the board */ 102 pcie_bus_clk: pcie_bus { 103 compatible = "fixed-clock"; 104 #clock-cells = <0>; 105 clock-frequency = <0>; 106 }; 107 108 pmu_a53 { 109 compatible = "arm,cortex-a53-pmu"; 110 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 111 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 112 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 113 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 114 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 115 }; 116 117 psci { 118 compatible = "arm,psci-1.0", "arm,psci-0.2"; 119 method = "smc"; 120 }; 121 122 /* External SCIF clock - to be overridden by boards that provide it */ 123 scif_clk: scif { 124 compatible = "fixed-clock"; 125 #clock-cells = <0>; 126 clock-frequency = <0>; 127 }; 128 129 soc { 130 compatible = "simple-bus"; 131 interrupt-parent = <&gic>; 132 133 #address-cells = <2>; 134 #size-cells = <2>; 135 ranges; 136 137 rwdt: watchdog@e6020000 { 138 compatible = "renesas,r8a77980-wdt", 139 "renesas,rcar-gen3-wdt"; 140 reg = <0 0xe6020000 0 0x0c>; 141 clocks = <&cpg CPG_MOD 402>; 142 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 143 resets = <&cpg 402>; 144 status = "disabled"; 145 }; 146 147 gpio0: gpio@e6050000 { 148 compatible = "renesas,gpio-r8a77980", 149 "renesas,rcar-gen3-gpio"; 150 reg = <0 0xe6050000 0 0x50>; 151 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 152 #gpio-cells = <2>; 153 gpio-controller; 154 gpio-ranges = <&pfc 0 0 22>; 155 #interrupt-cells = <2>; 156 interrupt-controller; 157 clocks = <&cpg CPG_MOD 912>; 158 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 159 resets = <&cpg 912>; 160 }; 161 162 gpio1: gpio@e6051000 { 163 compatible = "renesas,gpio-r8a77980", 164 "renesas,rcar-gen3-gpio"; 165 reg = <0 0xe6051000 0 0x50>; 166 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 167 #gpio-cells = <2>; 168 gpio-controller; 169 gpio-ranges = <&pfc 0 32 28>; 170 #interrupt-cells = <2>; 171 interrupt-controller; 172 clocks = <&cpg CPG_MOD 911>; 173 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 174 resets = <&cpg 911>; 175 }; 176 177 gpio2: gpio@e6052000 { 178 compatible = "renesas,gpio-r8a77980", 179 "renesas,rcar-gen3-gpio"; 180 reg = <0 0xe6052000 0 0x50>; 181 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 182 #gpio-cells = <2>; 183 gpio-controller; 184 gpio-ranges = <&pfc 0 64 30>; 185 #interrupt-cells = <2>; 186 interrupt-controller; 187 clocks = <&cpg CPG_MOD 910>; 188 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 189 resets = <&cpg 910>; 190 }; 191 192 gpio3: gpio@e6053000 { 193 compatible = "renesas,gpio-r8a77980", 194 "renesas,rcar-gen3-gpio"; 195 reg = <0 0xe6053000 0 0x50>; 196 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 197 #gpio-cells = <2>; 198 gpio-controller; 199 gpio-ranges = <&pfc 0 96 17>; 200 #interrupt-cells = <2>; 201 interrupt-controller; 202 clocks = <&cpg CPG_MOD 909>; 203 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 204 resets = <&cpg 909>; 205 }; 206 207 gpio4: gpio@e6054000 { 208 compatible = "renesas,gpio-r8a77980", 209 "renesas,rcar-gen3-gpio"; 210 reg = <0 0xe6054000 0 0x50>; 211 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 212 #gpio-cells = <2>; 213 gpio-controller; 214 gpio-ranges = <&pfc 0 128 25>; 215 #interrupt-cells = <2>; 216 interrupt-controller; 217 clocks = <&cpg CPG_MOD 908>; 218 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 219 resets = <&cpg 908>; 220 }; 221 222 gpio5: gpio@e6055000 { 223 compatible = "renesas,gpio-r8a77980", 224 "renesas,rcar-gen3-gpio"; 225 reg = <0 0xe6055000 0 0x50>; 226 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 227 #gpio-cells = <2>; 228 gpio-controller; 229 gpio-ranges = <&pfc 0 160 15>; 230 #interrupt-cells = <2>; 231 interrupt-controller; 232 clocks = <&cpg CPG_MOD 907>; 233 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 234 resets = <&cpg 907>; 235 }; 236 237 pfc: pin-controller@e6060000 { 238 compatible = "renesas,pfc-r8a77980"; 239 reg = <0 0xe6060000 0 0x50c>; 240 }; 241 242 cmt0: timer@e60f0000 { 243 compatible = "renesas,r8a77980-cmt0", 244 "renesas,rcar-gen3-cmt0"; 245 reg = <0 0xe60f0000 0 0x1004>; 246 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&cpg CPG_MOD 303>; 249 clock-names = "fck"; 250 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 251 resets = <&cpg 303>; 252 status = "disabled"; 253 }; 254 255 cmt1: timer@e6130000 { 256 compatible = "renesas,r8a77980-cmt1", 257 "renesas,rcar-gen3-cmt1"; 258 reg = <0 0xe6130000 0 0x1004>; 259 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&cpg CPG_MOD 302>; 268 clock-names = "fck"; 269 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 270 resets = <&cpg 302>; 271 status = "disabled"; 272 }; 273 274 cmt2: timer@e6140000 { 275 compatible = "renesas,r8a77980-cmt1", 276 "renesas,rcar-gen3-cmt1"; 277 reg = <0 0xe6140000 0 0x1004>; 278 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&cpg CPG_MOD 301>; 287 clock-names = "fck"; 288 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 289 resets = <&cpg 301>; 290 status = "disabled"; 291 }; 292 293 cmt3: timer@e6148000 { 294 compatible = "renesas,r8a77980-cmt1", 295 "renesas,rcar-gen3-cmt1"; 296 reg = <0 0xe6148000 0 0x1004>; 297 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&cpg CPG_MOD 300>; 306 clock-names = "fck"; 307 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 308 resets = <&cpg 300>; 309 status = "disabled"; 310 }; 311 312 cpg: clock-controller@e6150000 { 313 compatible = "renesas,r8a77980-cpg-mssr"; 314 reg = <0 0xe6150000 0 0x1000>; 315 clocks = <&extal_clk>, <&extalr_clk>; 316 clock-names = "extal", "extalr"; 317 #clock-cells = <2>; 318 #power-domain-cells = <0>; 319 #reset-cells = <1>; 320 }; 321 322 rst: reset-controller@e6160000 { 323 compatible = "renesas,r8a77980-rst"; 324 reg = <0 0xe6160000 0 0x200>; 325 }; 326 327 sysc: system-controller@e6180000 { 328 compatible = "renesas,r8a77980-sysc"; 329 reg = <0 0xe6180000 0 0x440>; 330 #power-domain-cells = <1>; 331 }; 332 333 intc_ex: interrupt-controller@e61c0000 { 334 compatible = "renesas,intc-ex-r8a77980", "renesas,irqc"; 335 #interrupt-cells = <2>; 336 interrupt-controller; 337 reg = <0 0xe61c0000 0 0x200>; 338 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 339 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 340 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 341 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 342 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 343 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&cpg CPG_MOD 407>; 345 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 346 resets = <&cpg 407>; 347 }; 348 349 i2c0: i2c@e6500000 { 350 compatible = "renesas,i2c-r8a77980", 351 "renesas,rcar-gen3-i2c"; 352 reg = <0 0xe6500000 0 0x40>; 353 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&cpg CPG_MOD 931>; 355 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 356 resets = <&cpg 931>; 357 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 358 <&dmac2 0x91>, <&dmac2 0x90>; 359 dma-names = "tx", "rx", "tx", "rx"; 360 i2c-scl-internal-delay-ns = <6>; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 status = "disabled"; 364 }; 365 366 i2c1: i2c@e6508000 { 367 compatible = "renesas,i2c-r8a77980", 368 "renesas,rcar-gen3-i2c"; 369 reg = <0 0xe6508000 0 0x40>; 370 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&cpg CPG_MOD 930>; 372 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 373 resets = <&cpg 930>; 374 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 375 <&dmac2 0x93>, <&dmac2 0x92>; 376 dma-names = "tx", "rx", "tx", "rx"; 377 i2c-scl-internal-delay-ns = <6>; 378 #address-cells = <1>; 379 #size-cells = <0>; 380 status = "disabled"; 381 }; 382 383 i2c2: i2c@e6510000 { 384 compatible = "renesas,i2c-r8a77980", 385 "renesas,rcar-gen3-i2c"; 386 reg = <0 0xe6510000 0 0x40>; 387 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 388 clocks = <&cpg CPG_MOD 929>; 389 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 390 resets = <&cpg 929>; 391 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 392 <&dmac2 0x95>, <&dmac2 0x94>; 393 dma-names = "tx", "rx", "tx", "rx"; 394 i2c-scl-internal-delay-ns = <6>; 395 #address-cells = <1>; 396 #size-cells = <0>; 397 status = "disabled"; 398 }; 399 400 i2c3: i2c@e66d0000 { 401 compatible = "renesas,i2c-r8a77980", 402 "renesas,rcar-gen3-i2c"; 403 reg = <0 0xe66d0000 0 0x40>; 404 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&cpg CPG_MOD 928>; 406 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 407 resets = <&cpg 928>; 408 i2c-scl-internal-delay-ns = <6>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 status = "disabled"; 412 }; 413 414 i2c4: i2c@e66d8000 { 415 compatible = "renesas,i2c-r8a77980", 416 "renesas,rcar-gen3-i2c"; 417 reg = <0 0xe66d8000 0 0x40>; 418 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&cpg CPG_MOD 927>; 420 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 421 resets = <&cpg 927>; 422 i2c-scl-internal-delay-ns = <6>; 423 #address-cells = <1>; 424 #size-cells = <0>; 425 status = "disabled"; 426 }; 427 428 i2c5: i2c@e66e0000 { 429 compatible = "renesas,i2c-r8a77980", 430 "renesas,rcar-gen3-i2c"; 431 reg = <0 0xe66e0000 0 0x40>; 432 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&cpg CPG_MOD 919>; 434 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 435 resets = <&cpg 919>; 436 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>, 437 <&dmac2 0x9b>, <&dmac2 0x9a>; 438 dma-names = "tx", "rx", "tx", "rx"; 439 i2c-scl-internal-delay-ns = <6>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 status = "disabled"; 443 }; 444 445 hscif0: serial@e6540000 { 446 compatible = "renesas,hscif-r8a77980", 447 "renesas,rcar-gen3-hscif", 448 "renesas,hscif"; 449 reg = <0 0xe6540000 0 0x60>; 450 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&cpg CPG_MOD 520>, 452 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 453 <&scif_clk>; 454 clock-names = "fck", "brg_int", "scif_clk"; 455 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 456 <&dmac2 0x31>, <&dmac2 0x30>; 457 dma-names = "tx", "rx", "tx", "rx"; 458 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 459 resets = <&cpg 520>; 460 status = "disabled"; 461 }; 462 463 hscif1: serial@e6550000 { 464 compatible = "renesas,hscif-r8a77980", 465 "renesas,rcar-gen3-hscif", 466 "renesas,hscif"; 467 reg = <0 0xe6550000 0 0x60>; 468 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&cpg CPG_MOD 519>, 470 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 471 <&scif_clk>; 472 clock-names = "fck", "brg_int", "scif_clk"; 473 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 474 <&dmac2 0x33>, <&dmac2 0x32>; 475 dma-names = "tx", "rx", "tx", "rx"; 476 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 477 resets = <&cpg 519>; 478 status = "disabled"; 479 }; 480 481 hscif2: serial@e6560000 { 482 compatible = "renesas,hscif-r8a77980", 483 "renesas,rcar-gen3-hscif", 484 "renesas,hscif"; 485 reg = <0 0xe6560000 0 0x60>; 486 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&cpg CPG_MOD 518>, 488 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 489 <&scif_clk>; 490 clock-names = "fck", "brg_int", "scif_clk"; 491 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 492 <&dmac2 0x35>, <&dmac2 0x34>; 493 dma-names = "tx", "rx", "tx", "rx"; 494 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 495 resets = <&cpg 518>; 496 status = "disabled"; 497 }; 498 499 hscif3: serial@e66a0000 { 500 compatible = "renesas,hscif-r8a77980", 501 "renesas,rcar-gen3-hscif", 502 "renesas,hscif"; 503 reg = <0 0xe66a0000 0 0x60>; 504 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&cpg CPG_MOD 517>, 506 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 507 <&scif_clk>; 508 clock-names = "fck", "brg_int", "scif_clk"; 509 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 510 <&dmac2 0x37>, <&dmac2 0x36>; 511 dma-names = "tx", "rx", "tx", "rx"; 512 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 513 resets = <&cpg 517>; 514 status = "disabled"; 515 }; 516 517 pcie_phy: pcie-phy@e65d0000 { 518 compatible = "renesas,r8a77980-pcie-phy"; 519 reg = <0 0xe65d0000 0 0x8000>; 520 #phy-cells = <0>; 521 clocks = <&cpg CPG_MOD 319>; 522 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 523 resets = <&cpg 319>; 524 status = "disabled"; 525 }; 526 527 canfd: can@e66c0000 { 528 compatible = "renesas,r8a77980-canfd", 529 "renesas,rcar-gen3-canfd"; 530 reg = <0 0xe66c0000 0 0x8000>; 531 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&cpg CPG_MOD 914>, 534 <&cpg CPG_CORE R8A77980_CLK_CANFD>, 535 <&can_clk>; 536 clock-names = "fck", "canfd", "can_clk"; 537 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>; 538 assigned-clock-rates = <40000000>; 539 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 540 resets = <&cpg 914>; 541 status = "disabled"; 542 543 channel0 { 544 status = "disabled"; 545 }; 546 547 channel1 { 548 status = "disabled"; 549 }; 550 }; 551 552 avb: ethernet@e6800000 { 553 compatible = "renesas,etheravb-r8a77980", 554 "renesas,etheravb-rcar-gen3"; 555 reg = <0 0xe6800000 0 0x800>; 556 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 581 interrupt-names = "ch0", "ch1", "ch2", "ch3", 582 "ch4", "ch5", "ch6", "ch7", 583 "ch8", "ch9", "ch10", "ch11", 584 "ch12", "ch13", "ch14", "ch15", 585 "ch16", "ch17", "ch18", "ch19", 586 "ch20", "ch21", "ch22", "ch23", 587 "ch24"; 588 clocks = <&cpg CPG_MOD 812>; 589 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 590 resets = <&cpg 812>; 591 phy-mode = "rgmii"; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 status = "disabled"; 595 }; 596 597 pwm0: pwm@e6e30000 { 598 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; 599 reg = <0 0xe6e30000 0 0x10>; 600 #pwm-cells = <2>; 601 clocks = <&cpg CPG_MOD 523>; 602 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 603 resets = <&cpg 523>; 604 status = "disabled"; 605 }; 606 607 pwm1: pwm@e6e31000 { 608 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; 609 reg = <0 0xe6e31000 0 0x10>; 610 #pwm-cells = <2>; 611 clocks = <&cpg CPG_MOD 523>; 612 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 613 resets = <&cpg 523>; 614 status = "disabled"; 615 }; 616 617 pwm2: pwm@e6e32000 { 618 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; 619 reg = <0 0xe6e32000 0 0x10>; 620 #pwm-cells = <2>; 621 clocks = <&cpg CPG_MOD 523>; 622 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 623 resets = <&cpg 523>; 624 status = "disabled"; 625 }; 626 627 pwm3: pwm@e6e33000 { 628 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; 629 reg = <0 0xe6e33000 0 0x10>; 630 #pwm-cells = <2>; 631 clocks = <&cpg CPG_MOD 523>; 632 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 633 resets = <&cpg 523>; 634 status = "disabled"; 635 }; 636 637 pwm4: pwm@e6e34000 { 638 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; 639 reg = <0 0xe6e34000 0 0x10>; 640 #pwm-cells = <2>; 641 clocks = <&cpg CPG_MOD 523>; 642 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 643 resets = <&cpg 523>; 644 status = "disabled"; 645 }; 646 647 scif0: serial@e6e60000 { 648 compatible = "renesas,scif-r8a77980", 649 "renesas,rcar-gen3-scif", 650 "renesas,scif"; 651 reg = <0 0xe6e60000 0 0x40>; 652 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 653 clocks = <&cpg CPG_MOD 207>, 654 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 655 <&scif_clk>; 656 clock-names = "fck", "brg_int", "scif_clk"; 657 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 658 <&dmac2 0x51>, <&dmac2 0x50>; 659 dma-names = "tx", "rx", "tx", "rx"; 660 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 661 resets = <&cpg 207>; 662 status = "disabled"; 663 }; 664 665 scif1: serial@e6e68000 { 666 compatible = "renesas,scif-r8a77980", 667 "renesas,rcar-gen3-scif", 668 "renesas,scif"; 669 reg = <0 0xe6e68000 0 0x40>; 670 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&cpg CPG_MOD 206>, 672 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 673 <&scif_clk>; 674 clock-names = "fck", "brg_int", "scif_clk"; 675 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 676 <&dmac2 0x53>, <&dmac2 0x52>; 677 dma-names = "tx", "rx", "tx", "rx"; 678 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 679 resets = <&cpg 206>; 680 status = "disabled"; 681 }; 682 683 scif3: serial@e6c50000 { 684 compatible = "renesas,scif-r8a77980", 685 "renesas,rcar-gen3-scif", 686 "renesas,scif"; 687 reg = <0 0xe6c50000 0 0x40>; 688 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&cpg CPG_MOD 204>, 690 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 691 <&scif_clk>; 692 clock-names = "fck", "brg_int", "scif_clk"; 693 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 694 <&dmac2 0x57>, <&dmac2 0x56>; 695 dma-names = "tx", "rx", "tx", "rx"; 696 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 697 resets = <&cpg 204>; 698 status = "disabled"; 699 }; 700 701 scif4: serial@e6c40000 { 702 compatible = "renesas,scif-r8a77980", 703 "renesas,rcar-gen3-scif", 704 "renesas,scif"; 705 reg = <0 0xe6c40000 0 0x40>; 706 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&cpg CPG_MOD 203>, 708 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 709 <&scif_clk>; 710 clock-names = "fck", "brg_int", "scif_clk"; 711 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 712 <&dmac2 0x59>, <&dmac2 0x58>; 713 dma-names = "tx", "rx", "tx", "rx"; 714 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 715 resets = <&cpg 203>; 716 status = "disabled"; 717 }; 718 719 tpu: pwm@e6e80000 { 720 compatible = "renesas,tpu-r8a77980", "renesas,tpu"; 721 reg = <0 0xe6e80000 0 0x148>; 722 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&cpg CPG_MOD 304>; 724 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 725 resets = <&cpg 304>; 726 #pwm-cells = <3>; 727 status = "disabled"; 728 }; 729 730 vin0: video@e6ef0000 { 731 compatible = "renesas,vin-r8a77980"; 732 reg = <0 0xe6ef0000 0 0x1000>; 733 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 734 clocks = <&cpg CPG_MOD 811>; 735 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 736 resets = <&cpg 811>; 737 status = "disabled"; 738 739 ports { 740 #address-cells = <1>; 741 #size-cells = <0>; 742 743 port@1 { 744 #address-cells = <1>; 745 #size-cells = <0>; 746 747 reg = <1>; 748 749 vin0csi40: endpoint@2 { 750 reg = <2>; 751 remote-endpoint = <&csi40vin0>; 752 }; 753 }; 754 }; 755 }; 756 757 vin1: video@e6ef1000 { 758 compatible = "renesas,vin-r8a77980"; 759 reg = <0 0xe6ef1000 0 0x1000>; 760 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 761 clocks = <&cpg CPG_MOD 810>; 762 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 763 status = "disabled"; 764 resets = <&cpg 810>; 765 766 ports { 767 #address-cells = <1>; 768 #size-cells = <0>; 769 770 port@1 { 771 #address-cells = <1>; 772 #size-cells = <0>; 773 774 reg = <1>; 775 776 vin1csi40: endpoint@2 { 777 reg = <2>; 778 remote-endpoint = <&csi40vin1>; 779 }; 780 }; 781 }; 782 }; 783 784 vin2: video@e6ef2000 { 785 compatible = "renesas,vin-r8a77980"; 786 reg = <0 0xe6ef2000 0 0x1000>; 787 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&cpg CPG_MOD 809>; 789 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 790 resets = <&cpg 809>; 791 status = "disabled"; 792 793 ports { 794 #address-cells = <1>; 795 #size-cells = <0>; 796 797 port@1 { 798 #address-cells = <1>; 799 #size-cells = <0>; 800 801 reg = <1>; 802 803 vin2csi40: endpoint@2 { 804 reg = <2>; 805 remote-endpoint = <&csi40vin2>; 806 }; 807 }; 808 }; 809 }; 810 811 vin3: video@e6ef3000 { 812 compatible = "renesas,vin-r8a77980"; 813 reg = <0 0xe6ef3000 0 0x1000>; 814 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 815 clocks = <&cpg CPG_MOD 808>; 816 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 817 resets = <&cpg 808>; 818 status = "disabled"; 819 820 ports { 821 #address-cells = <1>; 822 #size-cells = <0>; 823 824 port@1 { 825 #address-cells = <1>; 826 #size-cells = <0>; 827 828 reg = <1>; 829 830 vin3csi40: endpoint@2 { 831 reg = <2>; 832 remote-endpoint = <&csi40vin3>; 833 }; 834 }; 835 }; 836 }; 837 838 vin4: video@e6ef4000 { 839 compatible = "renesas,vin-r8a77980"; 840 reg = <0 0xe6ef4000 0 0x1000>; 841 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 842 clocks = <&cpg CPG_MOD 807>; 843 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 844 resets = <&cpg 807>; 845 status = "disabled"; 846 847 ports { 848 #address-cells = <1>; 849 #size-cells = <0>; 850 851 port@1 { 852 #address-cells = <1>; 853 #size-cells = <0>; 854 855 reg = <1>; 856 857 vin4csi41: endpoint@2 { 858 reg = <2>; 859 remote-endpoint = <&csi41vin4>; 860 }; 861 }; 862 }; 863 }; 864 865 vin5: video@e6ef5000 { 866 compatible = "renesas,vin-r8a77980"; 867 reg = <0 0xe6ef5000 0 0x1000>; 868 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&cpg CPG_MOD 806>; 870 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 871 resets = <&cpg 806>; 872 status = "disabled"; 873 874 ports { 875 #address-cells = <1>; 876 #size-cells = <0>; 877 878 port@1 { 879 #address-cells = <1>; 880 #size-cells = <0>; 881 882 reg = <1>; 883 884 vin5csi41: endpoint@2 { 885 reg = <2>; 886 remote-endpoint = <&csi41vin5>; 887 }; 888 }; 889 }; 890 }; 891 892 vin6: video@e6ef6000 { 893 compatible = "renesas,vin-r8a77980"; 894 reg = <0 0xe6ef6000 0 0x1000>; 895 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 896 clocks = <&cpg CPG_MOD 805>; 897 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 898 resets = <&cpg 805>; 899 status = "disabled"; 900 901 ports { 902 #address-cells = <1>; 903 #size-cells = <0>; 904 905 port@1 { 906 #address-cells = <1>; 907 #size-cells = <0>; 908 909 reg = <1>; 910 911 vin6csi41: endpoint@2 { 912 reg = <2>; 913 remote-endpoint = <&csi41vin6>; 914 }; 915 }; 916 }; 917 }; 918 919 vin7: video@e6ef7000 { 920 compatible = "renesas,vin-r8a77980"; 921 reg = <0 0xe6ef7000 0 0x1000>; 922 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 923 clocks = <&cpg CPG_MOD 804>; 924 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 925 resets = <&cpg 804>; 926 status = "disabled"; 927 928 ports { 929 #address-cells = <1>; 930 #size-cells = <0>; 931 932 port@1 { 933 #address-cells = <1>; 934 #size-cells = <0>; 935 936 reg = <1>; 937 938 vin7csi41: endpoint@2 { 939 reg = <2>; 940 remote-endpoint = <&csi41vin7>; 941 }; 942 }; 943 }; 944 }; 945 946 vin8: video@e6ef8000 { 947 compatible = "renesas,vin-r8a77980"; 948 reg = <0 0xe6ef8000 0 0x1000>; 949 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 950 clocks = <&cpg CPG_MOD 628>; 951 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 952 resets = <&cpg 628>; 953 status = "disabled"; 954 }; 955 956 vin9: video@e6ef9000 { 957 compatible = "renesas,vin-r8a77980"; 958 reg = <0 0xe6ef9000 0 0x1000>; 959 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&cpg CPG_MOD 627>; 961 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 962 resets = <&cpg 627>; 963 status = "disabled"; 964 }; 965 966 vin10: video@e6efa000 { 967 compatible = "renesas,vin-r8a77980"; 968 reg = <0 0xe6efa000 0 0x1000>; 969 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; 970 clocks = <&cpg CPG_MOD 625>; 971 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 972 resets = <&cpg 625>; 973 status = "disabled"; 974 }; 975 976 vin11: video@e6efb000 { 977 compatible = "renesas,vin-r8a77980"; 978 reg = <0 0xe6efb000 0 0x1000>; 979 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 980 clocks = <&cpg CPG_MOD 618>; 981 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 982 resets = <&cpg 618>; 983 status = "disabled"; 984 }; 985 986 vin12: video@e6efc000 { 987 compatible = "renesas,vin-r8a77980"; 988 reg = <0 0xe6efc000 0 0x1000>; 989 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 990 clocks = <&cpg CPG_MOD 612>; 991 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 992 resets = <&cpg 612>; 993 status = "disabled"; 994 }; 995 996 vin13: video@e6efd000 { 997 compatible = "renesas,vin-r8a77980"; 998 reg = <0 0xe6efd000 0 0x1000>; 999 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1000 clocks = <&cpg CPG_MOD 608>; 1001 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1002 resets = <&cpg 608>; 1003 status = "disabled"; 1004 }; 1005 1006 vin14: video@e6efe000 { 1007 compatible = "renesas,vin-r8a77980"; 1008 reg = <0 0xe6efe000 0 0x1000>; 1009 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; 1010 clocks = <&cpg CPG_MOD 605>; 1011 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1012 resets = <&cpg 605>; 1013 status = "disabled"; 1014 }; 1015 1016 vin15: video@e6eff000 { 1017 compatible = "renesas,vin-r8a77980"; 1018 reg = <0 0xe6eff000 0 0x1000>; 1019 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 1020 clocks = <&cpg CPG_MOD 604>; 1021 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1022 resets = <&cpg 604>; 1023 status = "disabled"; 1024 }; 1025 1026 dmac1: dma-controller@e7300000 { 1027 compatible = "renesas,dmac-r8a77980", 1028 "renesas,rcar-dmac"; 1029 reg = <0 0xe7300000 0 0x10000>; 1030 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 1031 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 1032 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 1033 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 1034 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 1035 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 1036 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 1037 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 1038 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 1039 GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 1040 GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 1041 GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 1042 GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 1043 GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 1044 GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 1045 GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 1046 GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1047 interrupt-names = "error", 1048 "ch0", "ch1", "ch2", "ch3", 1049 "ch4", "ch5", "ch6", "ch7", 1050 "ch8", "ch9", "ch10", "ch11", 1051 "ch12", "ch13", "ch14", "ch15"; 1052 clocks = <&cpg CPG_MOD 218>; 1053 clock-names = "fck"; 1054 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1055 resets = <&cpg 218>; 1056 #dma-cells = <1>; 1057 dma-channels = <16>; 1058 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 1059 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 1060 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 1061 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 1062 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 1063 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 1064 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 1065 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 1066 }; 1067 1068 dmac2: dma-controller@e7310000 { 1069 compatible = "renesas,dmac-r8a77980", 1070 "renesas,rcar-dmac"; 1071 reg = <0 0xe7310000 0 0x10000>; 1072 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 1073 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 1074 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 1075 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 1076 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 1077 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 1078 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 1079 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 1080 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 1081 GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 1082 GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 1083 GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 1084 GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 1085 GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 1086 GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 1087 GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 1088 GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1089 interrupt-names = "error", 1090 "ch0", "ch1", "ch2", "ch3", 1091 "ch4", "ch5", "ch6", "ch7", 1092 "ch8", "ch9", "ch10", "ch11", 1093 "ch12", "ch13", "ch14", "ch15"; 1094 clocks = <&cpg CPG_MOD 217>; 1095 clock-names = "fck"; 1096 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1097 resets = <&cpg 217>; 1098 #dma-cells = <1>; 1099 dma-channels = <16>; 1100 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 1101 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 1102 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 1103 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 1104 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 1105 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 1106 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 1107 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 1108 }; 1109 1110 gether: ethernet@e7400000 { 1111 compatible = "renesas,gether-r8a77980"; 1112 reg = <0 0xe7400000 0 0x1000>; 1113 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1114 clocks = <&cpg CPG_MOD 813>; 1115 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1116 resets = <&cpg 813>; 1117 #address-cells = <1>; 1118 #size-cells = <0>; 1119 status = "disabled"; 1120 }; 1121 1122 ipmmu_ds1: mmu@e7740000 { 1123 compatible = "renesas,ipmmu-r8a77980"; 1124 reg = <0 0xe7740000 0 0x1000>; 1125 renesas,ipmmu-main = <&ipmmu_mm 0>; 1126 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1127 #iommu-cells = <1>; 1128 }; 1129 1130 ipmmu_ir: mmu@ff8b0000 { 1131 compatible = "renesas,ipmmu-r8a77980"; 1132 reg = <0 0xff8b0000 0 0x1000>; 1133 renesas,ipmmu-main = <&ipmmu_mm 3>; 1134 power-domains = <&sysc R8A77980_PD_A3IR>; 1135 #iommu-cells = <1>; 1136 }; 1137 1138 ipmmu_mm: mmu@e67b0000 { 1139 compatible = "renesas,ipmmu-r8a77980"; 1140 reg = <0 0xe67b0000 0 0x1000>; 1141 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1143 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1144 #iommu-cells = <1>; 1145 }; 1146 1147 ipmmu_rt: mmu@ffc80000 { 1148 compatible = "renesas,ipmmu-r8a77980"; 1149 reg = <0 0xffc80000 0 0x1000>; 1150 renesas,ipmmu-main = <&ipmmu_mm 10>; 1151 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1152 #iommu-cells = <1>; 1153 }; 1154 1155 ipmmu_vc0: mmu@fe6b0000 { 1156 compatible = "renesas,ipmmu-r8a77980"; 1157 reg = <0 0xfe6b0000 0 0x1000>; 1158 renesas,ipmmu-main = <&ipmmu_mm 12>; 1159 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1160 #iommu-cells = <1>; 1161 }; 1162 1163 ipmmu_vi0: mmu@febd0000 { 1164 compatible = "renesas,ipmmu-r8a77980"; 1165 reg = <0 0xfebd0000 0 0x1000>; 1166 renesas,ipmmu-main = <&ipmmu_mm 14>; 1167 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1168 #iommu-cells = <1>; 1169 }; 1170 1171 ipmmu_vip0: mmu@e7b00000 { 1172 compatible = "renesas,ipmmu-r8a77980"; 1173 reg = <0 0xe7b00000 0 0x1000>; 1174 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1175 #iommu-cells = <1>; 1176 }; 1177 1178 ipmmu_vip1: mmu@e7960000 { 1179 compatible = "renesas,ipmmu-r8a77980"; 1180 reg = <0 0xe7960000 0 0x1000>; 1181 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1182 #iommu-cells = <1>; 1183 }; 1184 1185 mmc0: mmc@ee140000 { 1186 compatible = "renesas,sdhi-r8a77980", 1187 "renesas,rcar-gen3-sdhi"; 1188 reg = <0 0xee140000 0 0x2000>; 1189 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1190 clocks = <&cpg CPG_MOD 314>; 1191 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1192 resets = <&cpg 314>; 1193 max-frequency = <200000000>; 1194 status = "disabled"; 1195 }; 1196 1197 gic: interrupt-controller@f1010000 { 1198 compatible = "arm,gic-400"; 1199 #interrupt-cells = <3>; 1200 #address-cells = <0>; 1201 interrupt-controller; 1202 reg = <0x0 0xf1010000 0 0x1000>, 1203 <0x0 0xf1020000 0 0x20000>, 1204 <0x0 0xf1040000 0 0x20000>, 1205 <0x0 0xf1060000 0 0x20000>; 1206 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 1207 IRQ_TYPE_LEVEL_HIGH)>; 1208 clocks = <&cpg CPG_MOD 408>; 1209 clock-names = "clk"; 1210 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1211 resets = <&cpg 408>; 1212 }; 1213 1214 pciec: pcie@fe000000 { 1215 compatible = "renesas,pcie-r8a77980", 1216 "renesas,pcie-rcar-gen3"; 1217 reg = <0 0xfe000000 0 0x80000>; 1218 #address-cells = <3>; 1219 #size-cells = <2>; 1220 bus-range = <0x00 0xff>; 1221 device_type = "pci"; 1222 ranges = < 1223 0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000 1224 0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000 1225 0x02000000 0 0x30000000 0 0x30000000 0 0x8000000 1226 0x42000000 0 0x38000000 0 0x38000000 0 0x8000000 1227 >; 1228 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1229 0 0x80000000>; 1230 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1233 #interrupt-cells = <1>; 1234 interrupt-map-mask = <0 0 0 0>; 1235 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 1236 IRQ_TYPE_LEVEL_HIGH>; 1237 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 1238 clock-names = "pcie", "pcie_bus"; 1239 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1240 resets = <&cpg 319>; 1241 phys = <&pcie_phy>; 1242 phy-names = "pcie"; 1243 status = "disabled"; 1244 }; 1245 1246 vspd0: vsp@fea20000 { 1247 compatible = "renesas,vsp2"; 1248 reg = <0 0xfea20000 0 0x5000>; 1249 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1250 clocks = <&cpg CPG_MOD 623>; 1251 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1252 resets = <&cpg 623>; 1253 renesas,fcp = <&fcpvd0>; 1254 }; 1255 1256 fcpvd0: fcp@fea27000 { 1257 compatible = "renesas,fcpv"; 1258 reg = <0 0xfea27000 0 0x200>; 1259 clocks = <&cpg CPG_MOD 603>; 1260 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1261 resets = <&cpg 603>; 1262 }; 1263 1264 csi40: csi2@feaa0000 { 1265 compatible = "renesas,r8a77980-csi2"; 1266 reg = <0 0xfeaa0000 0 0x10000>; 1267 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1268 clocks = <&cpg CPG_MOD 716>; 1269 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1270 resets = <&cpg 716>; 1271 status = "disabled"; 1272 1273 ports { 1274 #address-cells = <1>; 1275 #size-cells = <0>; 1276 1277 port@1 { 1278 #address-cells = <1>; 1279 #size-cells = <0>; 1280 1281 reg = <1>; 1282 1283 csi40vin0: endpoint@0 { 1284 reg = <0>; 1285 remote-endpoint = <&vin0csi40>; 1286 }; 1287 csi40vin1: endpoint@1 { 1288 reg = <1>; 1289 remote-endpoint = <&vin1csi40>; 1290 }; 1291 csi40vin2: endpoint@2 { 1292 reg = <2>; 1293 remote-endpoint = <&vin2csi40>; 1294 }; 1295 csi40vin3: endpoint@3 { 1296 reg = <3>; 1297 remote-endpoint = <&vin3csi40>; 1298 }; 1299 }; 1300 }; 1301 }; 1302 1303 csi41: csi2@feab0000 { 1304 compatible = "renesas,r8a77980-csi2"; 1305 reg = <0 0xfeab0000 0 0x10000>; 1306 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1307 clocks = <&cpg CPG_MOD 715>; 1308 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1309 resets = <&cpg 715>; 1310 status = "disabled"; 1311 1312 ports { 1313 #address-cells = <1>; 1314 #size-cells = <0>; 1315 1316 port@1 { 1317 #address-cells = <1>; 1318 #size-cells = <0>; 1319 1320 reg = <1>; 1321 1322 csi41vin4: endpoint@0 { 1323 reg = <0>; 1324 remote-endpoint = <&vin4csi41>; 1325 }; 1326 csi41vin5: endpoint@1 { 1327 reg = <1>; 1328 remote-endpoint = <&vin5csi41>; 1329 }; 1330 csi41vin6: endpoint@2 { 1331 reg = <2>; 1332 remote-endpoint = <&vin6csi41>; 1333 }; 1334 csi41vin7: endpoint@3 { 1335 reg = <3>; 1336 remote-endpoint = <&vin7csi41>; 1337 }; 1338 }; 1339 }; 1340 }; 1341 1342 du: display@feb00000 { 1343 compatible = "renesas,du-r8a77980", 1344 "renesas,du-r8a77970"; 1345 reg = <0 0xfeb00000 0 0x80000>; 1346 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1347 clocks = <&cpg CPG_MOD 724>; 1348 clock-names = "du.0"; 1349 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1350 resets = <&cpg 724>; 1351 vsps = <&vspd0>; 1352 status = "disabled"; 1353 1354 ports { 1355 #address-cells = <1>; 1356 #size-cells = <0>; 1357 1358 port@0 { 1359 reg = <0>; 1360 du_out_rgb: endpoint { 1361 }; 1362 }; 1363 1364 port@1 { 1365 reg = <1>; 1366 du_out_lvds0: endpoint { 1367 remote-endpoint = <&lvds0_in>; 1368 }; 1369 }; 1370 }; 1371 }; 1372 1373 lvds0: lvds-encoder@feb90000 { 1374 compatible = "renesas,r8a77980-lvds"; 1375 reg = <0 0xfeb90000 0 0x14>; 1376 clocks = <&cpg CPG_MOD 727>; 1377 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1378 resets = <&cpg 727>; 1379 status = "disabled"; 1380 1381 ports { 1382 #address-cells = <1>; 1383 #size-cells = <0>; 1384 1385 port@0 { 1386 reg = <0>; 1387 lvds0_in: endpoint { 1388 remote-endpoint = 1389 <&du_out_lvds0>; 1390 }; 1391 }; 1392 1393 port@1 { 1394 reg = <1>; 1395 lvds0_out: endpoint { 1396 }; 1397 }; 1398 }; 1399 }; 1400 1401 prr: chipid@fff00044 { 1402 compatible = "renesas,prr"; 1403 reg = <0 0xfff00044 0 4>; 1404 }; 1405 }; 1406 1407 timer { 1408 compatible = "arm,armv8-timer"; 1409 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 1410 IRQ_TYPE_LEVEL_LOW)>, 1411 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 1412 IRQ_TYPE_LEVEL_LOW)>, 1413 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 1414 IRQ_TYPE_LEVEL_LOW)>, 1415 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 1416 IRQ_TYPE_LEVEL_LOW)>; 1417 }; 1418}; 1419