1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car V3H (R8A77980) SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8 9#include <dt-bindings/clock/r8a77980-cpg-mssr.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/r8a77980-sysc.h> 13 14/ { 15 compatible = "renesas,r8a77980"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 i2c0 = &i2c0; 21 i2c1 = &i2c1; 22 i2c2 = &i2c2; 23 i2c3 = &i2c3; 24 i2c4 = &i2c4; 25 i2c5 = &i2c5; 26 }; 27 28 /* External CAN clock - to be overridden by boards that provide it */ 29 can_clk: can { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <0>; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 a53_0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53", "arm,armv8"; 42 reg = <0>; 43 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 44 power-domains = <&sysc R8A77980_PD_CA53_CPU0>; 45 next-level-cache = <&L2_CA53>; 46 enable-method = "psci"; 47 }; 48 49 a53_1: cpu@1 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53", "arm,armv8"; 52 reg = <1>; 53 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 54 power-domains = <&sysc R8A77980_PD_CA53_CPU1>; 55 next-level-cache = <&L2_CA53>; 56 enable-method = "psci"; 57 }; 58 59 a53_2: cpu@2 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53", "arm,armv8"; 62 reg = <2>; 63 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 64 power-domains = <&sysc R8A77980_PD_CA53_CPU2>; 65 next-level-cache = <&L2_CA53>; 66 enable-method = "psci"; 67 }; 68 69 a53_3: cpu@3 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53", "arm,armv8"; 72 reg = <3>; 73 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 74 power-domains = <&sysc R8A77980_PD_CA53_CPU3>; 75 next-level-cache = <&L2_CA53>; 76 enable-method = "psci"; 77 }; 78 79 L2_CA53: cache-controller { 80 compatible = "cache"; 81 power-domains = <&sysc R8A77980_PD_CA53_SCU>; 82 cache-unified; 83 cache-level = <2>; 84 }; 85 }; 86 87 extal_clk: extal { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 /* This value must be overridden by the board */ 91 clock-frequency = <0>; 92 }; 93 94 extalr_clk: extalr { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 /* This value must be overridden by the board */ 98 clock-frequency = <0>; 99 }; 100 101 pmu_a53 { 102 compatible = "arm,cortex-a53-pmu"; 103 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 104 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 105 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 106 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 107 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 108 }; 109 110 psci { 111 compatible = "arm,psci-1.0", "arm,psci-0.2"; 112 method = "smc"; 113 }; 114 115 /* External SCIF clock - to be overridden by boards that provide it */ 116 scif_clk: scif { 117 compatible = "fixed-clock"; 118 #clock-cells = <0>; 119 clock-frequency = <0>; 120 }; 121 122 soc { 123 compatible = "simple-bus"; 124 interrupt-parent = <&gic>; 125 126 #address-cells = <2>; 127 #size-cells = <2>; 128 ranges; 129 130 rwdt: watchdog@e6020000 { 131 compatible = "renesas,r8a77980-wdt", 132 "renesas,rcar-gen3-wdt"; 133 reg = <0 0xe6020000 0 0x0c>; 134 clocks = <&cpg CPG_MOD 402>; 135 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 136 resets = <&cpg 402>; 137 status = "disabled"; 138 }; 139 140 gpio0: gpio@e6050000 { 141 compatible = "renesas,gpio-r8a77980", 142 "renesas,rcar-gen3-gpio"; 143 reg = <0 0xe6050000 0 0x50>; 144 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 145 #gpio-cells = <2>; 146 gpio-controller; 147 gpio-ranges = <&pfc 0 0 22>; 148 #interrupt-cells = <2>; 149 interrupt-controller; 150 clocks = <&cpg CPG_MOD 912>; 151 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 152 resets = <&cpg 912>; 153 }; 154 155 gpio1: gpio@e6051000 { 156 compatible = "renesas,gpio-r8a77980", 157 "renesas,rcar-gen3-gpio"; 158 reg = <0 0xe6051000 0 0x50>; 159 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 160 #gpio-cells = <2>; 161 gpio-controller; 162 gpio-ranges = <&pfc 0 32 28>; 163 #interrupt-cells = <2>; 164 interrupt-controller; 165 clocks = <&cpg CPG_MOD 911>; 166 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 167 resets = <&cpg 911>; 168 }; 169 170 gpio2: gpio@e6052000 { 171 compatible = "renesas,gpio-r8a77980", 172 "renesas,rcar-gen3-gpio"; 173 reg = <0 0xe6052000 0 0x50>; 174 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 175 #gpio-cells = <2>; 176 gpio-controller; 177 gpio-ranges = <&pfc 0 64 30>; 178 #interrupt-cells = <2>; 179 interrupt-controller; 180 clocks = <&cpg CPG_MOD 910>; 181 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 182 resets = <&cpg 910>; 183 }; 184 185 gpio3: gpio@e6053000 { 186 compatible = "renesas,gpio-r8a77980", 187 "renesas,rcar-gen3-gpio"; 188 reg = <0 0xe6053000 0 0x50>; 189 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 190 #gpio-cells = <2>; 191 gpio-controller; 192 gpio-ranges = <&pfc 0 96 17>; 193 #interrupt-cells = <2>; 194 interrupt-controller; 195 clocks = <&cpg CPG_MOD 909>; 196 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 197 resets = <&cpg 909>; 198 }; 199 200 gpio4: gpio@e6054000 { 201 compatible = "renesas,gpio-r8a77980", 202 "renesas,rcar-gen3-gpio"; 203 reg = <0 0xe6054000 0 0x50>; 204 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 205 #gpio-cells = <2>; 206 gpio-controller; 207 gpio-ranges = <&pfc 0 128 25>; 208 #interrupt-cells = <2>; 209 interrupt-controller; 210 clocks = <&cpg CPG_MOD 908>; 211 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 212 resets = <&cpg 908>; 213 }; 214 215 gpio5: gpio@e6055000 { 216 compatible = "renesas,gpio-r8a77980", 217 "renesas,rcar-gen3-gpio"; 218 reg = <0 0xe6055000 0 0x50>; 219 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 220 #gpio-cells = <2>; 221 gpio-controller; 222 gpio-ranges = <&pfc 0 160 15>; 223 #interrupt-cells = <2>; 224 interrupt-controller; 225 clocks = <&cpg CPG_MOD 907>; 226 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 227 resets = <&cpg 907>; 228 }; 229 230 pfc: pin-controller@e6060000 { 231 compatible = "renesas,pfc-r8a77980"; 232 reg = <0 0xe6060000 0 0x50c>; 233 }; 234 235 cpg: clock-controller@e6150000 { 236 compatible = "renesas,r8a77980-cpg-mssr"; 237 reg = <0 0xe6150000 0 0x1000>; 238 clocks = <&extal_clk>, <&extalr_clk>; 239 clock-names = "extal", "extalr"; 240 #clock-cells = <2>; 241 #power-domain-cells = <0>; 242 #reset-cells = <1>; 243 }; 244 245 rst: reset-controller@e6160000 { 246 compatible = "renesas,r8a77980-rst"; 247 reg = <0 0xe6160000 0 0x200>; 248 }; 249 250 sysc: system-controller@e6180000 { 251 compatible = "renesas,r8a77980-sysc"; 252 reg = <0 0xe6180000 0 0x440>; 253 #power-domain-cells = <1>; 254 }; 255 256 intc_ex: interrupt-controller@e61c0000 { 257 compatible = "renesas,intc-ex-r8a77980", "renesas,irqc"; 258 #interrupt-cells = <2>; 259 interrupt-controller; 260 reg = <0 0xe61c0000 0 0x200>; 261 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 262 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 263 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 264 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 265 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 266 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&cpg CPG_MOD 407>; 268 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 269 resets = <&cpg 407>; 270 }; 271 272 i2c0: i2c@e6500000 { 273 compatible = "renesas,i2c-r8a77980", 274 "renesas,rcar-gen3-i2c"; 275 reg = <0 0xe6500000 0 0x40>; 276 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&cpg CPG_MOD 931>; 278 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 279 resets = <&cpg 931>; 280 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 281 <&dmac2 0x91>, <&dmac2 0x90>; 282 dma-names = "tx", "rx", "tx", "rx"; 283 i2c-scl-internal-delay-ns = <6>; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 status = "disabled"; 287 }; 288 289 i2c1: i2c@e6508000 { 290 compatible = "renesas,i2c-r8a77980", 291 "renesas,rcar-gen3-i2c"; 292 reg = <0 0xe6508000 0 0x40>; 293 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&cpg CPG_MOD 930>; 295 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 296 resets = <&cpg 930>; 297 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 298 <&dmac2 0x93>, <&dmac2 0x92>; 299 dma-names = "tx", "rx", "tx", "rx"; 300 i2c-scl-internal-delay-ns = <6>; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 status = "disabled"; 304 }; 305 306 i2c2: i2c@e6510000 { 307 compatible = "renesas,i2c-r8a77980", 308 "renesas,rcar-gen3-i2c"; 309 reg = <0 0xe6510000 0 0x40>; 310 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&cpg CPG_MOD 929>; 312 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 313 resets = <&cpg 929>; 314 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 315 <&dmac2 0x95>, <&dmac2 0x94>; 316 dma-names = "tx", "rx", "tx", "rx"; 317 i2c-scl-internal-delay-ns = <6>; 318 #address-cells = <1>; 319 #size-cells = <0>; 320 status = "disabled"; 321 }; 322 323 i2c3: i2c@e66d0000 { 324 compatible = "renesas,i2c-r8a77980", 325 "renesas,rcar-gen3-i2c"; 326 reg = <0 0xe66d0000 0 0x40>; 327 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&cpg CPG_MOD 928>; 329 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 330 resets = <&cpg 928>; 331 i2c-scl-internal-delay-ns = <6>; 332 #address-cells = <1>; 333 #size-cells = <0>; 334 status = "disabled"; 335 }; 336 337 i2c4: i2c@e66d8000 { 338 compatible = "renesas,i2c-r8a77980", 339 "renesas,rcar-gen3-i2c"; 340 reg = <0 0xe66d8000 0 0x40>; 341 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&cpg CPG_MOD 927>; 343 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 344 resets = <&cpg 927>; 345 i2c-scl-internal-delay-ns = <6>; 346 #address-cells = <1>; 347 #size-cells = <0>; 348 status = "disabled"; 349 }; 350 351 i2c5: i2c@e66e0000 { 352 compatible = "renesas,i2c-r8a77980", 353 "renesas,rcar-gen3-i2c"; 354 reg = <0 0xe66e0000 0 0x40>; 355 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&cpg CPG_MOD 919>; 357 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 358 resets = <&cpg 919>; 359 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>, 360 <&dmac2 0x9b>, <&dmac2 0x9a>; 361 dma-names = "tx", "rx", "tx", "rx"; 362 i2c-scl-internal-delay-ns = <6>; 363 #address-cells = <1>; 364 #size-cells = <0>; 365 status = "disabled"; 366 }; 367 368 hscif0: serial@e6540000 { 369 compatible = "renesas,hscif-r8a77980", 370 "renesas,rcar-gen3-hscif", 371 "renesas,hscif"; 372 reg = <0 0xe6540000 0 0x60>; 373 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&cpg CPG_MOD 520>, 375 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 376 <&scif_clk>; 377 clock-names = "fck", "brg_int", "scif_clk"; 378 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 379 <&dmac2 0x31>, <&dmac2 0x30>; 380 dma-names = "tx", "rx", "tx", "rx"; 381 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 382 resets = <&cpg 520>; 383 status = "disabled"; 384 }; 385 386 hscif1: serial@e6550000 { 387 compatible = "renesas,hscif-r8a77980", 388 "renesas,rcar-gen3-hscif", 389 "renesas,hscif"; 390 reg = <0 0xe6550000 0 0x60>; 391 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&cpg CPG_MOD 519>, 393 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 394 <&scif_clk>; 395 clock-names = "fck", "brg_int", "scif_clk"; 396 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 397 <&dmac2 0x33>, <&dmac2 0x32>; 398 dma-names = "tx", "rx", "tx", "rx"; 399 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 400 resets = <&cpg 519>; 401 status = "disabled"; 402 }; 403 404 hscif2: serial@e6560000 { 405 compatible = "renesas,hscif-r8a77980", 406 "renesas,rcar-gen3-hscif", 407 "renesas,hscif"; 408 reg = <0 0xe6560000 0 0x60>; 409 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&cpg CPG_MOD 518>, 411 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 412 <&scif_clk>; 413 clock-names = "fck", "brg_int", "scif_clk"; 414 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 415 <&dmac2 0x35>, <&dmac2 0x34>; 416 dma-names = "tx", "rx", "tx", "rx"; 417 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 418 resets = <&cpg 518>; 419 status = "disabled"; 420 }; 421 422 hscif3: serial@e66a0000 { 423 compatible = "renesas,hscif-r8a77980", 424 "renesas,rcar-gen3-hscif", 425 "renesas,hscif"; 426 reg = <0 0xe66a0000 0 0x60>; 427 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&cpg CPG_MOD 517>, 429 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 430 <&scif_clk>; 431 clock-names = "fck", "brg_int", "scif_clk"; 432 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 433 <&dmac2 0x37>, <&dmac2 0x36>; 434 dma-names = "tx", "rx", "tx", "rx"; 435 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 436 resets = <&cpg 517>; 437 status = "disabled"; 438 }; 439 440 canfd: can@e66c0000 { 441 compatible = "renesas,r8a77980-canfd", 442 "renesas,rcar-gen3-canfd"; 443 reg = <0 0xe66c0000 0 0x8000>; 444 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&cpg CPG_MOD 914>, 447 <&cpg CPG_CORE R8A77980_CLK_CANFD>, 448 <&can_clk>; 449 clock-names = "fck", "canfd", "can_clk"; 450 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>; 451 assigned-clock-rates = <40000000>; 452 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 453 resets = <&cpg 914>; 454 status = "disabled"; 455 456 channel0 { 457 status = "disabled"; 458 }; 459 460 channel1 { 461 status = "disabled"; 462 }; 463 }; 464 465 avb: ethernet@e6800000 { 466 compatible = "renesas,etheravb-r8a77980", 467 "renesas,etheravb-rcar-gen3"; 468 reg = <0 0xe6800000 0 0x800>; 469 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 494 interrupt-names = "ch0", "ch1", "ch2", "ch3", 495 "ch4", "ch5", "ch6", "ch7", 496 "ch8", "ch9", "ch10", "ch11", 497 "ch12", "ch13", "ch14", "ch15", 498 "ch16", "ch17", "ch18", "ch19", 499 "ch20", "ch21", "ch22", "ch23", 500 "ch24"; 501 clocks = <&cpg CPG_MOD 812>; 502 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 503 resets = <&cpg 812>; 504 phy-mode = "rgmii"; 505 #address-cells = <1>; 506 #size-cells = <0>; 507 status = "disabled"; 508 }; 509 510 scif0: serial@e6e60000 { 511 compatible = "renesas,scif-r8a77980", 512 "renesas,rcar-gen3-scif", 513 "renesas,scif"; 514 reg = <0 0xe6e60000 0 0x40>; 515 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&cpg CPG_MOD 207>, 517 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 518 <&scif_clk>; 519 clock-names = "fck", "brg_int", "scif_clk"; 520 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 521 <&dmac2 0x51>, <&dmac2 0x50>; 522 dma-names = "tx", "rx", "tx", "rx"; 523 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 524 resets = <&cpg 207>; 525 status = "disabled"; 526 }; 527 528 scif1: serial@e6e68000 { 529 compatible = "renesas,scif-r8a77980", 530 "renesas,rcar-gen3-scif", 531 "renesas,scif"; 532 reg = <0 0xe6e68000 0 0x40>; 533 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&cpg CPG_MOD 206>, 535 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 536 <&scif_clk>; 537 clock-names = "fck", "brg_int", "scif_clk"; 538 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 539 <&dmac2 0x53>, <&dmac2 0x52>; 540 dma-names = "tx", "rx", "tx", "rx"; 541 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 542 resets = <&cpg 206>; 543 status = "disabled"; 544 }; 545 546 scif3: serial@e6c50000 { 547 compatible = "renesas,scif-r8a77980", 548 "renesas,rcar-gen3-scif", 549 "renesas,scif"; 550 reg = <0 0xe6c50000 0 0x40>; 551 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&cpg CPG_MOD 204>, 553 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 554 <&scif_clk>; 555 clock-names = "fck", "brg_int", "scif_clk"; 556 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 557 <&dmac2 0x57>, <&dmac2 0x56>; 558 dma-names = "tx", "rx", "tx", "rx"; 559 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 560 resets = <&cpg 204>; 561 status = "disabled"; 562 }; 563 564 scif4: serial@e6c40000 { 565 compatible = "renesas,scif-r8a77980", 566 "renesas,rcar-gen3-scif", 567 "renesas,scif"; 568 reg = <0 0xe6c40000 0 0x40>; 569 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&cpg CPG_MOD 203>, 571 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 572 <&scif_clk>; 573 clock-names = "fck", "brg_int", "scif_clk"; 574 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 575 <&dmac2 0x59>, <&dmac2 0x58>; 576 dma-names = "tx", "rx", "tx", "rx"; 577 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 578 resets = <&cpg 203>; 579 status = "disabled"; 580 }; 581 582 dmac1: dma-controller@e7300000 { 583 compatible = "renesas,dmac-r8a77980", 584 "renesas,rcar-dmac"; 585 reg = <0 0xe7300000 0 0x10000>; 586 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 587 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 588 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 589 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 590 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 591 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 592 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 593 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 594 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 595 GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 596 GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 597 GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 598 GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 599 GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 600 GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 601 GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 602 GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 603 interrupt-names = "error", 604 "ch0", "ch1", "ch2", "ch3", 605 "ch4", "ch5", "ch6", "ch7", 606 "ch8", "ch9", "ch10", "ch11", 607 "ch12", "ch13", "ch14", "ch15"; 608 clocks = <&cpg CPG_MOD 218>; 609 clock-names = "fck"; 610 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 611 resets = <&cpg 218>; 612 #dma-cells = <1>; 613 dma-channels = <16>; 614 }; 615 616 dmac2: dma-controller@e7310000 { 617 compatible = "renesas,dmac-r8a77980", 618 "renesas,rcar-dmac"; 619 reg = <0 0xe7310000 0 0x10000>; 620 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 621 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 622 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 623 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 624 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 625 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 626 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 627 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 628 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 629 GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 630 GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 631 GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 632 GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 633 GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 634 GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 635 GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 636 GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 637 interrupt-names = "error", 638 "ch0", "ch1", "ch2", "ch3", 639 "ch4", "ch5", "ch6", "ch7", 640 "ch8", "ch9", "ch10", "ch11", 641 "ch12", "ch13", "ch14", "ch15"; 642 clocks = <&cpg CPG_MOD 217>; 643 clock-names = "fck"; 644 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 645 resets = <&cpg 217>; 646 #dma-cells = <1>; 647 dma-channels = <16>; 648 }; 649 650 gether: ethernet@e7400000 { 651 compatible = "renesas,gether-r8a77980"; 652 reg = <0 0xe7400000 0 0x1000>; 653 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&cpg CPG_MOD 813>; 655 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 656 resets = <&cpg 813>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 status = "disabled"; 660 }; 661 662 ipmmu_ds1: mmu@e7740000 { 663 compatible = "renesas,ipmmu-r8a77980"; 664 reg = <0 0xe7740000 0 0x1000>; 665 renesas,ipmmu-main = <&ipmmu_mm 0>; 666 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 667 #iommu-cells = <1>; 668 }; 669 670 ipmmu_ir: mmu@ff8b0000 { 671 compatible = "renesas,ipmmu-r8a77980"; 672 reg = <0 0xff8b0000 0 0x1000>; 673 renesas,ipmmu-main = <&ipmmu_mm 3>; 674 power-domains = <&sysc R8A77980_PD_A3IR>; 675 #iommu-cells = <1>; 676 }; 677 678 ipmmu_mm: mmu@e67b0000 { 679 compatible = "renesas,ipmmu-r8a77980"; 680 reg = <0 0xe67b0000 0 0x1000>; 681 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 683 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 684 #iommu-cells = <1>; 685 }; 686 687 ipmmu_rt: mmu@ffc80000 { 688 compatible = "renesas,ipmmu-r8a77980"; 689 reg = <0 0xffc80000 0 0x1000>; 690 renesas,ipmmu-main = <&ipmmu_mm 10>; 691 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 692 #iommu-cells = <1>; 693 }; 694 695 ipmmu_vc0: mmu@fe6b0000 { 696 compatible = "renesas,ipmmu-r8a77980"; 697 reg = <0 0xfe6b0000 0 0x1000>; 698 renesas,ipmmu-main = <&ipmmu_mm 12>; 699 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 700 #iommu-cells = <1>; 701 }; 702 703 ipmmu_vi0: mmu@febd0000 { 704 compatible = "renesas,ipmmu-r8a77980"; 705 reg = <0 0xfebd0000 0 0x1000>; 706 renesas,ipmmu-main = <&ipmmu_mm 14>; 707 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 708 #iommu-cells = <1>; 709 }; 710 711 ipmmu_vip0: mmu@e7b00000 { 712 compatible = "renesas,ipmmu-r8a77980"; 713 reg = <0 0xe7b00000 0 0x1000>; 714 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 715 #iommu-cells = <1>; 716 }; 717 718 ipmmu_vip1: mmu@e7960000 { 719 compatible = "renesas,ipmmu-r8a77980"; 720 reg = <0 0xe7960000 0 0x1000>; 721 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 722 #iommu-cells = <1>; 723 }; 724 725 mmc0: mmc@ee140000 { 726 compatible = "renesas,sdhi-r8a77980", 727 "renesas,rcar-gen3-sdhi"; 728 reg = <0 0xee140000 0 0x2000>; 729 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&cpg CPG_MOD 314>; 731 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 732 resets = <&cpg 314>; 733 max-frequency = <200000000>; 734 status = "disabled"; 735 }; 736 737 gic: interrupt-controller@f1010000 { 738 compatible = "arm,gic-400"; 739 #interrupt-cells = <3>; 740 #address-cells = <0>; 741 interrupt-controller; 742 reg = <0x0 0xf1010000 0 0x1000>, 743 <0x0 0xf1020000 0 0x20000>, 744 <0x0 0xf1040000 0 0x20000>, 745 <0x0 0xf1060000 0 0x20000>; 746 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 747 IRQ_TYPE_LEVEL_HIGH)>; 748 clocks = <&cpg CPG_MOD 408>; 749 clock-names = "clk"; 750 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 751 resets = <&cpg 408>; 752 }; 753 754 vspd0: vsp@fea20000 { 755 compatible = "renesas,vsp2"; 756 reg = <0 0xfea20000 0 0x5000>; 757 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&cpg CPG_MOD 623>; 759 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 760 resets = <&cpg 623>; 761 renesas,fcp = <&fcpvd0>; 762 }; 763 764 fcpvd0: fcp@fea27000 { 765 compatible = "renesas,fcpv"; 766 reg = <0 0xfea27000 0 0x200>; 767 clocks = <&cpg CPG_MOD 603>; 768 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 769 resets = <&cpg 603>; 770 }; 771 772 du: display@feb00000 { 773 compatible = "renesas,du-r8a77980", 774 "renesas,du-r8a77970"; 775 reg = <0 0xfeb00000 0 0x80000>; 776 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 777 clocks = <&cpg CPG_MOD 724>; 778 clock-names = "du.0"; 779 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 780 resets = <&cpg 724>; 781 vsps = <&vspd0>; 782 status = "disabled"; 783 784 ports { 785 #address-cells = <1>; 786 #size-cells = <0>; 787 788 port@0 { 789 reg = <0>; 790 du_out_rgb: endpoint { 791 }; 792 }; 793 794 port@1 { 795 reg = <1>; 796 du_out_lvds0: endpoint { 797 remote-endpoint = <&lvds0_in>; 798 }; 799 }; 800 }; 801 }; 802 803 lvds0: lvds-encoder@feb90000 { 804 compatible = "renesas,r8a77980-lvds"; 805 reg = <0 0xfeb90000 0 0x14>; 806 clocks = <&cpg CPG_MOD 727>; 807 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 808 resets = <&cpg 727>; 809 status = "disabled"; 810 811 ports { 812 #address-cells = <1>; 813 #size-cells = <0>; 814 815 port@0 { 816 reg = <0>; 817 lvds0_in: endpoint { 818 remote-endpoint = 819 <&du_out_lvds0>; 820 }; 821 }; 822 823 port@1 { 824 reg = <1>; 825 lvds0_out: endpoint { 826 }; 827 }; 828 }; 829 }; 830 831 prr: chipid@fff00044 { 832 compatible = "renesas,prr"; 833 reg = <0 0xfff00044 0 4>; 834 }; 835 }; 836 837 timer { 838 compatible = "arm,armv8-timer"; 839 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 840 IRQ_TYPE_LEVEL_LOW)>, 841 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 842 IRQ_TYPE_LEVEL_LOW)>, 843 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 844 IRQ_TYPE_LEVEL_LOW)>, 845 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 846 IRQ_TYPE_LEVEL_LOW)>; 847 }; 848}; 849