1b9edbce9SSergei Shtylyov// SPDX-License-Identifier: GPL-2.0 2b9edbce9SSergei Shtylyov/* 3b9edbce9SSergei Shtylyov * Device Tree Source for the Condor board 4b9edbce9SSergei Shtylyov * 5b9edbce9SSergei Shtylyov * Copyright (C) 2018 Renesas Electronics Corp. 6b9edbce9SSergei Shtylyov * Copyright (C) 2018 Cogent Embedded, Inc. 7b9edbce9SSergei Shtylyov */ 8b9edbce9SSergei Shtylyov 9b9edbce9SSergei Shtylyov/dts-v1/; 10b9edbce9SSergei Shtylyov#include "r8a77980.dtsi" 11b9edbce9SSergei Shtylyov 12b9edbce9SSergei Shtylyov/ { 13b9edbce9SSergei Shtylyov model = "Renesas Condor board based on r8a77980"; 14b9edbce9SSergei Shtylyov compatible = "renesas,condor", "renesas,r8a77980"; 15b9edbce9SSergei Shtylyov 16b9edbce9SSergei Shtylyov aliases { 17b9edbce9SSergei Shtylyov serial0 = &scif0; 188091788fSSergei Shtylyov ethernet0 = &avb; 19b9edbce9SSergei Shtylyov }; 20b9edbce9SSergei Shtylyov 21b9edbce9SSergei Shtylyov chosen { 22b9edbce9SSergei Shtylyov stdout-path = "serial0:115200n8"; 23b9edbce9SSergei Shtylyov }; 24b9edbce9SSergei Shtylyov 25b9edbce9SSergei Shtylyov memory@48000000 { 26b9edbce9SSergei Shtylyov device_type = "memory"; 27b9edbce9SSergei Shtylyov /* first 128MB is reserved for secure area. */ 28b9edbce9SSergei Shtylyov reg = <0 0x48000000 0 0x78000000>; 29b9edbce9SSergei Shtylyov }; 30b9edbce9SSergei Shtylyov}; 31b9edbce9SSergei Shtylyov 328091788fSSergei Shtylyov&avb { 338091788fSSergei Shtylyov phy-mode = "rgmii-id"; 348091788fSSergei Shtylyov phy-handle = <&phy0>; 358091788fSSergei Shtylyov renesas,no-ether-link; 368091788fSSergei Shtylyov status = "okay"; 378091788fSSergei Shtylyov 388091788fSSergei Shtylyov phy0: ethernet-phy@0 { 398091788fSSergei Shtylyov rxc-skew-ps = <1500>; 408091788fSSergei Shtylyov reg = <0>; 418091788fSSergei Shtylyov }; 428091788fSSergei Shtylyov}; 438091788fSSergei Shtylyov 44b9edbce9SSergei Shtylyov&extal_clk { 45b9edbce9SSergei Shtylyov clock-frequency = <16666666>; 46b9edbce9SSergei Shtylyov}; 47b9edbce9SSergei Shtylyov 48b9edbce9SSergei Shtylyov&extalr_clk { 49b9edbce9SSergei Shtylyov clock-frequency = <32768>; 50b9edbce9SSergei Shtylyov}; 51b9edbce9SSergei Shtylyov 52*a824e63cSSergei Shtylyov&pfc { 53*a824e63cSSergei Shtylyov scif0_pins: scif0 { 54*a824e63cSSergei Shtylyov groups = "scif0_data"; 55*a824e63cSSergei Shtylyov function = "scif0"; 56*a824e63cSSergei Shtylyov }; 57*a824e63cSSergei Shtylyov 58*a824e63cSSergei Shtylyov scif_clk_pins: scif_clk { 59*a824e63cSSergei Shtylyov groups = "scif_clk_b"; 60*a824e63cSSergei Shtylyov function = "scif_clk"; 61*a824e63cSSergei Shtylyov }; 62*a824e63cSSergei Shtylyov}; 63*a824e63cSSergei Shtylyov 64b9edbce9SSergei Shtylyov&scif0 { 65*a824e63cSSergei Shtylyov pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; 66*a824e63cSSergei Shtylyov pinctrl-names = "default"; 67*a824e63cSSergei Shtylyov 68b9edbce9SSergei Shtylyov status = "okay"; 69b9edbce9SSergei Shtylyov}; 70b9edbce9SSergei Shtylyov 71b9edbce9SSergei Shtylyov&scif_clk { 72b9edbce9SSergei Shtylyov clock-frequency = <14745600>; 73b9edbce9SSergei Shtylyov}; 74