1b9edbce9SSergei Shtylyov// SPDX-License-Identifier: GPL-2.0 2b9edbce9SSergei Shtylyov/* 3b9edbce9SSergei Shtylyov * Device Tree Source for the Condor board 4b9edbce9SSergei Shtylyov * 5b9edbce9SSergei Shtylyov * Copyright (C) 2018 Renesas Electronics Corp. 6b9edbce9SSergei Shtylyov * Copyright (C) 2018 Cogent Embedded, Inc. 7b9edbce9SSergei Shtylyov */ 8b9edbce9SSergei Shtylyov 9b9edbce9SSergei Shtylyov/dts-v1/; 10b9edbce9SSergei Shtylyov#include "r8a77980.dtsi" 11b9edbce9SSergei Shtylyov 12b9edbce9SSergei Shtylyov/ { 13b9edbce9SSergei Shtylyov model = "Renesas Condor board based on r8a77980"; 14b9edbce9SSergei Shtylyov compatible = "renesas,condor", "renesas,r8a77980"; 15b9edbce9SSergei Shtylyov 16b9edbce9SSergei Shtylyov aliases { 17b9edbce9SSergei Shtylyov serial0 = &scif0; 18eab53fdfSSergei Shtylyov ethernet0 = &gether; 19b9edbce9SSergei Shtylyov }; 20b9edbce9SSergei Shtylyov 21b9edbce9SSergei Shtylyov chosen { 22b9edbce9SSergei Shtylyov stdout-path = "serial0:115200n8"; 23b9edbce9SSergei Shtylyov }; 24b9edbce9SSergei Shtylyov 25*8ccb4c97SYoshihiro Kaneko d1_8v: regulator-2 { 26*8ccb4c97SYoshihiro Kaneko compatible = "regulator-fixed"; 27*8ccb4c97SYoshihiro Kaneko regulator-name = "D1.8V"; 28*8ccb4c97SYoshihiro Kaneko regulator-min-microvolt = <1800000>; 29*8ccb4c97SYoshihiro Kaneko regulator-max-microvolt = <1800000>; 30*8ccb4c97SYoshihiro Kaneko regulator-boot-on; 31*8ccb4c97SYoshihiro Kaneko regulator-always-on; 32b9edbce9SSergei Shtylyov }; 33cc922244SSergei Shtylyov 34cc922244SSergei Shtylyov d3_3v: regulator-0 { 35cc922244SSergei Shtylyov compatible = "regulator-fixed"; 36cc922244SSergei Shtylyov regulator-name = "D3.3V"; 37cc922244SSergei Shtylyov regulator-min-microvolt = <3300000>; 38cc922244SSergei Shtylyov regulator-max-microvolt = <3300000>; 39cc922244SSergei Shtylyov regulator-boot-on; 40cc922244SSergei Shtylyov regulator-always-on; 41cc922244SSergei Shtylyov }; 42cc922244SSergei Shtylyov 4370fd8b6aSSergei Shtylyov hdmi-out { 4470fd8b6aSSergei Shtylyov compatible = "hdmi-connector"; 4570fd8b6aSSergei Shtylyov type = "a"; 4670fd8b6aSSergei Shtylyov 4770fd8b6aSSergei Shtylyov port { 4870fd8b6aSSergei Shtylyov hdmi_con: endpoint { 4970fd8b6aSSergei Shtylyov remote-endpoint = <&adv7511_out>; 5070fd8b6aSSergei Shtylyov }; 5170fd8b6aSSergei Shtylyov }; 5270fd8b6aSSergei Shtylyov }; 5370fd8b6aSSergei Shtylyov 5470fd8b6aSSergei Shtylyov lvds-decoder { 5570fd8b6aSSergei Shtylyov compatible = "thine,thc63lvd1024"; 5670fd8b6aSSergei Shtylyov vcc-supply = <&d3_3v>; 5770fd8b6aSSergei Shtylyov 5870fd8b6aSSergei Shtylyov ports { 5970fd8b6aSSergei Shtylyov #address-cells = <1>; 6070fd8b6aSSergei Shtylyov #size-cells = <0>; 6170fd8b6aSSergei Shtylyov 6270fd8b6aSSergei Shtylyov port@0 { 6370fd8b6aSSergei Shtylyov reg = <0>; 6470fd8b6aSSergei Shtylyov thc63lvd1024_in: endpoint { 6570fd8b6aSSergei Shtylyov remote-endpoint = <&lvds0_out>; 6670fd8b6aSSergei Shtylyov }; 6770fd8b6aSSergei Shtylyov }; 6870fd8b6aSSergei Shtylyov 6970fd8b6aSSergei Shtylyov port@2 { 7070fd8b6aSSergei Shtylyov reg = <2>; 7170fd8b6aSSergei Shtylyov thc63lvd1024_out: endpoint { 7270fd8b6aSSergei Shtylyov remote-endpoint = <&adv7511_in>; 7370fd8b6aSSergei Shtylyov }; 7470fd8b6aSSergei Shtylyov }; 7570fd8b6aSSergei Shtylyov }; 7670fd8b6aSSergei Shtylyov }; 7770fd8b6aSSergei Shtylyov 78*8ccb4c97SYoshihiro Kaneko memory@48000000 { 79*8ccb4c97SYoshihiro Kaneko device_type = "memory"; 80*8ccb4c97SYoshihiro Kaneko /* first 128MB is reserved for secure area. */ 81*8ccb4c97SYoshihiro Kaneko reg = <0 0x48000000 0 0x78000000>; 82*8ccb4c97SYoshihiro Kaneko }; 83*8ccb4c97SYoshihiro Kaneko 84*8ccb4c97SYoshihiro Kaneko vddq_vin01: regulator-1 { 85*8ccb4c97SYoshihiro Kaneko compatible = "regulator-fixed"; 86*8ccb4c97SYoshihiro Kaneko regulator-name = "VDDQ_VIN01"; 87*8ccb4c97SYoshihiro Kaneko regulator-min-microvolt = <1800000>; 88*8ccb4c97SYoshihiro Kaneko regulator-max-microvolt = <1800000>; 89*8ccb4c97SYoshihiro Kaneko regulator-boot-on; 90*8ccb4c97SYoshihiro Kaneko regulator-always-on; 91*8ccb4c97SYoshihiro Kaneko }; 92*8ccb4c97SYoshihiro Kaneko 9370fd8b6aSSergei Shtylyov x1_clk: x1-clock { 9470fd8b6aSSergei Shtylyov compatible = "fixed-clock"; 9570fd8b6aSSergei Shtylyov #clock-cells = <0>; 9670fd8b6aSSergei Shtylyov clock-frequency = <148500000>; 9770fd8b6aSSergei Shtylyov }; 98b9edbce9SSergei Shtylyov}; 99b9edbce9SSergei Shtylyov 1007a9706d2SSergei Shtylyov&canfd { 1017a9706d2SSergei Shtylyov pinctrl-0 = <&canfd0_pins>; 1027a9706d2SSergei Shtylyov pinctrl-names = "default"; 1037a9706d2SSergei Shtylyov status = "okay"; 1047a9706d2SSergei Shtylyov 1057a9706d2SSergei Shtylyov channel0 { 1067a9706d2SSergei Shtylyov status = "okay"; 1077a9706d2SSergei Shtylyov }; 1087a9706d2SSergei Shtylyov}; 1097a9706d2SSergei Shtylyov 11070fd8b6aSSergei Shtylyov&du { 11170fd8b6aSSergei Shtylyov clocks = <&cpg CPG_MOD 724>, 11270fd8b6aSSergei Shtylyov <&x1_clk>; 11370fd8b6aSSergei Shtylyov clock-names = "du.0", "dclkin.0"; 11470fd8b6aSSergei Shtylyov status = "okay"; 11570fd8b6aSSergei Shtylyov}; 11670fd8b6aSSergei Shtylyov 117b9edbce9SSergei Shtylyov&extal_clk { 118b9edbce9SSergei Shtylyov clock-frequency = <16666666>; 119b9edbce9SSergei Shtylyov}; 120b9edbce9SSergei Shtylyov 121b9edbce9SSergei Shtylyov&extalr_clk { 122b9edbce9SSergei Shtylyov clock-frequency = <32768>; 123b9edbce9SSergei Shtylyov}; 124b9edbce9SSergei Shtylyov 125eab53fdfSSergei Shtylyov&gether { 126eab53fdfSSergei Shtylyov pinctrl-0 = <&gether_pins>; 127eab53fdfSSergei Shtylyov pinctrl-names = "default"; 128eab53fdfSSergei Shtylyov 129eab53fdfSSergei Shtylyov phy-mode = "rgmii-id"; 130eab53fdfSSergei Shtylyov phy-handle = <&phy0>; 131eab53fdfSSergei Shtylyov renesas,no-ether-link; 132eab53fdfSSergei Shtylyov status = "okay"; 133eab53fdfSSergei Shtylyov 134eab53fdfSSergei Shtylyov phy0: ethernet-phy@0 { 135eab53fdfSSergei Shtylyov rxc-skew-ps = <1500>; 136eab53fdfSSergei Shtylyov reg = <0>; 137eab53fdfSSergei Shtylyov interrupt-parent = <&gpio4>; 138eab53fdfSSergei Shtylyov interrupts = <23 IRQ_TYPE_LEVEL_LOW>; 139eab53fdfSSergei Shtylyov }; 140eab53fdfSSergei Shtylyov}; 141eab53fdfSSergei Shtylyov 14245fde0d4SSergei Shtylyov&i2c0 { 14345fde0d4SSergei Shtylyov pinctrl-0 = <&i2c0_pins>; 14445fde0d4SSergei Shtylyov pinctrl-names = "default"; 14545fde0d4SSergei Shtylyov 14645fde0d4SSergei Shtylyov status = "okay"; 14745fde0d4SSergei Shtylyov clock-frequency = <400000>; 14845fde0d4SSergei Shtylyov 14945fde0d4SSergei Shtylyov io_expander0: gpio@20 { 15045fde0d4SSergei Shtylyov compatible = "onnn,pca9654"; 15145fde0d4SSergei Shtylyov reg = <0x20>; 15245fde0d4SSergei Shtylyov gpio-controller; 15345fde0d4SSergei Shtylyov #gpio-cells = <2>; 15445fde0d4SSergei Shtylyov }; 15545fde0d4SSergei Shtylyov 15645fde0d4SSergei Shtylyov io_expander1: gpio@21 { 15745fde0d4SSergei Shtylyov compatible = "onnn,pca9654"; 15845fde0d4SSergei Shtylyov reg = <0x21>; 15945fde0d4SSergei Shtylyov gpio-controller; 16045fde0d4SSergei Shtylyov #gpio-cells = <2>; 16145fde0d4SSergei Shtylyov }; 16270fd8b6aSSergei Shtylyov 16370fd8b6aSSergei Shtylyov hdmi@39 { 16470fd8b6aSSergei Shtylyov compatible = "adi,adv7511w"; 16570fd8b6aSSergei Shtylyov reg = <0x39>; 16670fd8b6aSSergei Shtylyov interrupt-parent = <&gpio1>; 16770fd8b6aSSergei Shtylyov interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 16870fd8b6aSSergei Shtylyov avdd-supply = <&d1_8v>; 16970fd8b6aSSergei Shtylyov dvdd-supply = <&d1_8v>; 17070fd8b6aSSergei Shtylyov pvdd-supply = <&d1_8v>; 17170fd8b6aSSergei Shtylyov bgvdd-supply = <&d1_8v>; 17270fd8b6aSSergei Shtylyov dvdd-3v-supply = <&d3_3v>; 17370fd8b6aSSergei Shtylyov 17470fd8b6aSSergei Shtylyov adi,input-depth = <8>; 17570fd8b6aSSergei Shtylyov adi,input-colorspace = "rgb"; 17670fd8b6aSSergei Shtylyov adi,input-clock = "1x"; 17770fd8b6aSSergei Shtylyov adi,input-style = <1>; 17870fd8b6aSSergei Shtylyov adi,input-justification = "evenly"; 17970fd8b6aSSergei Shtylyov 18070fd8b6aSSergei Shtylyov ports { 18170fd8b6aSSergei Shtylyov #address-cells = <1>; 18270fd8b6aSSergei Shtylyov #size-cells = <0>; 18370fd8b6aSSergei Shtylyov 18470fd8b6aSSergei Shtylyov port@0 { 18570fd8b6aSSergei Shtylyov reg = <0>; 18670fd8b6aSSergei Shtylyov adv7511_in: endpoint { 18770fd8b6aSSergei Shtylyov remote-endpoint = <&thc63lvd1024_out>; 18870fd8b6aSSergei Shtylyov }; 18970fd8b6aSSergei Shtylyov }; 19070fd8b6aSSergei Shtylyov 19170fd8b6aSSergei Shtylyov port@1 { 19270fd8b6aSSergei Shtylyov reg = <1>; 19370fd8b6aSSergei Shtylyov adv7511_out: endpoint { 19470fd8b6aSSergei Shtylyov remote-endpoint = <&hdmi_con>; 19570fd8b6aSSergei Shtylyov }; 19670fd8b6aSSergei Shtylyov }; 19770fd8b6aSSergei Shtylyov }; 19870fd8b6aSSergei Shtylyov }; 19970fd8b6aSSergei Shtylyov}; 20070fd8b6aSSergei Shtylyov 20170fd8b6aSSergei Shtylyov&lvds0 { 20270fd8b6aSSergei Shtylyov status = "okay"; 20370fd8b6aSSergei Shtylyov 20470fd8b6aSSergei Shtylyov ports { 20570fd8b6aSSergei Shtylyov port@1 { 20670fd8b6aSSergei Shtylyov lvds0_out: endpoint { 20770fd8b6aSSergei Shtylyov remote-endpoint = <&thc63lvd1024_in>; 20870fd8b6aSSergei Shtylyov }; 20970fd8b6aSSergei Shtylyov }; 21070fd8b6aSSergei Shtylyov }; 21145fde0d4SSergei Shtylyov}; 21245fde0d4SSergei Shtylyov 213cc922244SSergei Shtylyov&mmc0 { 214cc922244SSergei Shtylyov pinctrl-0 = <&mmc_pins>; 215cc922244SSergei Shtylyov pinctrl-1 = <&mmc_pins_uhs>; 216cc922244SSergei Shtylyov pinctrl-names = "default", "state_uhs"; 217cc922244SSergei Shtylyov 218cc922244SSergei Shtylyov vmmc-supply = <&d3_3v>; 219cc922244SSergei Shtylyov vqmmc-supply = <&vddq_vin01>; 220cc922244SSergei Shtylyov mmc-hs200-1_8v; 221cc922244SSergei Shtylyov bus-width = <8>; 222cc922244SSergei Shtylyov non-removable; 223cc922244SSergei Shtylyov status = "okay"; 224cc922244SSergei Shtylyov}; 225cc922244SSergei Shtylyov 226c6eb2047SSergei Shtylyov&pciec { 227c6eb2047SSergei Shtylyov status = "okay"; 228c6eb2047SSergei Shtylyov}; 229c6eb2047SSergei Shtylyov 230c6eb2047SSergei Shtylyov&pcie_bus_clk { 231c6eb2047SSergei Shtylyov clock-frequency = <100000000>; 232c6eb2047SSergei Shtylyov}; 233c6eb2047SSergei Shtylyov 234c6eb2047SSergei Shtylyov&pcie_phy { 235c6eb2047SSergei Shtylyov status = "okay"; 236c6eb2047SSergei Shtylyov}; 237c6eb2047SSergei Shtylyov 238a824e63cSSergei Shtylyov&pfc { 2397a9706d2SSergei Shtylyov canfd0_pins: canfd0 { 2407a9706d2SSergei Shtylyov groups = "canfd0_data_a"; 2417a9706d2SSergei Shtylyov function = "canfd0"; 2427a9706d2SSergei Shtylyov }; 2437a9706d2SSergei Shtylyov 244eab53fdfSSergei Shtylyov gether_pins: gether { 245eab53fdfSSergei Shtylyov groups = "gether_mdio_a", "gether_rgmii", 246eab53fdfSSergei Shtylyov "gether_txcrefclk", "gether_txcrefclk_mega"; 247eab53fdfSSergei Shtylyov function = "gether"; 248eab53fdfSSergei Shtylyov }; 249eab53fdfSSergei Shtylyov 25045fde0d4SSergei Shtylyov i2c0_pins: i2c0 { 25145fde0d4SSergei Shtylyov groups = "i2c0"; 25245fde0d4SSergei Shtylyov function = "i2c0"; 25345fde0d4SSergei Shtylyov }; 25445fde0d4SSergei Shtylyov 255cc922244SSergei Shtylyov mmc_pins: mmc { 256cc922244SSergei Shtylyov groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; 257cc922244SSergei Shtylyov function = "mmc"; 258cc922244SSergei Shtylyov power-source = <3300>; 259cc922244SSergei Shtylyov }; 260cc922244SSergei Shtylyov 261cc922244SSergei Shtylyov mmc_pins_uhs: mmc_uhs { 262cc922244SSergei Shtylyov groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; 263cc922244SSergei Shtylyov function = "mmc"; 264cc922244SSergei Shtylyov power-source = <1800>; 265cc922244SSergei Shtylyov }; 266cc922244SSergei Shtylyov 267a824e63cSSergei Shtylyov scif0_pins: scif0 { 268a824e63cSSergei Shtylyov groups = "scif0_data"; 269a824e63cSSergei Shtylyov function = "scif0"; 270a824e63cSSergei Shtylyov }; 271a824e63cSSergei Shtylyov 272a824e63cSSergei Shtylyov scif_clk_pins: scif_clk { 273a824e63cSSergei Shtylyov groups = "scif_clk_b"; 274a824e63cSSergei Shtylyov function = "scif_clk"; 275a824e63cSSergei Shtylyov }; 276a824e63cSSergei Shtylyov}; 277a824e63cSSergei Shtylyov 278bcee502cSSergei Shtylyov&rwdt { 279bcee502cSSergei Shtylyov timeout-sec = <60>; 280bcee502cSSergei Shtylyov status = "okay"; 281bcee502cSSergei Shtylyov}; 282bcee502cSSergei Shtylyov 283b9edbce9SSergei Shtylyov&scif0 { 284a824e63cSSergei Shtylyov pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; 285a824e63cSSergei Shtylyov pinctrl-names = "default"; 286a824e63cSSergei Shtylyov 287b9edbce9SSergei Shtylyov status = "okay"; 288b9edbce9SSergei Shtylyov}; 289b9edbce9SSergei Shtylyov 290b9edbce9SSergei Shtylyov&scif_clk { 291b9edbce9SSergei Shtylyov clock-frequency = <14745600>; 292b9edbce9SSergei Shtylyov}; 293