1/* 2 * Device Tree Source for the r8a77970 SoC 3 * 4 * Copyright (C) 2016-2017 Renesas Electronics Corp. 5 * Copyright (C) 2017 Cogent Embedded, Inc. 6 * 7 * This file is licensed under the terms of the GNU General Public License 8 * version 2. This program is licensed "as is" without any warranty of any 9 * kind, whether express or implied. 10 */ 11 12#include <dt-bindings/clock/r8a77970-cpg-mssr.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/power/r8a77970-sysc.h> 16 17/ { 18 compatible = "renesas,r8a77970"; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 a53_0: cpu@0 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a53", "arm,armv8"; 37 reg = <0>; 38 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; 39 power-domains = <&sysc R8A77970_PD_CA53_CPU0>; 40 next-level-cache = <&L2_CA53>; 41 enable-method = "psci"; 42 }; 43 44 a53_1: cpu@1 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a53", "arm,armv8"; 47 reg = <1>; 48 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; 49 power-domains = <&sysc R8A77970_PD_CA53_CPU1>; 50 next-level-cache = <&L2_CA53>; 51 enable-method = "psci"; 52 }; 53 54 L2_CA53: cache-controller { 55 compatible = "cache"; 56 power-domains = <&sysc R8A77970_PD_CA53_SCU>; 57 cache-unified; 58 cache-level = <2>; 59 }; 60 }; 61 62 extal_clk: extal { 63 compatible = "fixed-clock"; 64 #clock-cells = <0>; 65 /* This value must be overridden by the board */ 66 clock-frequency = <0>; 67 }; 68 69 extalr_clk: extalr { 70 compatible = "fixed-clock"; 71 #clock-cells = <0>; 72 /* This value must be overridden by the board */ 73 clock-frequency = <0>; 74 }; 75 76 pmu_a53 { 77 compatible = "arm,cortex-a53-pmu"; 78 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 79 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 80 interrupt-affinity = <&a53_0>, <&a53_1>; 81 }; 82 83 psci { 84 compatible = "arm,psci-1.0", "arm,psci-0.2"; 85 method = "smc"; 86 }; 87 88 /* External CAN clock - to be overridden by boards that provide it */ 89 can_clk: can { 90 compatible = "fixed-clock"; 91 #clock-cells = <0>; 92 clock-frequency = <0>; 93 }; 94 95 /* External SCIF clock - to be overridden by boards that provide it */ 96 scif_clk: scif { 97 compatible = "fixed-clock"; 98 #clock-cells = <0>; 99 clock-frequency = <0>; 100 }; 101 102 soc { 103 compatible = "simple-bus"; 104 interrupt-parent = <&gic>; 105 106 #address-cells = <2>; 107 #size-cells = <2>; 108 ranges; 109 110 rwdt: watchdog@e6020000 { 111 compatible = "renesas,r8a77970-wdt", 112 "renesas,rcar-gen3-wdt"; 113 reg = <0 0xe6020000 0 0x0c>; 114 clocks = <&cpg CPG_MOD 402>; 115 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 116 resets = <&cpg 402>; 117 status = "disabled"; 118 }; 119 120 gpio0: gpio@e6050000 { 121 compatible = "renesas,gpio-r8a77970", 122 "renesas,rcar-gen3-gpio"; 123 reg = <0 0xe6050000 0 0x50>; 124 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 125 #gpio-cells = <2>; 126 gpio-controller; 127 gpio-ranges = <&pfc 0 0 22>; 128 #interrupt-cells = <2>; 129 interrupt-controller; 130 clocks = <&cpg CPG_MOD 912>; 131 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 132 resets = <&cpg 912>; 133 }; 134 135 gpio1: gpio@e6051000 { 136 compatible = "renesas,gpio-r8a77970", 137 "renesas,rcar-gen3-gpio"; 138 reg = <0 0xe6051000 0 0x50>; 139 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 140 #gpio-cells = <2>; 141 gpio-controller; 142 gpio-ranges = <&pfc 0 32 28>; 143 #interrupt-cells = <2>; 144 interrupt-controller; 145 clocks = <&cpg CPG_MOD 911>; 146 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 147 resets = <&cpg 911>; 148 }; 149 150 gpio2: gpio@e6052000 { 151 compatible = "renesas,gpio-r8a77970", 152 "renesas,rcar-gen3-gpio"; 153 reg = <0 0xe6052000 0 0x50>; 154 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 155 #gpio-cells = <2>; 156 gpio-controller; 157 gpio-ranges = <&pfc 0 64 17>; 158 #interrupt-cells = <2>; 159 interrupt-controller; 160 clocks = <&cpg CPG_MOD 910>; 161 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 162 resets = <&cpg 910>; 163 }; 164 165 gpio3: gpio@e6053000 { 166 compatible = "renesas,gpio-r8a77970", 167 "renesas,rcar-gen3-gpio"; 168 reg = <0 0xe6053000 0 0x50>; 169 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 170 #gpio-cells = <2>; 171 gpio-controller; 172 gpio-ranges = <&pfc 0 96 17>; 173 #interrupt-cells = <2>; 174 interrupt-controller; 175 clocks = <&cpg CPG_MOD 909>; 176 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 177 resets = <&cpg 909>; 178 }; 179 180 gpio4: gpio@e6054000 { 181 compatible = "renesas,gpio-r8a77970", 182 "renesas,rcar-gen3-gpio"; 183 reg = <0 0xe6054000 0 0x50>; 184 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 185 #gpio-cells = <2>; 186 gpio-controller; 187 gpio-ranges = <&pfc 0 128 6>; 188 #interrupt-cells = <2>; 189 interrupt-controller; 190 clocks = <&cpg CPG_MOD 908>; 191 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 192 resets = <&cpg 908>; 193 }; 194 195 gpio5: gpio@e6055000 { 196 compatible = "renesas,gpio-r8a77970", 197 "renesas,rcar-gen3-gpio"; 198 reg = <0 0xe6055000 0 0x50>; 199 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 200 #gpio-cells = <2>; 201 gpio-controller; 202 gpio-ranges = <&pfc 0 160 15>; 203 #interrupt-cells = <2>; 204 interrupt-controller; 205 clocks = <&cpg CPG_MOD 907>; 206 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 207 resets = <&cpg 907>; 208 }; 209 210 pfc: pin-controller@e6060000 { 211 compatible = "renesas,pfc-r8a77970"; 212 reg = <0 0xe6060000 0 0x504>; 213 }; 214 215 cpg: clock-controller@e6150000 { 216 compatible = "renesas,r8a77970-cpg-mssr"; 217 reg = <0 0xe6150000 0 0x1000>; 218 clocks = <&extal_clk>, <&extalr_clk>; 219 clock-names = "extal", "extalr"; 220 #clock-cells = <2>; 221 #power-domain-cells = <0>; 222 #reset-cells = <1>; 223 }; 224 225 rst: reset-controller@e6160000 { 226 compatible = "renesas,r8a77970-rst"; 227 reg = <0 0xe6160000 0 0x200>; 228 }; 229 230 sysc: system-controller@e6180000 { 231 compatible = "renesas,r8a77970-sysc"; 232 reg = <0 0xe6180000 0 0x440>; 233 #power-domain-cells = <1>; 234 }; 235 236 intc_ex: interrupt-controller@e61c0000 { 237 compatible = "renesas,intc-ex-r8a77970", "renesas,irqc"; 238 #interrupt-cells = <2>; 239 interrupt-controller; 240 reg = <0 0xe61c0000 0 0x200>; 241 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 242 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 243 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 244 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 245 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 246 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 247 clocks = <&cpg CPG_MOD 407>; 248 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 249 resets = <&cpg 407>; 250 }; 251 252 i2c0: i2c@e6500000 { 253 compatible = "renesas,i2c-r8a77970", 254 "renesas,rcar-gen3-i2c"; 255 reg = <0 0xe6500000 0 0x40>; 256 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&cpg CPG_MOD 931>; 258 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 259 resets = <&cpg 931>; 260 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 261 <&dmac2 0x91>, <&dmac2 0x90>; 262 dma-names = "tx", "rx", "tx", "rx"; 263 i2c-scl-internal-delay-ns = <6>; 264 #address-cells = <1>; 265 #size-cells = <0>; 266 status = "disabled"; 267 }; 268 269 i2c1: i2c@e6508000 { 270 compatible = "renesas,i2c-r8a77970", 271 "renesas,rcar-gen3-i2c"; 272 reg = <0 0xe6508000 0 0x40>; 273 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 274 clocks = <&cpg CPG_MOD 930>; 275 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 276 resets = <&cpg 930>; 277 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 278 <&dmac2 0x93>, <&dmac2 0x92>; 279 dma-names = "tx", "rx", "tx", "rx"; 280 i2c-scl-internal-delay-ns = <6>; 281 #address-cells = <1>; 282 #size-cells = <0>; 283 status = "disabled"; 284 }; 285 286 i2c2: i2c@e6510000 { 287 compatible = "renesas,i2c-r8a77970", 288 "renesas,rcar-gen3-i2c"; 289 reg = <0 0xe6510000 0 0x40>; 290 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&cpg CPG_MOD 929>; 292 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 293 resets = <&cpg 929>; 294 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 295 <&dmac2 0x95>, <&dmac2 0x94>; 296 dma-names = "tx", "rx", "tx", "rx"; 297 i2c-scl-internal-delay-ns = <6>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 status = "disabled"; 301 }; 302 303 i2c3: i2c@e66d0000 { 304 compatible = "renesas,i2c-r8a77970", 305 "renesas,rcar-gen3-i2c"; 306 reg = <0 0xe66d0000 0 0x40>; 307 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&cpg CPG_MOD 928>; 309 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 310 resets = <&cpg 928>; 311 dmas = <&dmac1 0x97>, <&dmac1 0x96>, 312 <&dmac2 0x97>, <&dmac2 0x96>; 313 dma-names = "tx", "rx", "tx", "rx"; 314 i2c-scl-internal-delay-ns = <6>; 315 #address-cells = <1>; 316 #size-cells = <0>; 317 status = "disabled"; 318 }; 319 320 i2c4: i2c@e66d8000 { 321 compatible = "renesas,i2c-r8a77970", 322 "renesas,rcar-gen3-i2c"; 323 reg = <0 0xe66d8000 0 0x40>; 324 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&cpg CPG_MOD 927>; 326 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 327 resets = <&cpg 927>; 328 dmas = <&dmac1 0x99>, <&dmac1 0x98>, 329 <&dmac2 0x99>, <&dmac2 0x98>; 330 dma-names = "tx", "rx", "tx", "rx"; 331 i2c-scl-internal-delay-ns = <6>; 332 #address-cells = <1>; 333 #size-cells = <0>; 334 status = "disabled"; 335 }; 336 337 hscif0: serial@e6540000 { 338 compatible = "renesas,hscif-r8a77970", 339 "renesas,rcar-gen3-hscif", 340 "renesas,hscif"; 341 reg = <0 0xe6540000 0 96>; 342 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&cpg CPG_MOD 520>, 344 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 345 <&scif_clk>; 346 clock-names = "fck", "brg_int", "scif_clk"; 347 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 348 <&dmac2 0x31>, <&dmac2 0x30>; 349 dma-names = "tx", "rx", "tx", "rx"; 350 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 351 resets = <&cpg 520>; 352 status = "disabled"; 353 }; 354 355 hscif1: serial@e6550000 { 356 compatible = "renesas,hscif-r8a77970", 357 "renesas,rcar-gen3-hscif", 358 "renesas,hscif"; 359 reg = <0 0xe6550000 0 96>; 360 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&cpg CPG_MOD 519>, 362 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 363 <&scif_clk>; 364 clock-names = "fck", "brg_int", "scif_clk"; 365 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 366 <&dmac2 0x33>, <&dmac2 0x32>; 367 dma-names = "tx", "rx", "tx", "rx"; 368 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 369 resets = <&cpg 519>; 370 status = "disabled"; 371 }; 372 373 hscif2: serial@e6560000 { 374 compatible = "renesas,hscif-r8a77970", 375 "renesas,rcar-gen3-hscif", 376 "renesas,hscif"; 377 reg = <0 0xe6560000 0 96>; 378 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&cpg CPG_MOD 518>, 380 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 381 <&scif_clk>; 382 clock-names = "fck", "brg_int", "scif_clk"; 383 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 384 <&dmac2 0x35>, <&dmac2 0x34>; 385 dma-names = "tx", "rx", "tx", "rx"; 386 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 387 resets = <&cpg 518>; 388 status = "disabled"; 389 }; 390 391 hscif3: serial@e66a0000 { 392 compatible = "renesas,hscif-r8a77970", 393 "renesas,rcar-gen3-hscif", "renesas,hscif"; 394 reg = <0 0xe66a0000 0 96>; 395 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&cpg CPG_MOD 517>, 397 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 398 <&scif_clk>; 399 clock-names = "fck", "brg_int", "scif_clk"; 400 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 401 <&dmac2 0x37>, <&dmac2 0x36>; 402 dma-names = "tx", "rx", "tx", "rx"; 403 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 404 resets = <&cpg 517>; 405 status = "disabled"; 406 }; 407 408 canfd: can@e66c0000 { 409 compatible = "renesas,r8a77970-canfd", 410 "renesas,rcar-gen3-canfd"; 411 reg = <0 0xe66c0000 0 0x8000>; 412 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&cpg CPG_MOD 914>, 415 <&cpg CPG_CORE R8A77970_CLK_CANFD>, 416 <&can_clk>; 417 clock-names = "fck", "canfd", "can_clk"; 418 assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>; 419 assigned-clock-rates = <40000000>; 420 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 421 resets = <&cpg 914>; 422 status = "disabled"; 423 424 channel0 { 425 status = "disabled"; 426 }; 427 428 channel1 { 429 status = "disabled"; 430 }; 431 }; 432 433 avb: ethernet@e6800000 { 434 compatible = "renesas,etheravb-r8a77970", 435 "renesas,etheravb-rcar-gen3"; 436 reg = <0 0xe6800000 0 0x800>; 437 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 462 interrupt-names = "ch0", "ch1", "ch2", "ch3", 463 "ch4", "ch5", "ch6", "ch7", 464 "ch8", "ch9", "ch10", "ch11", 465 "ch12", "ch13", "ch14", "ch15", 466 "ch16", "ch17", "ch18", "ch19", 467 "ch20", "ch21", "ch22", "ch23", 468 "ch24"; 469 clocks = <&cpg CPG_MOD 812>; 470 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 471 resets = <&cpg 812>; 472 phy-mode = "rgmii"; 473 iommus = <&ipmmu_rt 3>; 474 #address-cells = <1>; 475 #size-cells = <0>; 476 status = "disabled"; 477 }; 478 479 scif0: serial@e6e60000 { 480 compatible = "renesas,scif-r8a77970", 481 "renesas,rcar-gen3-scif", 482 "renesas,scif"; 483 reg = <0 0xe6e60000 0 64>; 484 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 485 clocks = <&cpg CPG_MOD 207>, 486 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 487 <&scif_clk>; 488 clock-names = "fck", "brg_int", "scif_clk"; 489 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 490 <&dmac2 0x51>, <&dmac2 0x50>; 491 dma-names = "tx", "rx", "tx", "rx"; 492 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 493 resets = <&cpg 207>; 494 status = "disabled"; 495 }; 496 497 scif1: serial@e6e68000 { 498 compatible = "renesas,scif-r8a77970", 499 "renesas,rcar-gen3-scif", 500 "renesas,scif"; 501 reg = <0 0xe6e68000 0 64>; 502 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&cpg CPG_MOD 206>, 504 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 505 <&scif_clk>; 506 clock-names = "fck", "brg_int", "scif_clk"; 507 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 508 <&dmac2 0x53>, <&dmac2 0x52>; 509 dma-names = "tx", "rx", "tx", "rx"; 510 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 511 resets = <&cpg 206>; 512 status = "disabled"; 513 }; 514 515 scif3: serial@e6c50000 { 516 compatible = "renesas,scif-r8a77970", 517 "renesas,rcar-gen3-scif", 518 "renesas,scif"; 519 reg = <0 0xe6c50000 0 64>; 520 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&cpg CPG_MOD 204>, 522 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 523 <&scif_clk>; 524 clock-names = "fck", "brg_int", "scif_clk"; 525 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 526 <&dmac2 0x57>, <&dmac2 0x56>; 527 dma-names = "tx", "rx", "tx", "rx"; 528 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 529 resets = <&cpg 204>; 530 status = "disabled"; 531 }; 532 533 scif4: serial@e6c40000 { 534 compatible = "renesas,scif-r8a77970", 535 "renesas,rcar-gen3-scif", "renesas,scif"; 536 reg = <0 0xe6c40000 0 64>; 537 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&cpg CPG_MOD 203>, 539 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 540 <&scif_clk>; 541 clock-names = "fck", "brg_int", "scif_clk"; 542 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 543 <&dmac2 0x59>, <&dmac2 0x58>; 544 dma-names = "tx", "rx", "tx", "rx"; 545 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 546 resets = <&cpg 203>; 547 status = "disabled"; 548 }; 549 550 551 vin0: video@e6ef0000 { 552 compatible = "renesas,vin-r8a77970"; 553 reg = <0 0xe6ef0000 0 0x1000>; 554 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&cpg CPG_MOD 811>; 556 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 557 resets = <&cpg 811>; 558 renesas,id = <0>; 559 status = "disabled"; 560 561 ports { 562 #address-cells = <1>; 563 #size-cells = <0>; 564 565 port@1 { 566 #address-cells = <1>; 567 #size-cells = <0>; 568 569 reg = <1>; 570 571 vin0csi40: endpoint@2 { 572 reg = <2>; 573 remote-endpoint= <&csi40vin0>; 574 }; 575 }; 576 }; 577 }; 578 579 vin1: video@e6ef1000 { 580 compatible = "renesas,vin-r8a77970"; 581 reg = <0 0xe6ef1000 0 0x1000>; 582 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&cpg CPG_MOD 810>; 584 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 585 resets = <&cpg 810>; 586 renesas,id = <1>; 587 status = "disabled"; 588 589 ports { 590 #address-cells = <1>; 591 #size-cells = <0>; 592 593 port@1 { 594 #address-cells = <1>; 595 #size-cells = <0>; 596 597 reg = <1>; 598 599 vin1csi40: endpoint@2 { 600 reg = <2>; 601 remote-endpoint= <&csi40vin1>; 602 }; 603 }; 604 }; 605 }; 606 607 vin2: video@e6ef2000 { 608 compatible = "renesas,vin-r8a77970"; 609 reg = <0 0xe6ef2000 0 0x1000>; 610 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&cpg CPG_MOD 809>; 612 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 613 resets = <&cpg 809>; 614 renesas,id = <2>; 615 status = "disabled"; 616 617 ports { 618 #address-cells = <1>; 619 #size-cells = <0>; 620 621 port@1 { 622 #address-cells = <1>; 623 #size-cells = <0>; 624 625 reg = <1>; 626 627 vin2csi40: endpoint@2 { 628 reg = <2>; 629 remote-endpoint= <&csi40vin2>; 630 }; 631 }; 632 }; 633 }; 634 635 vin3: video@e6ef3000 { 636 compatible = "renesas,vin-r8a77970"; 637 reg = <0 0xe6ef3000 0 0x1000>; 638 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 639 clocks = <&cpg CPG_MOD 808>; 640 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 641 resets = <&cpg 808>; 642 renesas,id = <3>; 643 status = "disabled"; 644 645 ports { 646 #address-cells = <1>; 647 #size-cells = <0>; 648 649 port@1 { 650 #address-cells = <1>; 651 #size-cells = <0>; 652 653 reg = <1>; 654 655 vin3csi40: endpoint@2 { 656 reg = <2>; 657 remote-endpoint= <&csi40vin3>; 658 }; 659 }; 660 }; 661 }; 662 663 dmac1: dma-controller@e7300000 { 664 compatible = "renesas,dmac-r8a77970", 665 "renesas,rcar-dmac"; 666 reg = <0 0xe7300000 0 0x10000>; 667 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 668 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 669 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 670 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 671 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 672 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 673 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 674 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 675 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 676 interrupt-names = "error", 677 "ch0", "ch1", "ch2", "ch3", 678 "ch4", "ch5", "ch6", "ch7"; 679 clocks = <&cpg CPG_MOD 218>; 680 clock-names = "fck"; 681 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 682 resets = <&cpg 218>; 683 #dma-cells = <1>; 684 dma-channels = <8>; 685 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 686 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 687 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 688 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; 689 }; 690 691 dmac2: dma-controller@e7310000 { 692 compatible = "renesas,dmac-r8a77970", 693 "renesas,rcar-dmac"; 694 reg = <0 0xe7310000 0 0x10000>; 695 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 696 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 697 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 698 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 699 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 700 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 701 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 702 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 703 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 704 interrupt-names = "error", 705 "ch0", "ch1", "ch2", "ch3", 706 "ch4", "ch5", "ch6", "ch7"; 707 clocks = <&cpg CPG_MOD 217>; 708 clock-names = "fck"; 709 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 710 resets = <&cpg 217>; 711 #dma-cells = <1>; 712 dma-channels = <8>; 713 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 714 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 715 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 716 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; 717 }; 718 719 ipmmu_ds1: mmu@e7740000 { 720 compatible = "renesas,ipmmu-r8a77970"; 721 reg = <0 0xe7740000 0 0x1000>; 722 renesas,ipmmu-main = <&ipmmu_mm 0>; 723 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 724 #iommu-cells = <1>; 725 }; 726 727 ipmmu_ir: mmu@ff8b0000 { 728 compatible = "renesas,ipmmu-r8a77970"; 729 reg = <0 0xff8b0000 0 0x1000>; 730 renesas,ipmmu-main = <&ipmmu_mm 3>; 731 power-domains = <&sysc R8A77970_PD_A3IR>; 732 #iommu-cells = <1>; 733 }; 734 735 ipmmu_mm: mmu@e67b0000 { 736 compatible = "renesas,ipmmu-r8a77970"; 737 reg = <0 0xe67b0000 0 0x1000>; 738 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 740 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 741 #iommu-cells = <1>; 742 }; 743 744 ipmmu_rt: mmu@ffc80000 { 745 compatible = "renesas,ipmmu-r8a77970"; 746 reg = <0 0xffc80000 0 0x1000>; 747 renesas,ipmmu-main = <&ipmmu_mm 7>; 748 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 749 #iommu-cells = <1>; 750 }; 751 752 ipmmu_vi0: mmu@febd0000 { 753 compatible = "renesas,ipmmu-r8a77970"; 754 reg = <0 0xfebd0000 0 0x1000>; 755 renesas,ipmmu-main = <&ipmmu_mm 9>; 756 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 757 #iommu-cells = <1>; 758 }; 759 760 gic: interrupt-controller@f1010000 { 761 compatible = "arm,gic-400"; 762 #interrupt-cells = <3>; 763 #address-cells = <0>; 764 interrupt-controller; 765 reg = <0 0xf1010000 0 0x1000>, 766 <0 0xf1020000 0 0x20000>, 767 <0 0xf1040000 0 0x20000>, 768 <0 0xf1060000 0 0x20000>; 769 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 770 IRQ_TYPE_LEVEL_HIGH)>; 771 clocks = <&cpg CPG_MOD 408>; 772 clock-names = "clk"; 773 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 774 resets = <&cpg 408>; 775 }; 776 777 vspd0: vsp@fea20000 { 778 compatible = "renesas,vsp2"; 779 reg = <0 0xfea20000 0 0x8000>; 780 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&cpg CPG_MOD 623>; 782 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 783 resets = <&cpg 623>; 784 renesas,fcp = <&fcpvd0>; 785 }; 786 787 fcpvd0: fcp@fea27000 { 788 compatible = "renesas,fcpv"; 789 reg = <0 0xfea27000 0 0x200>; 790 clocks = <&cpg CPG_MOD 603>; 791 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 792 resets = <&cpg 603>; 793 }; 794 795 csi40: csi2@feaa0000 { 796 compatible = "renesas,r8a77970-csi2"; 797 reg = <0 0xfeaa0000 0 0x10000>; 798 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 799 clocks = <&cpg CPG_MOD 716>; 800 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 801 resets = <&cpg 716>; 802 status = "disabled"; 803 804 ports { 805 #address-cells = <1>; 806 #size-cells = <0>; 807 808 port@1 { 809 #address-cells = <1>; 810 #size-cells = <0>; 811 812 reg = <1>; 813 814 csi40vin0: endpoint@0 { 815 reg = <0>; 816 remote-endpoint = <&vin0csi40>; 817 }; 818 csi40vin1: endpoint@1 { 819 reg = <1>; 820 remote-endpoint = <&vin1csi40>; 821 }; 822 csi40vin2: endpoint@2 { 823 reg = <2>; 824 remote-endpoint = <&vin2csi40>; 825 }; 826 csi40vin3: endpoint@3 { 827 reg = <3>; 828 remote-endpoint = <&vin3csi40>; 829 }; 830 }; 831 }; 832 }; 833 834 du: display@feb00000 { 835 compatible = "renesas,du-r8a77970"; 836 reg = <0 0xfeb00000 0 0x80000>; 837 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 838 clocks = <&cpg CPG_MOD 724>; 839 clock-names = "du.0"; 840 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 841 resets = <&cpg 724>; 842 vsps = <&vspd0>; 843 status = "disabled"; 844 845 ports { 846 #address-cells = <1>; 847 #size-cells = <0>; 848 849 port@0 { 850 reg = <0>; 851 du_out_rgb: endpoint { 852 }; 853 }; 854 855 port@1 { 856 reg = <1>; 857 du_out_lvds0: endpoint { 858 remote-endpoint = <&lvds0_in>; 859 }; 860 }; 861 }; 862 }; 863 864 lvds0: lvds-encoder@feb90000 { 865 compatible = "renesas,r8a77970-lvds"; 866 reg = <0 0xfeb90000 0 0x14>; 867 clocks = <&cpg CPG_MOD 727>; 868 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 869 resets = <&cpg 727>; 870 status = "disabled"; 871 872 ports { 873 #address-cells = <1>; 874 #size-cells = <0>; 875 876 port@0 { 877 reg = <0>; 878 lvds0_in: endpoint { 879 remote-endpoint = 880 <&du_out_lvds0>; 881 }; 882 }; 883 port@1 { 884 reg = <1>; 885 lvds0_out: endpoint { 886 }; 887 }; 888 }; 889 }; 890 891 prr: chipid@fff00044 { 892 compatible = "renesas,prr"; 893 reg = <0 0xfff00044 0 4>; 894 }; 895 }; 896 897 timer { 898 compatible = "arm,armv8-timer"; 899 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 900 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 901 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 902 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 903 }; 904}; 905