1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car V3M (R8A77970) SoC 4 * 5 * Copyright (C) 2016-2017 Renesas Electronics Corp. 6 * Copyright (C) 2017 Cogent Embedded, Inc. 7 */ 8 9#include <dt-bindings/clock/r8a77970-cpg-mssr.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/power/r8a77970-sysc.h> 13 14/ { 15 compatible = "renesas,r8a77970"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 i2c0 = &i2c0; 21 i2c1 = &i2c1; 22 i2c2 = &i2c2; 23 i2c3 = &i2c3; 24 i2c4 = &i2c4; 25 }; 26 27 /* External CAN clock - to be overridden by boards that provide it */ 28 can_clk: can { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <0>; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 a53_0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a53"; 41 reg = <0>; 42 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; 43 power-domains = <&sysc R8A77970_PD_CA53_CPU0>; 44 next-level-cache = <&L2_CA53>; 45 enable-method = "psci"; 46 }; 47 48 a53_1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53"; 51 reg = <1>; 52 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; 53 power-domains = <&sysc R8A77970_PD_CA53_CPU1>; 54 next-level-cache = <&L2_CA53>; 55 enable-method = "psci"; 56 }; 57 58 L2_CA53: cache-controller { 59 compatible = "cache"; 60 power-domains = <&sysc R8A77970_PD_CA53_SCU>; 61 cache-unified; 62 cache-level = <2>; 63 }; 64 }; 65 66 extal_clk: extal { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 /* This value must be overridden by the board */ 70 clock-frequency = <0>; 71 }; 72 73 extalr_clk: extalr { 74 compatible = "fixed-clock"; 75 #clock-cells = <0>; 76 /* This value must be overridden by the board */ 77 clock-frequency = <0>; 78 }; 79 80 pmu_a53 { 81 compatible = "arm,cortex-a53-pmu"; 82 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 83 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 84 interrupt-affinity = <&a53_0>, <&a53_1>; 85 }; 86 87 psci { 88 compatible = "arm,psci-1.0", "arm,psci-0.2"; 89 method = "smc"; 90 }; 91 92 /* External SCIF clock - to be overridden by boards that provide it */ 93 scif_clk: scif { 94 compatible = "fixed-clock"; 95 #clock-cells = <0>; 96 clock-frequency = <0>; 97 }; 98 99 soc { 100 compatible = "simple-bus"; 101 interrupt-parent = <&gic>; 102 103 #address-cells = <2>; 104 #size-cells = <2>; 105 ranges; 106 107 rwdt: watchdog@e6020000 { 108 compatible = "renesas,r8a77970-wdt", 109 "renesas,rcar-gen3-wdt"; 110 reg = <0 0xe6020000 0 0x0c>; 111 clocks = <&cpg CPG_MOD 402>; 112 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 113 resets = <&cpg 402>; 114 status = "disabled"; 115 }; 116 117 gpio0: gpio@e6050000 { 118 compatible = "renesas,gpio-r8a77970", 119 "renesas,rcar-gen3-gpio"; 120 reg = <0 0xe6050000 0 0x50>; 121 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 122 #gpio-cells = <2>; 123 gpio-controller; 124 gpio-ranges = <&pfc 0 0 22>; 125 #interrupt-cells = <2>; 126 interrupt-controller; 127 clocks = <&cpg CPG_MOD 912>; 128 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 129 resets = <&cpg 912>; 130 }; 131 132 gpio1: gpio@e6051000 { 133 compatible = "renesas,gpio-r8a77970", 134 "renesas,rcar-gen3-gpio"; 135 reg = <0 0xe6051000 0 0x50>; 136 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 137 #gpio-cells = <2>; 138 gpio-controller; 139 gpio-ranges = <&pfc 0 32 28>; 140 #interrupt-cells = <2>; 141 interrupt-controller; 142 clocks = <&cpg CPG_MOD 911>; 143 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 144 resets = <&cpg 911>; 145 }; 146 147 gpio2: gpio@e6052000 { 148 compatible = "renesas,gpio-r8a77970", 149 "renesas,rcar-gen3-gpio"; 150 reg = <0 0xe6052000 0 0x50>; 151 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 152 #gpio-cells = <2>; 153 gpio-controller; 154 gpio-ranges = <&pfc 0 64 17>; 155 #interrupt-cells = <2>; 156 interrupt-controller; 157 clocks = <&cpg CPG_MOD 910>; 158 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 159 resets = <&cpg 910>; 160 }; 161 162 gpio3: gpio@e6053000 { 163 compatible = "renesas,gpio-r8a77970", 164 "renesas,rcar-gen3-gpio"; 165 reg = <0 0xe6053000 0 0x50>; 166 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 167 #gpio-cells = <2>; 168 gpio-controller; 169 gpio-ranges = <&pfc 0 96 17>; 170 #interrupt-cells = <2>; 171 interrupt-controller; 172 clocks = <&cpg CPG_MOD 909>; 173 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 174 resets = <&cpg 909>; 175 }; 176 177 gpio4: gpio@e6054000 { 178 compatible = "renesas,gpio-r8a77970", 179 "renesas,rcar-gen3-gpio"; 180 reg = <0 0xe6054000 0 0x50>; 181 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 182 #gpio-cells = <2>; 183 gpio-controller; 184 gpio-ranges = <&pfc 0 128 6>; 185 #interrupt-cells = <2>; 186 interrupt-controller; 187 clocks = <&cpg CPG_MOD 908>; 188 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 189 resets = <&cpg 908>; 190 }; 191 192 gpio5: gpio@e6055000 { 193 compatible = "renesas,gpio-r8a77970", 194 "renesas,rcar-gen3-gpio"; 195 reg = <0 0xe6055000 0 0x50>; 196 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 197 #gpio-cells = <2>; 198 gpio-controller; 199 gpio-ranges = <&pfc 0 160 15>; 200 #interrupt-cells = <2>; 201 interrupt-controller; 202 clocks = <&cpg CPG_MOD 907>; 203 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 204 resets = <&cpg 907>; 205 }; 206 207 pfc: pinctrl@e6060000 { 208 compatible = "renesas,pfc-r8a77970"; 209 reg = <0 0xe6060000 0 0x504>; 210 }; 211 212 cmt0: timer@e60f0000 { 213 compatible = "renesas,r8a77970-cmt0", 214 "renesas,rcar-gen3-cmt0"; 215 reg = <0 0xe60f0000 0 0x1004>; 216 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&cpg CPG_MOD 303>; 219 clock-names = "fck"; 220 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 221 resets = <&cpg 303>; 222 status = "disabled"; 223 }; 224 225 cmt1: timer@e6130000 { 226 compatible = "renesas,r8a77970-cmt1", 227 "renesas,rcar-gen3-cmt1"; 228 reg = <0 0xe6130000 0 0x1004>; 229 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&cpg CPG_MOD 302>; 238 clock-names = "fck"; 239 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 240 resets = <&cpg 302>; 241 status = "disabled"; 242 }; 243 244 cmt2: timer@e6140000 { 245 compatible = "renesas,r8a77970-cmt1", 246 "renesas,rcar-gen3-cmt1"; 247 reg = <0 0xe6140000 0 0x1004>; 248 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&cpg CPG_MOD 301>; 257 clock-names = "fck"; 258 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 259 resets = <&cpg 301>; 260 status = "disabled"; 261 }; 262 263 cmt3: timer@e6148000 { 264 compatible = "renesas,r8a77970-cmt1", 265 "renesas,rcar-gen3-cmt1"; 266 reg = <0 0xe6148000 0 0x1004>; 267 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&cpg CPG_MOD 300>; 276 clock-names = "fck"; 277 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 278 resets = <&cpg 300>; 279 status = "disabled"; 280 }; 281 282 cpg: clock-controller@e6150000 { 283 compatible = "renesas,r8a77970-cpg-mssr"; 284 reg = <0 0xe6150000 0 0x1000>; 285 clocks = <&extal_clk>, <&extalr_clk>; 286 clock-names = "extal", "extalr"; 287 #clock-cells = <2>; 288 #power-domain-cells = <0>; 289 #reset-cells = <1>; 290 }; 291 292 rst: reset-controller@e6160000 { 293 compatible = "renesas,r8a77970-rst"; 294 reg = <0 0xe6160000 0 0x200>; 295 }; 296 297 sysc: system-controller@e6180000 { 298 compatible = "renesas,r8a77970-sysc"; 299 reg = <0 0xe6180000 0 0x440>; 300 #power-domain-cells = <1>; 301 }; 302 303 thermal: thermal@e6190000 { 304 compatible = "renesas,thermal-r8a77970"; 305 reg = <0 0xe6190000 0 0x10>, 306 <0 0xe6190100 0 0x120>; 307 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&cpg CPG_MOD 522>; 311 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 312 resets = <&cpg 522>; 313 #thermal-sensor-cells = <0>; 314 }; 315 316 intc_ex: interrupt-controller@e61c0000 { 317 compatible = "renesas,intc-ex-r8a77970", "renesas,irqc"; 318 #interrupt-cells = <2>; 319 interrupt-controller; 320 reg = <0 0xe61c0000 0 0x200>; 321 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&cpg CPG_MOD 407>; 328 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 329 resets = <&cpg 407>; 330 }; 331 332 tmu0: timer@e61e0000 { 333 compatible = "renesas,tmu-r8a77970", "renesas,tmu"; 334 reg = <0 0xe61e0000 0 0x30>; 335 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&cpg CPG_MOD 125>; 339 clock-names = "fck"; 340 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 341 resets = <&cpg 125>; 342 status = "disabled"; 343 }; 344 345 tmu1: timer@e6fc0000 { 346 compatible = "renesas,tmu-r8a77970", "renesas,tmu"; 347 reg = <0 0xe6fc0000 0 0x30>; 348 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&cpg CPG_MOD 124>; 352 clock-names = "fck"; 353 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 354 resets = <&cpg 124>; 355 status = "disabled"; 356 }; 357 358 tmu2: timer@e6fd0000 { 359 compatible = "renesas,tmu-r8a77970", "renesas,tmu"; 360 reg = <0 0xe6fd0000 0 0x30>; 361 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&cpg CPG_MOD 123>; 365 clock-names = "fck"; 366 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 367 resets = <&cpg 123>; 368 status = "disabled"; 369 }; 370 371 tmu3: timer@e6fe0000 { 372 compatible = "renesas,tmu-r8a77970", "renesas,tmu"; 373 reg = <0 0xe6fe0000 0 0x30>; 374 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&cpg CPG_MOD 122>; 378 clock-names = "fck"; 379 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 380 resets = <&cpg 122>; 381 status = "disabled"; 382 }; 383 384 tmu4: timer@ffc00000 { 385 compatible = "renesas,tmu-r8a77970", "renesas,tmu"; 386 reg = <0 0xffc00000 0 0x30>; 387 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&cpg CPG_MOD 121>; 391 clock-names = "fck"; 392 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 393 resets = <&cpg 121>; 394 status = "disabled"; 395 }; 396 397 i2c0: i2c@e6500000 { 398 compatible = "renesas,i2c-r8a77970", 399 "renesas,rcar-gen3-i2c"; 400 reg = <0 0xe6500000 0 0x40>; 401 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&cpg CPG_MOD 931>; 403 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 404 resets = <&cpg 931>; 405 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 406 <&dmac2 0x91>, <&dmac2 0x90>; 407 dma-names = "tx", "rx", "tx", "rx"; 408 i2c-scl-internal-delay-ns = <6>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 status = "disabled"; 412 }; 413 414 i2c1: i2c@e6508000 { 415 compatible = "renesas,i2c-r8a77970", 416 "renesas,rcar-gen3-i2c"; 417 reg = <0 0xe6508000 0 0x40>; 418 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&cpg CPG_MOD 930>; 420 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 421 resets = <&cpg 930>; 422 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 423 <&dmac2 0x93>, <&dmac2 0x92>; 424 dma-names = "tx", "rx", "tx", "rx"; 425 i2c-scl-internal-delay-ns = <6>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 status = "disabled"; 429 }; 430 431 i2c2: i2c@e6510000 { 432 compatible = "renesas,i2c-r8a77970", 433 "renesas,rcar-gen3-i2c"; 434 reg = <0 0xe6510000 0 0x40>; 435 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 436 clocks = <&cpg CPG_MOD 929>; 437 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 438 resets = <&cpg 929>; 439 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 440 <&dmac2 0x95>, <&dmac2 0x94>; 441 dma-names = "tx", "rx", "tx", "rx"; 442 i2c-scl-internal-delay-ns = <6>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 status = "disabled"; 446 }; 447 448 i2c3: i2c@e66d0000 { 449 compatible = "renesas,i2c-r8a77970", 450 "renesas,rcar-gen3-i2c"; 451 reg = <0 0xe66d0000 0 0x40>; 452 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&cpg CPG_MOD 928>; 454 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 455 resets = <&cpg 928>; 456 dmas = <&dmac1 0x97>, <&dmac1 0x96>, 457 <&dmac2 0x97>, <&dmac2 0x96>; 458 dma-names = "tx", "rx", "tx", "rx"; 459 i2c-scl-internal-delay-ns = <6>; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 status = "disabled"; 463 }; 464 465 i2c4: i2c@e66d8000 { 466 compatible = "renesas,i2c-r8a77970", 467 "renesas,rcar-gen3-i2c"; 468 reg = <0 0xe66d8000 0 0x40>; 469 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&cpg CPG_MOD 927>; 471 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 472 resets = <&cpg 927>; 473 dmas = <&dmac1 0x99>, <&dmac1 0x98>, 474 <&dmac2 0x99>, <&dmac2 0x98>; 475 dma-names = "tx", "rx", "tx", "rx"; 476 i2c-scl-internal-delay-ns = <6>; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 status = "disabled"; 480 }; 481 482 hscif0: serial@e6540000 { 483 compatible = "renesas,hscif-r8a77970", 484 "renesas,rcar-gen3-hscif", 485 "renesas,hscif"; 486 reg = <0 0xe6540000 0 96>; 487 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&cpg CPG_MOD 520>, 489 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 490 <&scif_clk>; 491 clock-names = "fck", "brg_int", "scif_clk"; 492 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 493 <&dmac2 0x31>, <&dmac2 0x30>; 494 dma-names = "tx", "rx", "tx", "rx"; 495 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 496 resets = <&cpg 520>; 497 status = "disabled"; 498 }; 499 500 hscif1: serial@e6550000 { 501 compatible = "renesas,hscif-r8a77970", 502 "renesas,rcar-gen3-hscif", 503 "renesas,hscif"; 504 reg = <0 0xe6550000 0 96>; 505 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&cpg CPG_MOD 519>, 507 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 508 <&scif_clk>; 509 clock-names = "fck", "brg_int", "scif_clk"; 510 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 511 <&dmac2 0x33>, <&dmac2 0x32>; 512 dma-names = "tx", "rx", "tx", "rx"; 513 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 514 resets = <&cpg 519>; 515 status = "disabled"; 516 }; 517 518 hscif2: serial@e6560000 { 519 compatible = "renesas,hscif-r8a77970", 520 "renesas,rcar-gen3-hscif", 521 "renesas,hscif"; 522 reg = <0 0xe6560000 0 96>; 523 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&cpg CPG_MOD 518>, 525 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 526 <&scif_clk>; 527 clock-names = "fck", "brg_int", "scif_clk"; 528 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 529 <&dmac2 0x35>, <&dmac2 0x34>; 530 dma-names = "tx", "rx", "tx", "rx"; 531 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 532 resets = <&cpg 518>; 533 status = "disabled"; 534 }; 535 536 hscif3: serial@e66a0000 { 537 compatible = "renesas,hscif-r8a77970", 538 "renesas,rcar-gen3-hscif", "renesas,hscif"; 539 reg = <0 0xe66a0000 0 96>; 540 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&cpg CPG_MOD 517>, 542 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 543 <&scif_clk>; 544 clock-names = "fck", "brg_int", "scif_clk"; 545 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 546 <&dmac2 0x37>, <&dmac2 0x36>; 547 dma-names = "tx", "rx", "tx", "rx"; 548 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 549 resets = <&cpg 517>; 550 status = "disabled"; 551 }; 552 553 canfd: can@e66c0000 { 554 compatible = "renesas,r8a77970-canfd", 555 "renesas,rcar-gen3-canfd"; 556 reg = <0 0xe66c0000 0 0x8000>; 557 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&cpg CPG_MOD 914>, 560 <&cpg CPG_CORE R8A77970_CLK_CANFD>, 561 <&can_clk>; 562 clock-names = "fck", "canfd", "can_clk"; 563 assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>; 564 assigned-clock-rates = <40000000>; 565 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 566 resets = <&cpg 914>; 567 status = "disabled"; 568 569 channel0 { 570 status = "disabled"; 571 }; 572 573 channel1 { 574 status = "disabled"; 575 }; 576 }; 577 578 avb: ethernet@e6800000 { 579 compatible = "renesas,etheravb-r8a77970", 580 "renesas,etheravb-rcar-gen3"; 581 reg = <0 0xe6800000 0 0x800>; 582 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 607 interrupt-names = "ch0", "ch1", "ch2", "ch3", 608 "ch4", "ch5", "ch6", "ch7", 609 "ch8", "ch9", "ch10", "ch11", 610 "ch12", "ch13", "ch14", "ch15", 611 "ch16", "ch17", "ch18", "ch19", 612 "ch20", "ch21", "ch22", "ch23", 613 "ch24"; 614 clocks = <&cpg CPG_MOD 812>; 615 clock-names = "fck"; 616 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 617 resets = <&cpg 812>; 618 phy-mode = "rgmii"; 619 rx-internal-delay-ps = <0>; 620 tx-internal-delay-ps = <0>; 621 iommus = <&ipmmu_rt 3>; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 status = "disabled"; 625 }; 626 627 pwm0: pwm@e6e30000 { 628 compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; 629 reg = <0 0xe6e30000 0 8>; 630 #pwm-cells = <2>; 631 clocks = <&cpg CPG_MOD 523>; 632 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 633 resets = <&cpg 523>; 634 status = "disabled"; 635 }; 636 637 pwm1: pwm@e6e31000 { 638 compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; 639 reg = <0 0xe6e31000 0 8>; 640 #pwm-cells = <2>; 641 clocks = <&cpg CPG_MOD 523>; 642 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 643 resets = <&cpg 523>; 644 status = "disabled"; 645 }; 646 647 pwm2: pwm@e6e32000 { 648 compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; 649 reg = <0 0xe6e32000 0 8>; 650 #pwm-cells = <2>; 651 clocks = <&cpg CPG_MOD 523>; 652 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 653 resets = <&cpg 523>; 654 status = "disabled"; 655 }; 656 657 pwm3: pwm@e6e33000 { 658 compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; 659 reg = <0 0xe6e33000 0 8>; 660 #pwm-cells = <2>; 661 clocks = <&cpg CPG_MOD 523>; 662 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 663 resets = <&cpg 523>; 664 status = "disabled"; 665 }; 666 667 pwm4: pwm@e6e34000 { 668 compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; 669 reg = <0 0xe6e34000 0 8>; 670 #pwm-cells = <2>; 671 clocks = <&cpg CPG_MOD 523>; 672 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 673 resets = <&cpg 523>; 674 status = "disabled"; 675 }; 676 677 scif0: serial@e6e60000 { 678 compatible = "renesas,scif-r8a77970", 679 "renesas,rcar-gen3-scif", 680 "renesas,scif"; 681 reg = <0 0xe6e60000 0 64>; 682 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&cpg CPG_MOD 207>, 684 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 685 <&scif_clk>; 686 clock-names = "fck", "brg_int", "scif_clk"; 687 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 688 <&dmac2 0x51>, <&dmac2 0x50>; 689 dma-names = "tx", "rx", "tx", "rx"; 690 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 691 resets = <&cpg 207>; 692 status = "disabled"; 693 }; 694 695 scif1: serial@e6e68000 { 696 compatible = "renesas,scif-r8a77970", 697 "renesas,rcar-gen3-scif", 698 "renesas,scif"; 699 reg = <0 0xe6e68000 0 64>; 700 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&cpg CPG_MOD 206>, 702 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 703 <&scif_clk>; 704 clock-names = "fck", "brg_int", "scif_clk"; 705 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 706 <&dmac2 0x53>, <&dmac2 0x52>; 707 dma-names = "tx", "rx", "tx", "rx"; 708 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 709 resets = <&cpg 206>; 710 status = "disabled"; 711 }; 712 713 scif3: serial@e6c50000 { 714 compatible = "renesas,scif-r8a77970", 715 "renesas,rcar-gen3-scif", 716 "renesas,scif"; 717 reg = <0 0xe6c50000 0 64>; 718 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&cpg CPG_MOD 204>, 720 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 721 <&scif_clk>; 722 clock-names = "fck", "brg_int", "scif_clk"; 723 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 724 <&dmac2 0x57>, <&dmac2 0x56>; 725 dma-names = "tx", "rx", "tx", "rx"; 726 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 727 resets = <&cpg 204>; 728 status = "disabled"; 729 }; 730 731 scif4: serial@e6c40000 { 732 compatible = "renesas,scif-r8a77970", 733 "renesas,rcar-gen3-scif", "renesas,scif"; 734 reg = <0 0xe6c40000 0 64>; 735 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&cpg CPG_MOD 203>, 737 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 738 <&scif_clk>; 739 clock-names = "fck", "brg_int", "scif_clk"; 740 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 741 <&dmac2 0x59>, <&dmac2 0x58>; 742 dma-names = "tx", "rx", "tx", "rx"; 743 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 744 resets = <&cpg 203>; 745 status = "disabled"; 746 }; 747 748 tpu: pwm@e6e80000 { 749 compatible = "renesas,tpu-r8a77970", "renesas,tpu"; 750 reg = <0 0xe6e80000 0 0x148>; 751 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 752 clocks = <&cpg CPG_MOD 304>; 753 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 754 resets = <&cpg 304>; 755 #pwm-cells = <3>; 756 status = "disabled"; 757 }; 758 759 msiof0: spi@e6e90000 { 760 compatible = "renesas,msiof-r8a77970", 761 "renesas,rcar-gen3-msiof"; 762 reg = <0 0xe6e90000 0 0x64>; 763 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&cpg CPG_MOD 211>; 765 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 766 resets = <&cpg 211>; 767 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 768 <&dmac2 0x41>, <&dmac2 0x40>; 769 dma-names = "tx", "rx", "tx", "rx"; 770 #address-cells = <1>; 771 #size-cells = <0>; 772 status = "disabled"; 773 }; 774 775 msiof1: spi@e6ea0000 { 776 compatible = "renesas,msiof-r8a77970", 777 "renesas,rcar-gen3-msiof"; 778 reg = <0 0xe6ea0000 0 0x0064>; 779 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&cpg CPG_MOD 210>; 781 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 782 resets = <&cpg 210>; 783 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 784 <&dmac2 0x43>, <&dmac2 0x42>; 785 dma-names = "tx", "rx", "tx", "rx"; 786 #address-cells = <1>; 787 #size-cells = <0>; 788 status = "disabled"; 789 }; 790 791 msiof2: spi@e6c00000 { 792 compatible = "renesas,msiof-r8a77970", 793 "renesas,rcar-gen3-msiof"; 794 reg = <0 0xe6c00000 0 0x0064>; 795 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&cpg CPG_MOD 209>; 797 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 798 resets = <&cpg 209>; 799 dmas = <&dmac1 0x45>, <&dmac1 0x44>, 800 <&dmac2 0x45>, <&dmac2 0x44>; 801 dma-names = "tx", "rx", "tx", "rx"; 802 #address-cells = <1>; 803 #size-cells = <0>; 804 status = "disabled"; 805 }; 806 807 msiof3: spi@e6c10000 { 808 compatible = "renesas,msiof-r8a77970", 809 "renesas,rcar-gen3-msiof"; 810 reg = <0 0xe6c10000 0 0x0064>; 811 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&cpg CPG_MOD 208>; 813 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 814 resets = <&cpg 208>; 815 dmas = <&dmac1 0x47>, <&dmac1 0x46>, 816 <&dmac2 0x47>, <&dmac2 0x46>; 817 dma-names = "tx", "rx", "tx", "rx"; 818 #address-cells = <1>; 819 #size-cells = <0>; 820 status = "disabled"; 821 }; 822 823 vin0: video@e6ef0000 { 824 compatible = "renesas,vin-r8a77970"; 825 reg = <0 0xe6ef0000 0 0x1000>; 826 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 827 clocks = <&cpg CPG_MOD 811>; 828 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 829 resets = <&cpg 811>; 830 renesas,id = <0>; 831 status = "disabled"; 832 833 ports { 834 #address-cells = <1>; 835 #size-cells = <0>; 836 837 port@1 { 838 #address-cells = <1>; 839 #size-cells = <0>; 840 841 reg = <1>; 842 843 vin0csi40: endpoint@2 { 844 reg = <2>; 845 remote-endpoint = <&csi40vin0>; 846 }; 847 }; 848 }; 849 }; 850 851 vin1: video@e6ef1000 { 852 compatible = "renesas,vin-r8a77970"; 853 reg = <0 0xe6ef1000 0 0x1000>; 854 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&cpg CPG_MOD 810>; 856 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 857 resets = <&cpg 810>; 858 renesas,id = <1>; 859 status = "disabled"; 860 861 ports { 862 #address-cells = <1>; 863 #size-cells = <0>; 864 865 port@1 { 866 #address-cells = <1>; 867 #size-cells = <0>; 868 869 reg = <1>; 870 871 vin1csi40: endpoint@2 { 872 reg = <2>; 873 remote-endpoint = <&csi40vin1>; 874 }; 875 }; 876 }; 877 }; 878 879 vin2: video@e6ef2000 { 880 compatible = "renesas,vin-r8a77970"; 881 reg = <0 0xe6ef2000 0 0x1000>; 882 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 883 clocks = <&cpg CPG_MOD 809>; 884 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 885 resets = <&cpg 809>; 886 renesas,id = <2>; 887 status = "disabled"; 888 889 ports { 890 #address-cells = <1>; 891 #size-cells = <0>; 892 893 port@1 { 894 #address-cells = <1>; 895 #size-cells = <0>; 896 897 reg = <1>; 898 899 vin2csi40: endpoint@2 { 900 reg = <2>; 901 remote-endpoint = <&csi40vin2>; 902 }; 903 }; 904 }; 905 }; 906 907 vin3: video@e6ef3000 { 908 compatible = "renesas,vin-r8a77970"; 909 reg = <0 0xe6ef3000 0 0x1000>; 910 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&cpg CPG_MOD 808>; 912 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 913 resets = <&cpg 808>; 914 renesas,id = <3>; 915 status = "disabled"; 916 917 ports { 918 #address-cells = <1>; 919 #size-cells = <0>; 920 921 port@1 { 922 #address-cells = <1>; 923 #size-cells = <0>; 924 925 reg = <1>; 926 927 vin3csi40: endpoint@2 { 928 reg = <2>; 929 remote-endpoint = <&csi40vin3>; 930 }; 931 }; 932 }; 933 }; 934 935 dmac1: dma-controller@e7300000 { 936 compatible = "renesas,dmac-r8a77970", 937 "renesas,rcar-dmac"; 938 reg = <0 0xe7300000 0 0x10000>; 939 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 948 interrupt-names = "error", 949 "ch0", "ch1", "ch2", "ch3", 950 "ch4", "ch5", "ch6", "ch7"; 951 clocks = <&cpg CPG_MOD 218>; 952 clock-names = "fck"; 953 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 954 resets = <&cpg 218>; 955 #dma-cells = <1>; 956 dma-channels = <8>; 957 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 958 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 959 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 960 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; 961 }; 962 963 dmac2: dma-controller@e7310000 { 964 compatible = "renesas,dmac-r8a77970", 965 "renesas,rcar-dmac"; 966 reg = <0 0xe7310000 0 0x10000>; 967 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 976 interrupt-names = "error", 977 "ch0", "ch1", "ch2", "ch3", 978 "ch4", "ch5", "ch6", "ch7"; 979 clocks = <&cpg CPG_MOD 217>; 980 clock-names = "fck"; 981 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 982 resets = <&cpg 217>; 983 #dma-cells = <1>; 984 dma-channels = <8>; 985 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 986 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 987 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 988 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; 989 }; 990 991 ipmmu_ds1: iommu@e7740000 { 992 compatible = "renesas,ipmmu-r8a77970"; 993 reg = <0 0xe7740000 0 0x1000>; 994 renesas,ipmmu-main = <&ipmmu_mm 0>; 995 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 996 #iommu-cells = <1>; 997 }; 998 999 ipmmu_ir: iommu@ff8b0000 { 1000 compatible = "renesas,ipmmu-r8a77970"; 1001 reg = <0 0xff8b0000 0 0x1000>; 1002 renesas,ipmmu-main = <&ipmmu_mm 3>; 1003 power-domains = <&sysc R8A77970_PD_A3IR>; 1004 #iommu-cells = <1>; 1005 }; 1006 1007 ipmmu_mm: iommu@e67b0000 { 1008 compatible = "renesas,ipmmu-r8a77970"; 1009 reg = <0 0xe67b0000 0 0x1000>; 1010 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1011 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1012 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1013 #iommu-cells = <1>; 1014 }; 1015 1016 ipmmu_rt: iommu@ffc80000 { 1017 compatible = "renesas,ipmmu-r8a77970"; 1018 reg = <0 0xffc80000 0 0x1000>; 1019 renesas,ipmmu-main = <&ipmmu_mm 7>; 1020 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1021 #iommu-cells = <1>; 1022 }; 1023 1024 ipmmu_vi0: iommu@febd0000 { 1025 compatible = "renesas,ipmmu-r8a77970"; 1026 reg = <0 0xfebd0000 0 0x1000>; 1027 renesas,ipmmu-main = <&ipmmu_mm 9>; 1028 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1029 #iommu-cells = <1>; 1030 }; 1031 1032 mmc0: mmc@ee140000 { 1033 compatible = "renesas,sdhi-r8a77970", 1034 "renesas,rcar-gen3-sdhi"; 1035 reg = <0 0xee140000 0 0x2000>; 1036 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1037 clocks = <&cpg CPG_MOD 314>; 1038 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1039 resets = <&cpg 314>; 1040 max-frequency = <200000000>; 1041 iommus = <&ipmmu_ds1 32>; 1042 status = "disabled"; 1043 }; 1044 1045 rpc: spi@ee200000 { 1046 compatible = "renesas,r8a77970-rpc-if", 1047 "renesas,rcar-gen3-rpc-if"; 1048 reg = <0 0xee200000 0 0x200>, 1049 <0 0x08000000 0 0x4000000>, 1050 <0 0xee208000 0 0x100>; 1051 reg-names = "regs", "dirmap", "wbuf"; 1052 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1053 clocks = <&cpg CPG_MOD 917>; 1054 clock-names = "rpc"; 1055 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1056 resets = <&cpg 917>; 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 status = "disabled"; 1060 }; 1061 1062 gic: interrupt-controller@f1010000 { 1063 compatible = "arm,gic-400"; 1064 #interrupt-cells = <3>; 1065 #address-cells = <0>; 1066 interrupt-controller; 1067 reg = <0 0xf1010000 0 0x1000>, 1068 <0 0xf1020000 0 0x20000>, 1069 <0 0xf1040000 0 0x20000>, 1070 <0 0xf1060000 0 0x20000>; 1071 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 1072 IRQ_TYPE_LEVEL_HIGH)>; 1073 clocks = <&cpg CPG_MOD 408>; 1074 clock-names = "clk"; 1075 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1076 resets = <&cpg 408>; 1077 }; 1078 1079 vspd0: vsp@fea20000 { 1080 compatible = "renesas,vsp2"; 1081 reg = <0 0xfea20000 0 0x5000>; 1082 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1083 clocks = <&cpg CPG_MOD 623>; 1084 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1085 resets = <&cpg 623>; 1086 renesas,fcp = <&fcpvd0>; 1087 }; 1088 1089 fcpvd0: fcp@fea27000 { 1090 compatible = "renesas,fcpv"; 1091 reg = <0 0xfea27000 0 0x200>; 1092 clocks = <&cpg CPG_MOD 603>; 1093 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1094 resets = <&cpg 603>; 1095 }; 1096 1097 csi40: csi2@feaa0000 { 1098 compatible = "renesas,r8a77970-csi2"; 1099 reg = <0 0xfeaa0000 0 0x10000>; 1100 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1101 clocks = <&cpg CPG_MOD 716>; 1102 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1103 resets = <&cpg 716>; 1104 status = "disabled"; 1105 1106 ports { 1107 #address-cells = <1>; 1108 #size-cells = <0>; 1109 1110 port@0 { 1111 reg = <0>; 1112 }; 1113 1114 port@1 { 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 1118 reg = <1>; 1119 1120 csi40vin0: endpoint@0 { 1121 reg = <0>; 1122 remote-endpoint = <&vin0csi40>; 1123 }; 1124 csi40vin1: endpoint@1 { 1125 reg = <1>; 1126 remote-endpoint = <&vin1csi40>; 1127 }; 1128 csi40vin2: endpoint@2 { 1129 reg = <2>; 1130 remote-endpoint = <&vin2csi40>; 1131 }; 1132 csi40vin3: endpoint@3 { 1133 reg = <3>; 1134 remote-endpoint = <&vin3csi40>; 1135 }; 1136 }; 1137 }; 1138 }; 1139 1140 du: display@feb00000 { 1141 compatible = "renesas,du-r8a77970"; 1142 reg = <0 0xfeb00000 0 0x80000>; 1143 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1144 clocks = <&cpg CPG_MOD 724>; 1145 clock-names = "du.0"; 1146 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1147 resets = <&cpg 724>; 1148 reset-names = "du.0"; 1149 renesas,vsps = <&vspd0 0>; 1150 1151 status = "disabled"; 1152 1153 ports { 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 1157 port@0 { 1158 reg = <0>; 1159 du_out_rgb: endpoint { 1160 }; 1161 }; 1162 1163 port@1 { 1164 reg = <1>; 1165 du_out_lvds0: endpoint { 1166 remote-endpoint = <&lvds0_in>; 1167 }; 1168 }; 1169 }; 1170 }; 1171 1172 lvds0: lvds-encoder@feb90000 { 1173 compatible = "renesas,r8a77970-lvds"; 1174 reg = <0 0xfeb90000 0 0x14>; 1175 clocks = <&cpg CPG_MOD 727>; 1176 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1177 resets = <&cpg 727>; 1178 status = "disabled"; 1179 1180 ports { 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 1184 port@0 { 1185 reg = <0>; 1186 lvds0_in: endpoint { 1187 remote-endpoint = 1188 <&du_out_lvds0>; 1189 }; 1190 }; 1191 port@1 { 1192 reg = <1>; 1193 lvds0_out: endpoint { 1194 }; 1195 }; 1196 }; 1197 }; 1198 1199 prr: chipid@fff00044 { 1200 compatible = "renesas,prr"; 1201 reg = <0 0xfff00044 0 4>; 1202 }; 1203 }; 1204 1205 thermal-zones { 1206 cpu-thermal { 1207 polling-delay-passive = <250>; 1208 polling-delay = <1000>; 1209 thermal-sensors = <&thermal>; 1210 1211 cooling-maps { 1212 }; 1213 1214 trips { 1215 cpu-crit { 1216 temperature = <120000>; 1217 hysteresis = <2000>; 1218 type = "critical"; 1219 }; 1220 }; 1221 }; 1222 }; 1223 1224 timer { 1225 compatible = "arm,armv8-timer"; 1226 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1227 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1228 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1229 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 1230 }; 1231}; 1232