1/* 2 * Device Tree Source for the r8a77970 SoC 3 * 4 * Copyright (C) 2016-2017 Renesas Electronics Corp. 5 * Copyright (C) 2017 Cogent Embedded, Inc. 6 * 7 * This file is licensed under the terms of the GNU General Public License 8 * version 2. This program is licensed "as is" without any warranty of any 9 * kind, whether express or implied. 10 */ 11 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/clock/renesas-cpg-mssr.h> 15 16/ { 17 compatible = "renesas,r8a77970"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 psci { 22 compatible = "arm,psci-1.0", "arm,psci-0.2"; 23 method = "smc"; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 a53_0: cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a53", "arm,armv8"; 33 reg = <0>; 34 clocks = <&cpg CPG_CORE 0>; 35 power-domains = <&sysc 5>; 36 next-level-cache = <&L2_CA53>; 37 enable-method = "psci"; 38 }; 39 40 L2_CA53: cache-controller { 41 compatible = "cache"; 42 power-domains = <&sysc 21>; 43 cache-unified; 44 cache-level = <2>; 45 }; 46 }; 47 48 extal_clk: extal { 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; 51 /* This value must be overridden by the board */ 52 clock-frequency = <0>; 53 }; 54 55 extalr_clk: extalr { 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 /* This value must be overridden by the board */ 59 clock-frequency = <0>; 60 }; 61 62 /* External SCIF clock - to be overridden by boards that provide it */ 63 scif_clk: scif { 64 compatible = "fixed-clock"; 65 #clock-cells = <0>; 66 clock-frequency = <0>; 67 }; 68 69 soc { 70 compatible = "simple-bus"; 71 interrupt-parent = <&gic>; 72 73 #address-cells = <2>; 74 #size-cells = <2>; 75 ranges; 76 77 gic: interrupt-controller@f1010000 { 78 compatible = "arm,gic-400"; 79 #interrupt-cells = <3>; 80 #address-cells = <0>; 81 interrupt-controller; 82 reg = <0 0xf1010000 0 0x1000>, 83 <0 0xf1020000 0 0x20000>, 84 <0 0xf1040000 0 0x20000>, 85 <0 0xf1060000 0 0x20000>; 86 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | 87 IRQ_TYPE_LEVEL_HIGH)>; 88 clocks = <&cpg CPG_MOD 408>; 89 clock-names = "clk"; 90 power-domains = <&sysc 32>; 91 resets = <&cpg 408>; 92 }; 93 94 timer { 95 compatible = "arm,armv8-timer"; 96 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | 97 IRQ_TYPE_LEVEL_LOW)>, 98 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | 99 IRQ_TYPE_LEVEL_LOW)>, 100 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | 101 IRQ_TYPE_LEVEL_LOW)>, 102 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | 103 IRQ_TYPE_LEVEL_LOW)>; 104 }; 105 106 cpg: clock-controller@e6150000 { 107 compatible = "renesas,r8a77970-cpg-mssr"; 108 reg = <0 0xe6150000 0 0x1000>; 109 clocks = <&extal_clk>, <&extalr_clk>; 110 clock-names = "extal", "extalr"; 111 #clock-cells = <2>; 112 #power-domain-cells = <0>; 113 #reset-cells = <1>; 114 }; 115 116 rst: reset-controller@e6160000 { 117 compatible = "renesas,r8a77970-rst"; 118 reg = <0 0xe6160000 0 0x200>; 119 }; 120 121 sysc: system-controller@e6180000 { 122 compatible = "renesas,r8a77970-sysc"; 123 reg = <0 0xe6180000 0 0x440>; 124 #power-domain-cells = <1>; 125 }; 126 127 prr: chipid@fff00044 { 128 compatible = "renesas,prr"; 129 reg = <0 0xfff00044 0 4>; 130 }; 131 132 dmac1: dma-controller@e7300000 { 133 compatible = "renesas,dmac-r8a77970", 134 "renesas,rcar-dmac"; 135 reg = <0 0xe7300000 0 0x10000>; 136 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 137 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 138 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 139 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 140 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 141 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 142 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 143 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 144 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 145 interrupt-names = "error", 146 "ch0", "ch1", "ch2", "ch3", 147 "ch4", "ch5", "ch6", "ch7"; 148 clocks = <&cpg CPG_MOD 218>; 149 clock-names = "fck"; 150 power-domains = <&sysc 32>; 151 resets = <&cpg 218>; 152 #dma-cells = <1>; 153 dma-channels = <8>; 154 }; 155 156 dmac2: dma-controller@e7310000 { 157 compatible = "renesas,dmac-r8a77970", 158 "renesas,rcar-dmac"; 159 reg = <0 0xe7310000 0 0x10000>; 160 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 161 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 162 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 163 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 164 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 165 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 166 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 167 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 168 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 169 interrupt-names = "error", 170 "ch0", "ch1", "ch2", "ch3", 171 "ch4", "ch5", "ch6", "ch7"; 172 clocks = <&cpg CPG_MOD 217>; 173 clock-names = "fck"; 174 power-domains = <&sysc 32>; 175 resets = <&cpg 217>; 176 #dma-cells = <1>; 177 dma-channels = <8>; 178 }; 179 180 hscif0: serial@e6540000 { 181 compatible = "renesas,hscif-r8a77970", 182 "renesas,rcar-gen3-hscif", 183 "renesas,hscif"; 184 reg = <0 0xe6540000 0 96>; 185 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 186 clocks = <&cpg CPG_MOD 520>, 187 <&cpg CPG_CORE 9>, 188 <&scif_clk>; 189 clock-names = "fck", "brg_int", "scif_clk"; 190 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 191 <&dmac2 0x31>, <&dmac2 0x30>; 192 dma-names = "tx", "rx", "tx", "rx"; 193 power-domains = <&sysc 32>; 194 resets = <&cpg 520>; 195 status = "disabled"; 196 }; 197 198 hscif1: serial@e6550000 { 199 compatible = "renesas,hscif-r8a77970", 200 "renesas,rcar-gen3-hscif", 201 "renesas,hscif"; 202 reg = <0 0xe6550000 0 96>; 203 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 204 clocks = <&cpg CPG_MOD 519>, 205 <&cpg CPG_CORE 9>, 206 <&scif_clk>; 207 clock-names = "fck", "brg_int", "scif_clk"; 208 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 209 <&dmac2 0x33>, <&dmac2 0x32>; 210 dma-names = "tx", "rx", "tx", "rx"; 211 power-domains = <&sysc 32>; 212 resets = <&cpg 519>; 213 status = "disabled"; 214 }; 215 216 hscif2: serial@e6560000 { 217 compatible = "renesas,hscif-r8a77970", 218 "renesas,rcar-gen3-hscif", 219 "renesas,hscif"; 220 reg = <0 0xe6560000 0 96>; 221 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&cpg CPG_MOD 518>, 223 <&cpg CPG_CORE 9>, 224 <&scif_clk>; 225 clock-names = "fck", "brg_int", "scif_clk"; 226 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 227 <&dmac2 0x35>, <&dmac2 0x34>; 228 dma-names = "tx", "rx", "tx", "rx"; 229 power-domains = <&sysc 32>; 230 resets = <&cpg 518>; 231 status = "disabled"; 232 }; 233 234 hscif3: serial@e66a0000 { 235 compatible = "renesas,hscif-r8a77970", 236 "renesas,rcar-gen3-hscif", "renesas,hscif"; 237 reg = <0 0xe66a0000 0 96>; 238 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&cpg CPG_MOD 517>, 240 <&cpg CPG_CORE 9>, 241 <&scif_clk>; 242 clock-names = "fck", "brg_int", "scif_clk"; 243 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 244 <&dmac2 0x37>, <&dmac2 0x36>; 245 dma-names = "tx", "rx", "tx", "rx"; 246 power-domains = <&sysc 32>; 247 resets = <&cpg 517>; 248 status = "disabled"; 249 }; 250 251 scif0: serial@e6e60000 { 252 compatible = "renesas,scif-r8a77970", 253 "renesas,rcar-gen3-scif", 254 "renesas,scif"; 255 reg = <0 0xe6e60000 0 64>; 256 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&cpg CPG_MOD 207>, 258 <&cpg CPG_CORE 9>, 259 <&scif_clk>; 260 clock-names = "fck", "brg_int", "scif_clk"; 261 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 262 <&dmac2 0x51>, <&dmac2 0x50>; 263 dma-names = "tx", "rx", "tx", "rx"; 264 power-domains = <&sysc 32>; 265 resets = <&cpg 207>; 266 status = "disabled"; 267 }; 268 269 scif1: serial@e6e68000 { 270 compatible = "renesas,scif-r8a77970", 271 "renesas,rcar-gen3-scif", 272 "renesas,scif"; 273 reg = <0 0xe6e68000 0 64>; 274 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&cpg CPG_MOD 206>, 276 <&cpg CPG_CORE 9>, 277 <&scif_clk>; 278 clock-names = "fck", "brg_int", "scif_clk"; 279 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 280 <&dmac2 0x53>, <&dmac2 0x52>; 281 dma-names = "tx", "rx", "tx", "rx"; 282 power-domains = <&sysc 32>; 283 resets = <&cpg 206>; 284 status = "disabled"; 285 }; 286 287 scif3: serial@e6c50000 { 288 compatible = "renesas,scif-r8a77970", 289 "renesas,rcar-gen3-scif", 290 "renesas,scif"; 291 reg = <0 0xe6c50000 0 64>; 292 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&cpg CPG_MOD 204>, 294 <&cpg CPG_CORE 9>, 295 <&scif_clk>; 296 clock-names = "fck", "brg_int", "scif_clk"; 297 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 298 <&dmac2 0x57>, <&dmac2 0x56>; 299 dma-names = "tx", "rx", "tx", "rx"; 300 power-domains = <&sysc 32>; 301 resets = <&cpg 204>; 302 status = "disabled"; 303 }; 304 305 scif4: serial@e6c40000 { 306 compatible = "renesas,scif-r8a77970", 307 "renesas,rcar-gen3-scif", "renesas,scif"; 308 reg = <0 0xe6c40000 0 64>; 309 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&cpg CPG_MOD 203>, 311 <&cpg CPG_CORE 9>, 312 <&scif_clk>; 313 clock-names = "fck", "brg_int", "scif_clk"; 314 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 315 <&dmac2 0x59>, <&dmac2 0x58>; 316 dma-names = "tx", "rx", "tx", "rx"; 317 power-domains = <&sysc 32>; 318 resets = <&cpg 203>; 319 status = "disabled"; 320 }; 321 }; 322}; 323