1/* 2 * Device Tree Source for the r8a77970 SoC 3 * 4 * Copyright (C) 2016-2017 Renesas Electronics Corp. 5 * Copyright (C) 2017 Cogent Embedded, Inc. 6 * 7 * This file is licensed under the terms of the GNU General Public License 8 * version 2. This program is licensed "as is" without any warranty of any 9 * kind, whether express or implied. 10 */ 11 12#include <dt-bindings/clock/renesas-cpg-mssr.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/power/r8a77970-sysc.h> 16 17/ { 18 compatible = "renesas,r8a77970"; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 psci { 23 compatible = "arm,psci-1.0", "arm,psci-0.2"; 24 method = "smc"; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 a53_0: cpu@0 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a53", "arm,armv8"; 34 reg = <0>; 35 clocks = <&cpg CPG_CORE 0>; 36 power-domains = <&sysc 5>; 37 next-level-cache = <&L2_CA53>; 38 enable-method = "psci"; 39 }; 40 41 L2_CA53: cache-controller { 42 compatible = "cache"; 43 power-domains = <&sysc 21>; 44 cache-unified; 45 cache-level = <2>; 46 }; 47 }; 48 49 extal_clk: extal { 50 compatible = "fixed-clock"; 51 #clock-cells = <0>; 52 /* This value must be overridden by the board */ 53 clock-frequency = <0>; 54 }; 55 56 extalr_clk: extalr { 57 compatible = "fixed-clock"; 58 #clock-cells = <0>; 59 /* This value must be overridden by the board */ 60 clock-frequency = <0>; 61 }; 62 63 /* External SCIF clock - to be overridden by boards that provide it */ 64 scif_clk: scif { 65 compatible = "fixed-clock"; 66 #clock-cells = <0>; 67 clock-frequency = <0>; 68 }; 69 70 soc { 71 compatible = "simple-bus"; 72 interrupt-parent = <&gic>; 73 74 #address-cells = <2>; 75 #size-cells = <2>; 76 ranges; 77 78 gic: interrupt-controller@f1010000 { 79 compatible = "arm,gic-400"; 80 #interrupt-cells = <3>; 81 #address-cells = <0>; 82 interrupt-controller; 83 reg = <0 0xf1010000 0 0x1000>, 84 <0 0xf1020000 0 0x20000>, 85 <0 0xf1040000 0 0x20000>, 86 <0 0xf1060000 0 0x20000>; 87 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | 88 IRQ_TYPE_LEVEL_HIGH)>; 89 clocks = <&cpg CPG_MOD 408>; 90 clock-names = "clk"; 91 power-domains = <&sysc 32>; 92 resets = <&cpg 408>; 93 }; 94 95 timer { 96 compatible = "arm,armv8-timer"; 97 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | 98 IRQ_TYPE_LEVEL_LOW)>, 99 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | 100 IRQ_TYPE_LEVEL_LOW)>, 101 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | 102 IRQ_TYPE_LEVEL_LOW)>, 103 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | 104 IRQ_TYPE_LEVEL_LOW)>; 105 }; 106 107 rwdt: watchdog@e6020000 { 108 compatible = "renesas,r8a77970-wdt", 109 "renesas,rcar-gen3-wdt"; 110 reg = <0 0xe6020000 0 0x0c>; 111 clocks = <&cpg CPG_MOD 402>; 112 power-domains = <&sysc 32>; 113 resets = <&cpg 402>; 114 status = "disabled"; 115 }; 116 117 cpg: clock-controller@e6150000 { 118 compatible = "renesas,r8a77970-cpg-mssr"; 119 reg = <0 0xe6150000 0 0x1000>; 120 clocks = <&extal_clk>, <&extalr_clk>; 121 clock-names = "extal", "extalr"; 122 #clock-cells = <2>; 123 #power-domain-cells = <0>; 124 #reset-cells = <1>; 125 }; 126 127 rst: reset-controller@e6160000 { 128 compatible = "renesas,r8a77970-rst"; 129 reg = <0 0xe6160000 0 0x200>; 130 }; 131 132 sysc: system-controller@e6180000 { 133 compatible = "renesas,r8a77970-sysc"; 134 reg = <0 0xe6180000 0 0x440>; 135 #power-domain-cells = <1>; 136 }; 137 138 ipmmu_vi0: mmu@febd0000 { 139 compatible = "renesas,ipmmu-r8a77970"; 140 reg = <0 0xfebd0000 0 0x1000>; 141 renesas,ipmmu-main = <&ipmmu_mm 9>; 142 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 143 #iommu-cells = <1>; 144 status = "disabled"; 145 }; 146 147 ipmmu_ir: mmu@ff8b0000 { 148 compatible = "renesas,ipmmu-r8a77970"; 149 reg = <0 0xff8b0000 0 0x1000>; 150 renesas,ipmmu-main = <&ipmmu_mm 3>; 151 power-domains = <&sysc R8A77970_PD_A3IR>; 152 #iommu-cells = <1>; 153 status = "disabled"; 154 }; 155 156 ipmmu_rt: mmu@ffc80000 { 157 compatible = "renesas,ipmmu-r8a77970"; 158 reg = <0 0xffc80000 0 0x1000>; 159 renesas,ipmmu-main = <&ipmmu_mm 7>; 160 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 161 #iommu-cells = <1>; 162 status = "disabled"; 163 }; 164 165 ipmmu_ds1: mmu@e7740000 { 166 compatible = "renesas,ipmmu-r8a77970"; 167 reg = <0 0xe7740000 0 0x1000>; 168 renesas,ipmmu-main = <&ipmmu_mm 1>; 169 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 170 #iommu-cells = <1>; 171 status = "disabled"; 172 }; 173 174 ipmmu_mm: mmu@e67b0000 { 175 compatible = "renesas,ipmmu-r8a77970"; 176 reg = <0 0xe67b0000 0 0x1000>; 177 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 179 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 180 #iommu-cells = <1>; 181 status = "disabled"; 182 }; 183 184 intc_ex: interrupt-controller@e61c0000 { 185 compatible = "renesas,intc-ex-r8a77970", "renesas,irqc"; 186 #interrupt-cells = <2>; 187 interrupt-controller; 188 reg = <0 0xe61c0000 0 0x200>; 189 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 190 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 191 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 192 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 193 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 194 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 195 clocks = <&cpg CPG_MOD 407>; 196 power-domains = <&sysc 32>; 197 resets = <&cpg 407>; 198 }; 199 200 prr: chipid@fff00044 { 201 compatible = "renesas,prr"; 202 reg = <0 0xfff00044 0 4>; 203 }; 204 205 dmac1: dma-controller@e7300000 { 206 compatible = "renesas,dmac-r8a77970", 207 "renesas,rcar-dmac"; 208 reg = <0 0xe7300000 0 0x10000>; 209 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 210 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 211 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 212 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 213 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 214 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 215 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 216 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 217 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 218 interrupt-names = "error", 219 "ch0", "ch1", "ch2", "ch3", 220 "ch4", "ch5", "ch6", "ch7"; 221 clocks = <&cpg CPG_MOD 218>; 222 clock-names = "fck"; 223 power-domains = <&sysc 32>; 224 resets = <&cpg 218>; 225 #dma-cells = <1>; 226 dma-channels = <8>; 227 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 228 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 229 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 230 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; 231 }; 232 233 dmac2: dma-controller@e7310000 { 234 compatible = "renesas,dmac-r8a77970", 235 "renesas,rcar-dmac"; 236 reg = <0 0xe7310000 0 0x10000>; 237 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 238 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 239 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 240 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 241 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 242 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 243 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 244 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 245 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 246 interrupt-names = "error", 247 "ch0", "ch1", "ch2", "ch3", 248 "ch4", "ch5", "ch6", "ch7"; 249 clocks = <&cpg CPG_MOD 217>; 250 clock-names = "fck"; 251 power-domains = <&sysc 32>; 252 resets = <&cpg 217>; 253 #dma-cells = <1>; 254 dma-channels = <8>; 255 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 256 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 257 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 258 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; 259 }; 260 261 hscif0: serial@e6540000 { 262 compatible = "renesas,hscif-r8a77970", 263 "renesas,rcar-gen3-hscif", 264 "renesas,hscif"; 265 reg = <0 0xe6540000 0 96>; 266 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&cpg CPG_MOD 520>, 268 <&cpg CPG_CORE 9>, 269 <&scif_clk>; 270 clock-names = "fck", "brg_int", "scif_clk"; 271 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 272 <&dmac2 0x31>, <&dmac2 0x30>; 273 dma-names = "tx", "rx", "tx", "rx"; 274 power-domains = <&sysc 32>; 275 resets = <&cpg 520>; 276 status = "disabled"; 277 }; 278 279 hscif1: serial@e6550000 { 280 compatible = "renesas,hscif-r8a77970", 281 "renesas,rcar-gen3-hscif", 282 "renesas,hscif"; 283 reg = <0 0xe6550000 0 96>; 284 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&cpg CPG_MOD 519>, 286 <&cpg CPG_CORE 9>, 287 <&scif_clk>; 288 clock-names = "fck", "brg_int", "scif_clk"; 289 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 290 <&dmac2 0x33>, <&dmac2 0x32>; 291 dma-names = "tx", "rx", "tx", "rx"; 292 power-domains = <&sysc 32>; 293 resets = <&cpg 519>; 294 status = "disabled"; 295 }; 296 297 hscif2: serial@e6560000 { 298 compatible = "renesas,hscif-r8a77970", 299 "renesas,rcar-gen3-hscif", 300 "renesas,hscif"; 301 reg = <0 0xe6560000 0 96>; 302 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&cpg CPG_MOD 518>, 304 <&cpg CPG_CORE 9>, 305 <&scif_clk>; 306 clock-names = "fck", "brg_int", "scif_clk"; 307 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 308 <&dmac2 0x35>, <&dmac2 0x34>; 309 dma-names = "tx", "rx", "tx", "rx"; 310 power-domains = <&sysc 32>; 311 resets = <&cpg 518>; 312 status = "disabled"; 313 }; 314 315 hscif3: serial@e66a0000 { 316 compatible = "renesas,hscif-r8a77970", 317 "renesas,rcar-gen3-hscif", "renesas,hscif"; 318 reg = <0 0xe66a0000 0 96>; 319 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&cpg CPG_MOD 517>, 321 <&cpg CPG_CORE 9>, 322 <&scif_clk>; 323 clock-names = "fck", "brg_int", "scif_clk"; 324 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 325 <&dmac2 0x37>, <&dmac2 0x36>; 326 dma-names = "tx", "rx", "tx", "rx"; 327 power-domains = <&sysc 32>; 328 resets = <&cpg 517>; 329 status = "disabled"; 330 }; 331 332 scif0: serial@e6e60000 { 333 compatible = "renesas,scif-r8a77970", 334 "renesas,rcar-gen3-scif", 335 "renesas,scif"; 336 reg = <0 0xe6e60000 0 64>; 337 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&cpg CPG_MOD 207>, 339 <&cpg CPG_CORE 9>, 340 <&scif_clk>; 341 clock-names = "fck", "brg_int", "scif_clk"; 342 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 343 <&dmac2 0x51>, <&dmac2 0x50>; 344 dma-names = "tx", "rx", "tx", "rx"; 345 power-domains = <&sysc 32>; 346 resets = <&cpg 207>; 347 status = "disabled"; 348 }; 349 350 scif1: serial@e6e68000 { 351 compatible = "renesas,scif-r8a77970", 352 "renesas,rcar-gen3-scif", 353 "renesas,scif"; 354 reg = <0 0xe6e68000 0 64>; 355 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&cpg CPG_MOD 206>, 357 <&cpg CPG_CORE 9>, 358 <&scif_clk>; 359 clock-names = "fck", "brg_int", "scif_clk"; 360 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 361 <&dmac2 0x53>, <&dmac2 0x52>; 362 dma-names = "tx", "rx", "tx", "rx"; 363 power-domains = <&sysc 32>; 364 resets = <&cpg 206>; 365 status = "disabled"; 366 }; 367 368 scif3: serial@e6c50000 { 369 compatible = "renesas,scif-r8a77970", 370 "renesas,rcar-gen3-scif", 371 "renesas,scif"; 372 reg = <0 0xe6c50000 0 64>; 373 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&cpg CPG_MOD 204>, 375 <&cpg CPG_CORE 9>, 376 <&scif_clk>; 377 clock-names = "fck", "brg_int", "scif_clk"; 378 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 379 <&dmac2 0x57>, <&dmac2 0x56>; 380 dma-names = "tx", "rx", "tx", "rx"; 381 power-domains = <&sysc 32>; 382 resets = <&cpg 204>; 383 status = "disabled"; 384 }; 385 386 scif4: serial@e6c40000 { 387 compatible = "renesas,scif-r8a77970", 388 "renesas,rcar-gen3-scif", "renesas,scif"; 389 reg = <0 0xe6c40000 0 64>; 390 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 391 clocks = <&cpg CPG_MOD 203>, 392 <&cpg CPG_CORE 9>, 393 <&scif_clk>; 394 clock-names = "fck", "brg_int", "scif_clk"; 395 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 396 <&dmac2 0x59>, <&dmac2 0x58>; 397 dma-names = "tx", "rx", "tx", "rx"; 398 power-domains = <&sysc 32>; 399 resets = <&cpg 203>; 400 status = "disabled"; 401 }; 402 403 avb: ethernet@e6800000 { 404 compatible = "renesas,etheravb-r8a77970", 405 "renesas,etheravb-rcar-gen3"; 406 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 407 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 432 interrupt-names = "ch0", "ch1", "ch2", "ch3", 433 "ch4", "ch5", "ch6", "ch7", 434 "ch8", "ch9", "ch10", "ch11", 435 "ch12", "ch13", "ch14", "ch15", 436 "ch16", "ch17", "ch18", "ch19", 437 "ch20", "ch21", "ch22", "ch23", 438 "ch24"; 439 clocks = <&cpg CPG_MOD 812>; 440 power-domains = <&sysc 32>; 441 resets = <&cpg 812>; 442 phy-mode = "rgmii-id"; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 }; 446 }; 447}; 448