xref: /linux/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts (revision 8a922b7728a93d837954315c98b84f6b78de0c4f) 
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the Eagle board with R-Car V3M
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 * Copyright (C) 2017 Cogent Embedded, Inc.
7 */
8
9/dts-v1/;
10#include "r8a77970.dtsi"
11#include <dt-bindings/gpio/gpio.h>
12
13/ {
14	model = "Renesas Eagle board based on r8a77970";
15	compatible = "renesas,eagle", "renesas,r8a77970";
16
17	aliases {
18		i2c0 = &i2c0;
19		i2c1 = &i2c1;
20		i2c2 = &i2c2;
21		i2c3 = &i2c3;
22		i2c4 = &i2c4;
23		serial0 = &scif0;
24		ethernet0 = &avb;
25	};
26
27	chosen {
28		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
29		stdout-path = "serial0:115200n8";
30	};
31
32	d3p3: regulator-fixed {
33		compatible = "regulator-fixed";
34		regulator-name = "fixed-3.3V";
35		regulator-min-microvolt = <3300000>;
36		regulator-max-microvolt = <3300000>;
37		regulator-boot-on;
38		regulator-always-on;
39	};
40
41	hdmi-out {
42		compatible = "hdmi-connector";
43		type = "a";
44
45		port {
46			hdmi_con_out: endpoint {
47				remote-endpoint = <&adv7511_out>;
48			};
49		};
50	};
51
52	lvds-decoder {
53		compatible = "thine,thc63lvd1024";
54
55		vcc-supply = <&d3p3>;
56
57		ports {
58			#address-cells = <1>;
59			#size-cells = <0>;
60
61			port@0 {
62				reg = <0>;
63				thc63lvd1024_in: endpoint {
64					remote-endpoint = <&lvds0_out>;
65				};
66			};
67
68			port@2 {
69				reg = <2>;
70				thc63lvd1024_out: endpoint {
71					remote-endpoint = <&adv7511_in>;
72				};
73			};
74		};
75	};
76
77	memory@48000000 {
78		device_type = "memory";
79		/* first 128MB is reserved for secure area. */
80		reg = <0x0 0x48000000 0x0 0x38000000>;
81	};
82
83	x1_clk: x1-clock {
84		compatible = "fixed-clock";
85		#clock-cells = <0>;
86		clock-frequency = <148500000>;
87	};
88};
89
90&avb {
91	pinctrl-0 = <&avb_pins>;
92	pinctrl-names = "default";
93
94	renesas,no-ether-link;
95	phy-handle = <&phy0>;
96	rx-internal-delay-ps = <1800>;
97	tx-internal-delay-ps = <2000>;
98	status = "okay";
99
100	phy0: ethernet-phy@0 {
101		compatible = "ethernet-phy-id0022.1622",
102			     "ethernet-phy-ieee802.3-c22";
103		rxc-skew-ps = <1500>;
104		reg = <0>;
105		interrupt-parent = <&gpio1>;
106		interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
107		reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
108	};
109};
110
111&canfd {
112	pinctrl-0 = <&canfd0_pins>;
113	pinctrl-names = "default";
114	status = "okay";
115
116	channel0 {
117		status = "okay";
118	};
119};
120
121&csi40 {
122	status = "okay";
123
124	ports {
125		port@0 {
126			csi40_in: endpoint {
127				clock-lanes = <0>;
128				data-lanes = <1 2 3 4>;
129				remote-endpoint = <&max9286_out0>;
130			};
131		};
132	};
133};
134
135&du {
136	clocks = <&cpg CPG_MOD 724>, <&x1_clk>;
137	clock-names = "du.0", "dclkin.0";
138	status = "okay";
139};
140
141&extal_clk {
142	clock-frequency = <16666666>;
143};
144
145&extalr_clk {
146	clock-frequency = <32768>;
147};
148
149&i2c0 {
150	pinctrl-0 = <&i2c0_pins>;
151	pinctrl-names = "default";
152
153	status = "okay";
154	clock-frequency = <400000>;
155
156	io_expander: gpio@20 {
157		compatible = "onnn,pca9654";
158		reg = <0x20>;
159		gpio-controller;
160		#gpio-cells = <2>;
161	};
162
163	hdmi@39 {
164		compatible = "adi,adv7511w";
165		reg = <0x39>;
166		interrupt-parent = <&gpio1>;
167		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
168
169		adi,input-depth = <8>;
170		adi,input-colorspace = "rgb";
171		adi,input-clock = "1x";
172
173		ports {
174			#address-cells = <1>;
175			#size-cells = <0>;
176
177			port@0 {
178				reg = <0>;
179				adv7511_in: endpoint {
180					remote-endpoint = <&thc63lvd1024_out>;
181				};
182			};
183
184			port@1 {
185				reg = <1>;
186				adv7511_out: endpoint {
187					remote-endpoint = <&hdmi_con_out>;
188				};
189			};
190		};
191	};
192};
193
194&i2c3 {
195	pinctrl-0 = <&i2c3_pins>;
196	pinctrl-names = "default";
197
198	status = "okay";
199	clock-frequency = <400000>;
200
201	gmsl0: gmsl-deserializer@48 {
202		compatible = "maxim,max9286";
203		reg = <0x48>;
204
205		maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
206		enable-gpios = <&io_expander 0 GPIO_ACTIVE_HIGH>;
207
208		ports {
209			#address-cells = <1>;
210			#size-cells = <0>;
211
212			port@0 {
213				reg = <0>;
214			};
215
216			port@1 {
217				reg = <1>;
218			};
219
220			port@2 {
221				reg = <2>;
222			};
223
224			port@3 {
225				reg = <3>;
226			};
227
228			port@4 {
229				reg = <4>;
230				max9286_out0: endpoint {
231					clock-lanes = <0>;
232					data-lanes = <1 2 3 4>;
233					remote-endpoint = <&csi40_in>;
234				};
235			};
236		};
237
238		i2c-mux {
239			#address-cells = <1>;
240			#size-cells = <0>;
241
242			i2c@0 {
243				#address-cells = <1>;
244				#size-cells = <0>;
245				reg = <0>;
246
247				status = "disabled";
248			};
249
250			i2c@1 {
251				#address-cells = <1>;
252				#size-cells = <0>;
253				reg = <1>;
254
255				status = "disabled";
256			};
257
258			i2c@2 {
259				#address-cells = <1>;
260				#size-cells = <0>;
261				reg = <2>;
262
263				status = "disabled";
264			};
265
266			i2c@3 {
267				#address-cells = <1>;
268				#size-cells = <0>;
269				reg = <3>;
270
271				status = "disabled";
272			};
273		};
274	};
275};
276
277&lvds0 {
278	status = "okay";
279
280	ports {
281		port@1 {
282			lvds0_out: endpoint {
283				remote-endpoint = <&thc63lvd1024_in>;
284			};
285		};
286	};
287};
288
289&pfc {
290	pinctrl-0 = <&scif_clk_pins>;
291	pinctrl-names = "default";
292
293	avb_pins: avb0 {
294		groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
295		function = "avb0";
296	};
297
298	canfd0_pins: canfd0 {
299		groups = "canfd0_data_a";
300		function = "canfd0";
301	};
302
303	i2c0_pins: i2c0 {
304		groups = "i2c0";
305		function = "i2c0";
306	};
307
308	i2c3_pins: i2c3 {
309		groups = "i2c3_a";
310		function = "i2c3";
311	};
312
313	qspi0_pins: qspi0 {
314		groups = "qspi0_ctrl", "qspi0_data4";
315		function = "qspi0";
316	};
317
318	scif0_pins: scif0 {
319		groups = "scif0_data";
320		function = "scif0";
321	};
322
323	scif_clk_pins: scif_clk {
324		groups = "scif_clk_b";
325		function = "scif_clk";
326	};
327};
328
329&rpc {
330	pinctrl-0 = <&qspi0_pins>;
331	pinctrl-names = "default";
332
333	status = "okay";
334
335	flash@0 {
336		compatible = "spansion,s25fs512s", "jedec,spi-nor";
337		reg = <0>;
338		spi-max-frequency = <50000000>;
339		spi-rx-bus-width = <4>;
340
341		partitions {
342			compatible = "fixed-partitions";
343			#address-cells = <1>;
344			#size-cells = <1>;
345
346			bootparam@0 {
347				reg = <0x00000000 0x040000>;
348				read-only;
349			};
350			cr7@40000 {
351				reg = <0x00040000 0x080000>;
352				read-only;
353			};
354			cert_header_sa3@c0000 {
355				reg = <0x000c0000 0x080000>;
356				read-only;
357			};
358			bl2@140000 {
359				reg = <0x00140000 0x040000>;
360				read-only;
361			};
362			cert_header_sa6@180000 {
363				reg = <0x00180000 0x040000>;
364				read-only;
365			};
366			bl31@1c0000 {
367				reg = <0x001c0000 0x460000>;
368				read-only;
369			};
370			uboot@640000 {
371				reg = <0x00640000 0x0c0000>;
372				read-only;
373			};
374			uboot-env@700000 {
375				reg = <0x00700000 0x040000>;
376				read-only;
377			};
378			dtb@740000 {
379				reg = <0x00740000 0x080000>;
380			};
381			kernel@7c0000 {
382				reg = <0x007c0000 0x1400000>;
383			};
384			user@1bc0000 {
385				reg = <0x01bc0000 0x2440000>;
386			};
387		};
388	};
389};
390
391&rwdt {
392	timeout-sec = <60>;
393	status = "okay";
394};
395
396&scif0 {
397	pinctrl-0 = <&scif0_pins>;
398	pinctrl-names = "default";
399
400	status = "okay";
401};
402
403&scif_clk {
404	clock-frequency = <14745600>;
405};
406