xref: /linux/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts (revision 5f60d5f6bbc12e782fac78110b0ee62698f3b576) 
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the Eagle board with R-Car V3M
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 * Copyright (C) 2017 Cogent Embedded, Inc.
7 */
8
9/dts-v1/;
10#include "r8a77970.dtsi"
11#include <dt-bindings/gpio/gpio.h>
12
13/ {
14	model = "Renesas Eagle board based on r8a77970";
15	compatible = "renesas,eagle", "renesas,r8a77970";
16
17	aliases {
18		i2c0 = &i2c0;
19		i2c1 = &i2c1;
20		i2c2 = &i2c2;
21		i2c3 = &i2c3;
22		i2c4 = &i2c4;
23		serial0 = &scif0;
24		ethernet0 = &avb;
25	};
26
27	chosen {
28		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
29		stdout-path = "serial0:115200n8";
30	};
31
32	d1p8: regulator-fixed {
33		compatible = "regulator-fixed";
34		regulator-name = "fixed-1.8V";
35		regulator-min-microvolt = <1800000>;
36		regulator-max-microvolt = <1800000>;
37		regulator-boot-on;
38		regulator-always-on;
39	};
40
41	d3p3: regulator-fixed {
42		compatible = "regulator-fixed";
43		regulator-name = "fixed-3.3V";
44		regulator-min-microvolt = <3300000>;
45		regulator-max-microvolt = <3300000>;
46		regulator-boot-on;
47		regulator-always-on;
48	};
49
50	hdmi-out {
51		compatible = "hdmi-connector";
52		type = "a";
53
54		port {
55			hdmi_con_out: endpoint {
56				remote-endpoint = <&adv7511_out>;
57			};
58		};
59	};
60
61	lvds-decoder {
62		compatible = "thine,thc63lvd1024";
63
64		vcc-supply = <&d3p3>;
65
66		ports {
67			#address-cells = <1>;
68			#size-cells = <0>;
69
70			port@0 {
71				reg = <0>;
72				thc63lvd1024_in: endpoint {
73					remote-endpoint = <&lvds0_out>;
74				};
75			};
76
77			port@2 {
78				reg = <2>;
79				thc63lvd1024_out: endpoint {
80					remote-endpoint = <&adv7511_in>;
81				};
82			};
83		};
84	};
85
86	memory@48000000 {
87		device_type = "memory";
88		/* first 128MB is reserved for secure area. */
89		reg = <0x0 0x48000000 0x0 0x38000000>;
90	};
91
92	x1_clk: x1-clock {
93		compatible = "fixed-clock";
94		#clock-cells = <0>;
95		clock-frequency = <148500000>;
96	};
97};
98
99&avb {
100	pinctrl-0 = <&avb_pins>;
101	pinctrl-names = "default";
102
103	renesas,no-ether-link;
104	phy-handle = <&phy0>;
105	rx-internal-delay-ps = <1800>;
106	tx-internal-delay-ps = <2000>;
107	status = "okay";
108
109	phy0: ethernet-phy@0 {
110		compatible = "ethernet-phy-id0022.1622",
111			     "ethernet-phy-ieee802.3-c22";
112		rxc-skew-ps = <1500>;
113		reg = <0>;
114		interrupt-parent = <&gpio1>;
115		interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
116		reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
117	};
118};
119
120&canfd {
121	pinctrl-0 = <&canfd0_pins>;
122	pinctrl-names = "default";
123	status = "okay";
124
125	channel0 {
126		status = "okay";
127	};
128};
129
130&csi40 {
131	status = "okay";
132
133	ports {
134		port@0 {
135			csi40_in: endpoint {
136				clock-lanes = <0>;
137				data-lanes = <1 2 3 4>;
138				remote-endpoint = <&max9286_out0>;
139			};
140		};
141	};
142};
143
144&du {
145	clocks = <&cpg CPG_MOD 724>, <&x1_clk>;
146	clock-names = "du.0", "dclkin.0";
147	status = "okay";
148};
149
150&extal_clk {
151	clock-frequency = <16666666>;
152};
153
154&extalr_clk {
155	clock-frequency = <32768>;
156};
157
158&i2c0 {
159	pinctrl-0 = <&i2c0_pins>;
160	pinctrl-names = "default";
161
162	status = "okay";
163	clock-frequency = <400000>;
164
165	io_expander: gpio@20 {
166		compatible = "onnn,pca9654";
167		reg = <0x20>;
168		gpio-controller;
169		#gpio-cells = <2>;
170	};
171
172	hdmi@39 {
173		compatible = "adi,adv7511w";
174		reg = <0x39>;
175		interrupt-parent = <&gpio1>;
176		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
177
178		avdd-supply = <&d1p8>;
179		dvdd-supply = <&d1p8>;
180		pvdd-supply = <&d1p8>;
181		dvdd-3v-supply = <&d3p3>;
182		bgvdd-supply = <&d1p8>;
183
184		adi,input-depth = <8>;
185		adi,input-colorspace = "rgb";
186		adi,input-clock = "1x";
187
188		ports {
189			#address-cells = <1>;
190			#size-cells = <0>;
191
192			port@0 {
193				reg = <0>;
194				adv7511_in: endpoint {
195					remote-endpoint = <&thc63lvd1024_out>;
196				};
197			};
198
199			port@1 {
200				reg = <1>;
201				adv7511_out: endpoint {
202					remote-endpoint = <&hdmi_con_out>;
203				};
204			};
205		};
206	};
207};
208
209&i2c3 {
210	pinctrl-0 = <&i2c3_pins>;
211	pinctrl-names = "default";
212
213	status = "okay";
214	clock-frequency = <400000>;
215
216	gmsl0: gmsl-deserializer@48 {
217		compatible = "maxim,max9286";
218		reg = <0x48>;
219
220		maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
221		enable-gpios = <&io_expander 0 GPIO_ACTIVE_HIGH>;
222
223		ports {
224			#address-cells = <1>;
225			#size-cells = <0>;
226
227			port@0 {
228				reg = <0>;
229			};
230
231			port@1 {
232				reg = <1>;
233			};
234
235			port@2 {
236				reg = <2>;
237			};
238
239			port@3 {
240				reg = <3>;
241			};
242
243			port@4 {
244				reg = <4>;
245				max9286_out0: endpoint {
246					clock-lanes = <0>;
247					data-lanes = <1 2 3 4>;
248					remote-endpoint = <&csi40_in>;
249				};
250			};
251		};
252
253		i2c-mux {
254			#address-cells = <1>;
255			#size-cells = <0>;
256
257			i2c@0 {
258				#address-cells = <1>;
259				#size-cells = <0>;
260				reg = <0>;
261
262				status = "disabled";
263			};
264
265			i2c@1 {
266				#address-cells = <1>;
267				#size-cells = <0>;
268				reg = <1>;
269
270				status = "disabled";
271			};
272
273			i2c@2 {
274				#address-cells = <1>;
275				#size-cells = <0>;
276				reg = <2>;
277
278				status = "disabled";
279			};
280
281			i2c@3 {
282				#address-cells = <1>;
283				#size-cells = <0>;
284				reg = <3>;
285
286				status = "disabled";
287			};
288		};
289	};
290};
291
292&lvds0 {
293	status = "okay";
294
295	ports {
296		port@1 {
297			lvds0_out: endpoint {
298				remote-endpoint = <&thc63lvd1024_in>;
299			};
300		};
301	};
302};
303
304&pfc {
305	pinctrl-0 = <&scif_clk_pins>;
306	pinctrl-names = "default";
307
308	avb_pins: avb0 {
309		groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
310		function = "avb0";
311	};
312
313	canfd0_pins: canfd0 {
314		groups = "canfd0_data_a";
315		function = "canfd0";
316	};
317
318	i2c0_pins: i2c0 {
319		groups = "i2c0";
320		function = "i2c0";
321	};
322
323	i2c3_pins: i2c3 {
324		groups = "i2c3_a";
325		function = "i2c3";
326	};
327
328	qspi0_pins: qspi0 {
329		groups = "qspi0_ctrl", "qspi0_data4";
330		function = "qspi0";
331	};
332
333	scif0_pins: scif0 {
334		groups = "scif0_data";
335		function = "scif0";
336	};
337
338	scif_clk_pins: scif_clk {
339		groups = "scif_clk_b";
340		function = "scif_clk";
341	};
342};
343
344&rpc {
345	pinctrl-0 = <&qspi0_pins>;
346	pinctrl-names = "default";
347
348	status = "okay";
349
350	flash@0 {
351		compatible = "spansion,s25fs512s", "jedec,spi-nor";
352		reg = <0>;
353		spi-max-frequency = <50000000>;
354		spi-rx-bus-width = <4>;
355
356		partitions {
357			compatible = "fixed-partitions";
358			#address-cells = <1>;
359			#size-cells = <1>;
360
361			bootparam@0 {
362				reg = <0x00000000 0x040000>;
363				read-only;
364			};
365			cr7@40000 {
366				reg = <0x00040000 0x080000>;
367				read-only;
368			};
369			cert_header_sa3@c0000 {
370				reg = <0x000c0000 0x080000>;
371				read-only;
372			};
373			bl2@140000 {
374				reg = <0x00140000 0x040000>;
375				read-only;
376			};
377			cert_header_sa6@180000 {
378				reg = <0x00180000 0x040000>;
379				read-only;
380			};
381			bl31@1c0000 {
382				reg = <0x001c0000 0x460000>;
383				read-only;
384			};
385			uboot@640000 {
386				reg = <0x00640000 0x0c0000>;
387				read-only;
388			};
389			uboot-env@700000 {
390				reg = <0x00700000 0x040000>;
391				read-only;
392			};
393			dtb@740000 {
394				reg = <0x00740000 0x080000>;
395			};
396			kernel@7c0000 {
397				reg = <0x007c0000 0x1400000>;
398			};
399			user@1bc0000 {
400				reg = <0x01bc0000 0x2440000>;
401			};
402		};
403	};
404};
405
406&rwdt {
407	timeout-sec = <60>;
408	status = "okay";
409};
410
411&scif0 {
412	pinctrl-0 = <&scif0_pins>;
413	pinctrl-names = "default";
414
415	status = "okay";
416};
417
418&scif_clk {
419	clock-frequency = <14745600>;
420};
421