xref: /linux/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts (revision 55d0969c451159cff86949b38c39171cab962069) 
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the Eagle board with R-Car V3M
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 * Copyright (C) 2017 Cogent Embedded, Inc.
7 */
8
9/dts-v1/;
10#include "r8a77970.dtsi"
11#include <dt-bindings/gpio/gpio.h>
12
13/ {
14	model = "Renesas Eagle board based on r8a77970";
15	compatible = "renesas,eagle", "renesas,r8a77970";
16
17	aliases {
18		i2c0 = &i2c0;
19		i2c1 = &i2c1;
20		i2c2 = &i2c2;
21		i2c3 = &i2c3;
22		i2c4 = &i2c4;
23		serial0 = &scif0;
24		ethernet0 = &avb;
25	};
26
27	chosen {
28		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
29		stdout-path = "serial0:115200n8";
30	};
31
32	d1p8: regulator-fixed {
33		compatible = "regulator-fixed";
34		regulator-name = "fixed-1.8V";
35		regulator-min-microvolt = <1800000>;
36		regulator-max-microvolt = <1800000>;
37		regulator-boot-on;
38		regulator-always-on;
39	};
40
41	d3p3: regulator-fixed {
42		compatible = "regulator-fixed";
43		regulator-name = "fixed-3.3V";
44		regulator-min-microvolt = <3300000>;
45		regulator-max-microvolt = <3300000>;
46		regulator-boot-on;
47		regulator-always-on;
48	};
49
50	hdmi-out {
51		compatible = "hdmi-connector";
52		type = "a";
53
54		port {
55			hdmi_con_out: endpoint {
56				remote-endpoint = <&adv7511_out>;
57			};
58		};
59	};
60
61	lvds-decoder {
62		compatible = "thine,thc63lvd1024";
63
64		vcc-supply = <&d3p3>;
65
66		ports {
67			#address-cells = <1>;
68			#size-cells = <0>;
69
70			port@0 {
71				reg = <0>;
72				thc63lvd1024_in: endpoint {
73					remote-endpoint = <&lvds0_out>;
74				};
75			};
76
77			port@2 {
78				reg = <2>;
79				thc63lvd1024_out: endpoint {
80					remote-endpoint = <&adv7511_in>;
81				};
82			};
83		};
84	};
85
86	memory@48000000 {
87		device_type = "memory";
88		/* first 128MB is reserved for secure area. */
89		reg = <0x0 0x48000000 0x0 0x38000000>;
90	};
91
92	x1_clk: x1-clock {
93		compatible = "fixed-clock";
94		#clock-cells = <0>;
95		clock-frequency = <148500000>;
96	};
97};
98
99&avb {
100	pinctrl-0 = <&avb_pins>;
101	pinctrl-names = "default";
102
103	renesas,no-ether-link;
104	phy-handle = <&phy0>;
105	rx-internal-delay-ps = <1800>;
106	tx-internal-delay-ps = <2000>;
107	status = "okay";
108
109	phy0: ethernet-phy@0 {
110		compatible = "ethernet-phy-id0022.1622",
111			     "ethernet-phy-ieee802.3-c22";
112		rxc-skew-ps = <1500>;
113		reg = <0>;
114		interrupts-extended = <&gpio1 17 IRQ_TYPE_LEVEL_LOW>;
115		reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
116	};
117};
118
119&canfd {
120	pinctrl-0 = <&canfd0_pins>;
121	pinctrl-names = "default";
122	status = "okay";
123
124	channel0 {
125		status = "okay";
126	};
127};
128
129&csi40 {
130	status = "okay";
131
132	ports {
133		port@0 {
134			csi40_in: endpoint {
135				clock-lanes = <0>;
136				data-lanes = <1 2 3 4>;
137				remote-endpoint = <&max9286_out0>;
138			};
139		};
140	};
141};
142
143&du {
144	clocks = <&cpg CPG_MOD 724>, <&x1_clk>;
145	clock-names = "du.0", "dclkin.0";
146	status = "okay";
147};
148
149&extal_clk {
150	clock-frequency = <16666666>;
151};
152
153&extalr_clk {
154	clock-frequency = <32768>;
155};
156
157&i2c0 {
158	pinctrl-0 = <&i2c0_pins>;
159	pinctrl-names = "default";
160
161	status = "okay";
162	clock-frequency = <400000>;
163
164	io_expander: gpio@20 {
165		compatible = "onnn,pca9654";
166		reg = <0x20>;
167		gpio-controller;
168		#gpio-cells = <2>;
169	};
170
171	hdmi@39 {
172		compatible = "adi,adv7511w";
173		reg = <0x39>;
174		interrupts-extended = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>;
175
176		avdd-supply = <&d1p8>;
177		dvdd-supply = <&d1p8>;
178		pvdd-supply = <&d1p8>;
179		dvdd-3v-supply = <&d3p3>;
180		bgvdd-supply = <&d1p8>;
181
182		adi,input-depth = <8>;
183		adi,input-colorspace = "rgb";
184		adi,input-clock = "1x";
185
186		ports {
187			#address-cells = <1>;
188			#size-cells = <0>;
189
190			port@0 {
191				reg = <0>;
192				adv7511_in: endpoint {
193					remote-endpoint = <&thc63lvd1024_out>;
194				};
195			};
196
197			port@1 {
198				reg = <1>;
199				adv7511_out: endpoint {
200					remote-endpoint = <&hdmi_con_out>;
201				};
202			};
203		};
204	};
205};
206
207&i2c3 {
208	pinctrl-0 = <&i2c3_pins>;
209	pinctrl-names = "default";
210
211	status = "okay";
212	clock-frequency = <400000>;
213
214	gmsl0: gmsl-deserializer@48 {
215		compatible = "maxim,max9286";
216		reg = <0x48>;
217
218		maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
219		enable-gpios = <&io_expander 0 GPIO_ACTIVE_HIGH>;
220
221		ports {
222			#address-cells = <1>;
223			#size-cells = <0>;
224
225			port@0 {
226				reg = <0>;
227			};
228
229			port@1 {
230				reg = <1>;
231			};
232
233			port@2 {
234				reg = <2>;
235			};
236
237			port@3 {
238				reg = <3>;
239			};
240
241			port@4 {
242				reg = <4>;
243				max9286_out0: endpoint {
244					clock-lanes = <0>;
245					data-lanes = <1 2 3 4>;
246					remote-endpoint = <&csi40_in>;
247				};
248			};
249		};
250
251		i2c-mux {
252			#address-cells = <1>;
253			#size-cells = <0>;
254
255			i2c@0 {
256				#address-cells = <1>;
257				#size-cells = <0>;
258				reg = <0>;
259
260				status = "disabled";
261			};
262
263			i2c@1 {
264				#address-cells = <1>;
265				#size-cells = <0>;
266				reg = <1>;
267
268				status = "disabled";
269			};
270
271			i2c@2 {
272				#address-cells = <1>;
273				#size-cells = <0>;
274				reg = <2>;
275
276				status = "disabled";
277			};
278
279			i2c@3 {
280				#address-cells = <1>;
281				#size-cells = <0>;
282				reg = <3>;
283
284				status = "disabled";
285			};
286		};
287	};
288};
289
290&lvds0 {
291	status = "okay";
292
293	ports {
294		port@1 {
295			lvds0_out: endpoint {
296				remote-endpoint = <&thc63lvd1024_in>;
297			};
298		};
299	};
300};
301
302&pfc {
303	pinctrl-0 = <&scif_clk_pins>;
304	pinctrl-names = "default";
305
306	avb_pins: avb0 {
307		groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
308		function = "avb0";
309	};
310
311	canfd0_pins: canfd0 {
312		groups = "canfd0_data_a";
313		function = "canfd0";
314	};
315
316	i2c0_pins: i2c0 {
317		groups = "i2c0";
318		function = "i2c0";
319	};
320
321	i2c3_pins: i2c3 {
322		groups = "i2c3_a";
323		function = "i2c3";
324	};
325
326	qspi0_pins: qspi0 {
327		groups = "qspi0_ctrl", "qspi0_data4";
328		function = "qspi0";
329	};
330
331	scif0_pins: scif0 {
332		groups = "scif0_data";
333		function = "scif0";
334	};
335
336	scif_clk_pins: scif_clk {
337		groups = "scif_clk_b";
338		function = "scif_clk";
339	};
340};
341
342&rpc {
343	pinctrl-0 = <&qspi0_pins>;
344	pinctrl-names = "default";
345
346	status = "okay";
347
348	flash@0 {
349		compatible = "spansion,s25fs512s", "jedec,spi-nor";
350		reg = <0>;
351		spi-max-frequency = <50000000>;
352		spi-rx-bus-width = <4>;
353
354		partitions {
355			compatible = "fixed-partitions";
356			#address-cells = <1>;
357			#size-cells = <1>;
358
359			bootparam@0 {
360				reg = <0x00000000 0x040000>;
361				read-only;
362			};
363			cr7@40000 {
364				reg = <0x00040000 0x080000>;
365				read-only;
366			};
367			cert_header_sa3@c0000 {
368				reg = <0x000c0000 0x080000>;
369				read-only;
370			};
371			bl2@140000 {
372				reg = <0x00140000 0x040000>;
373				read-only;
374			};
375			cert_header_sa6@180000 {
376				reg = <0x00180000 0x040000>;
377				read-only;
378			};
379			bl31@1c0000 {
380				reg = <0x001c0000 0x460000>;
381				read-only;
382			};
383			uboot@640000 {
384				reg = <0x00640000 0x0c0000>;
385				read-only;
386			};
387			uboot-env@700000 {
388				reg = <0x00700000 0x040000>;
389				read-only;
390			};
391			dtb@740000 {
392				reg = <0x00740000 0x080000>;
393			};
394			kernel@7c0000 {
395				reg = <0x007c0000 0x1400000>;
396			};
397			user@1bc0000 {
398				reg = <0x01bc0000 0x2440000>;
399			};
400		};
401	};
402};
403
404&rwdt {
405	timeout-sec = <60>;
406	status = "okay";
407};
408
409&scif0 {
410	pinctrl-0 = <&scif0_pins>;
411	pinctrl-names = "default";
412
413	status = "okay";
414};
415
416&scif_clk {
417	clock-frequency = <14745600>;
418};
419