1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the Eagle V3M Function expansion board. 4 * 5 * Copyright (C) 2024 Niklas Söderlund <niklas.soderlund@ragnatech.se> 6 */ 7 8/dts-v1/; 9/plugin/; 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13 14/ { 15 /* CN4 */ 16 /* Eagle: SW18 set to OFF */ 17 cvbs-in-cn4 { 18 compatible = "composite-video-connector"; 19 label = "CVBS IN CN4"; 20 21 port { 22 cvbs_con: endpoint { 23 remote-endpoint = <&adv7482_ain7>; 24 }; 25 }; 26 }; 27 28 /* CN2 */ 29 /* Eagle: SW35 set 5, 6 and 8 to OFF */ 30 hdmi-in-cn2 { 31 compatible = "hdmi-connector"; 32 label = "HDMI IN CN2"; 33 type = "a"; 34 35 port { 36 hdmi_in_con2: endpoint { 37 remote-endpoint = <&adv7612_in>; 38 }; 39 }; 40 }; 41 42 /* CN3 */ 43 /* Eagle: SW18 set to OFF */ 44 hdmi-in-cn3 { 45 compatible = "hdmi-connector"; 46 label = "HDMI IN CN3"; 47 type = "a"; 48 49 port { 50 hdmi_in_con: endpoint { 51 remote-endpoint = <&adv7482_hdmi>; 52 }; 53 }; 54 }; 55}; 56 57/* Disconnect MAX9286 GMSL I2C. */ 58&i2c3 { 59 status = "disabled"; 60}; 61 62/* Connect expansion board I2C. */ 63&i2c0 { 64 #address-cells = <1>; 65 #size-cells = <0>; 66 67 gpio@27 { 68 compatible = "onnn,pca9654"; 69 reg = <0x27>; 70 gpio-controller; 71 #gpio-cells = <2>; 72 73 vin0_adv7612_en { 74 gpio-hog; 75 gpios = <3 GPIO_ACTIVE_LOW>; 76 output-high; 77 line-name = "VIN0_ADV7612_ENn"; 78 }; 79 }; 80 81 hdmi-decoder@4c { 82 compatible = "adi,adv7612"; 83 reg = <0x4c>, <0x50>, <0x52>, <0x54>, <0x56>, <0x58>; 84 reg-names = "main", "afe", "rep", "edid", "hdmi", "cp"; 85 interrupts-extended = <&gpio3 2 IRQ_TYPE_LEVEL_LOW>; 86 default-input = <0>; 87 88 ports { 89 #address-cells = <1>; 90 #size-cells = <0>; 91 92 port@0 { 93 reg = <0>; 94 95 adv7612_in: endpoint { 96 remote-endpoint = <&hdmi_in_con2>; 97 }; 98 }; 99 100 port@2 { 101 reg = <2>; 102 103 adv7612_out: endpoint { 104 remote-endpoint = <&vin0_in>; 105 }; 106 }; 107 }; 108 }; 109 110 video-receiver@70 { 111 compatible = "adi,adv7482"; 112 reg = <0x70 0x71 0x72 0x73 0x74 0x75 113 0x60 0x61 0x62 0x63 0x64 0x65>; 114 reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater", 115 "infoframe", "cbus", "cec", "sdp", "txa", "txb" ; 116 interrupts-extended = <&gpio3 3 IRQ_TYPE_LEVEL_LOW>, 117 <&gpio3 4 IRQ_TYPE_LEVEL_LOW>; 118 interrupt-names = "intrq1", "intrq2"; 119 120 ports { 121 #address-cells = <1>; 122 #size-cells = <0>; 123 124 port@7 { 125 reg = <7>; 126 127 adv7482_ain7: endpoint { 128 remote-endpoint = <&cvbs_con>; 129 }; 130 }; 131 132 port@8 { 133 reg = <8>; 134 135 adv7482_hdmi: endpoint { 136 remote-endpoint = <&hdmi_in_con>; 137 }; 138 }; 139 140 port@a { 141 reg = <10>; 142 143 adv7482_txa: endpoint { 144 clock-lanes = <0>; 145 data-lanes = <1 2 3 4>; 146 remote-endpoint = <&csi40_in>; 147 }; 148 }; 149 }; 150 }; 151 152}; 153 154&csi40 { 155 status = "okay"; 156 157 ports { 158 #address-cells = <1>; 159 #size-cells = <0>; 160 161 port@0 { 162 reg = <0>; 163 164 csi40_in: endpoint { 165 clock-lanes = <0>; 166 data-lanes = <1 2 3 4>; 167 remote-endpoint = <&adv7482_txa>; 168 }; 169 }; 170 }; 171}; 172 173&pfc { 174 vin0_pins_parallel: vin0 { 175 groups = "vin0_data12", "vin0_sync", "vin0_clk", "vin0_clkenb"; 176 function = "vin0"; 177 }; 178}; 179 180&vin0 { 181 status = "okay"; 182 183 pinctrl-0 = <&vin0_pins_parallel>; 184 pinctrl-names = "default"; 185 186 ports { 187 #address-cells = <1>; 188 #size-cells = <0>; 189 190 port@0 { 191 reg = <0>; 192 193 vin0_in: endpoint { 194 pclk-sample = <0>; 195 hsync-active = <0>; 196 vsync-active = <0>; 197 remote-endpoint = <&adv7612_out>; 198 }; 199 }; 200 }; 201}; 202 203&vin1 { 204 status = "okay"; 205}; 206 207&vin2 { 208 status = "okay"; 209}; 210 211&vin3 { 212 status = "okay"; 213}; 214