1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC 4 * 5 * Copyright (C) 2016-2017 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a77961-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a77961-sysc.h> 11 12#define CPG_AUDIO_CLK_I R8A77961_CLK_S0D4 13 14/ { 15 compatible = "renesas,r8a77961"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* 20 * The external audio clocks are configured as 0 Hz fixed frequency 21 * clocks by default. 22 * Boards that provide audio clocks should override them. 23 */ 24 audio_clk_a: audio_clk_a { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <0>; 28 }; 29 30 audio_clk_b: audio_clk_b { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <0>; 34 }; 35 36 audio_clk_c: audio_clk_c { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <0>; 40 }; 41 42 /* External CAN clock - to be overridden by boards that provide it */ 43 can_clk: can { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <0>; 47 }; 48 49 cluster0_opp: opp_table0 { 50 compatible = "operating-points-v2"; 51 opp-shared; 52 53 opp-500000000 { 54 opp-hz = /bits/ 64 <500000000>; 55 opp-microvolt = <820000>; 56 clock-latency-ns = <300000>; 57 }; 58 opp-1000000000 { 59 opp-hz = /bits/ 64 <1000000000>; 60 opp-microvolt = <820000>; 61 clock-latency-ns = <300000>; 62 }; 63 opp-1500000000 { 64 opp-hz = /bits/ 64 <1500000000>; 65 opp-microvolt = <820000>; 66 clock-latency-ns = <300000>; 67 }; 68 opp-1600000000 { 69 opp-hz = /bits/ 64 <1600000000>; 70 opp-microvolt = <900000>; 71 clock-latency-ns = <300000>; 72 turbo-mode; 73 }; 74 opp-1700000000 { 75 opp-hz = /bits/ 64 <1700000000>; 76 opp-microvolt = <900000>; 77 clock-latency-ns = <300000>; 78 turbo-mode; 79 }; 80 opp-1800000000 { 81 opp-hz = /bits/ 64 <1800000000>; 82 opp-microvolt = <960000>; 83 clock-latency-ns = <300000>; 84 turbo-mode; 85 }; 86 }; 87 88 cluster1_opp: opp_table1 { 89 compatible = "operating-points-v2"; 90 opp-shared; 91 92 opp-800000000 { 93 opp-hz = /bits/ 64 <800000000>; 94 opp-microvolt = <820000>; 95 clock-latency-ns = <300000>; 96 }; 97 opp-1000000000 { 98 opp-hz = /bits/ 64 <1000000000>; 99 opp-microvolt = <820000>; 100 clock-latency-ns = <300000>; 101 }; 102 opp-1200000000 { 103 opp-hz = /bits/ 64 <1200000000>; 104 opp-microvolt = <820000>; 105 clock-latency-ns = <300000>; 106 }; 107 opp-1300000000 { 108 opp-hz = /bits/ 64 <1300000000>; 109 opp-microvolt = <820000>; 110 clock-latency-ns = <300000>; 111 turbo-mode; 112 }; 113 }; 114 115 cpus { 116 #address-cells = <1>; 117 #size-cells = <0>; 118 119 cpu-map { 120 cluster0 { 121 core0 { 122 cpu = <&a57_0>; 123 }; 124 core1 { 125 cpu = <&a57_1>; 126 }; 127 }; 128 129 cluster1 { 130 core0 { 131 cpu = <&a53_0>; 132 }; 133 core1 { 134 cpu = <&a53_1>; 135 }; 136 core2 { 137 cpu = <&a53_2>; 138 }; 139 core3 { 140 cpu = <&a53_3>; 141 }; 142 }; 143 }; 144 145 a57_0: cpu@0 { 146 compatible = "arm,cortex-a57"; 147 reg = <0x0>; 148 device_type = "cpu"; 149 power-domains = <&sysc R8A77961_PD_CA57_CPU0>; 150 next-level-cache = <&L2_CA57>; 151 enable-method = "psci"; 152 cpu-idle-states = <&CPU_SLEEP_0>; 153 dynamic-power-coefficient = <854>; 154 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; 155 operating-points-v2 = <&cluster0_opp>; 156 capacity-dmips-mhz = <1024>; 157 #cooling-cells = <2>; 158 }; 159 160 a57_1: cpu@1 { 161 compatible = "arm,cortex-a57"; 162 reg = <0x1>; 163 device_type = "cpu"; 164 power-domains = <&sysc R8A77961_PD_CA57_CPU1>; 165 next-level-cache = <&L2_CA57>; 166 enable-method = "psci"; 167 cpu-idle-states = <&CPU_SLEEP_0>; 168 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; 169 operating-points-v2 = <&cluster0_opp>; 170 capacity-dmips-mhz = <1024>; 171 #cooling-cells = <2>; 172 }; 173 174 a53_0: cpu@100 { 175 compatible = "arm,cortex-a53"; 176 reg = <0x100>; 177 device_type = "cpu"; 178 power-domains = <&sysc R8A77961_PD_CA53_CPU0>; 179 next-level-cache = <&L2_CA53>; 180 enable-method = "psci"; 181 cpu-idle-states = <&CPU_SLEEP_1>; 182 #cooling-cells = <2>; 183 dynamic-power-coefficient = <277>; 184 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 185 operating-points-v2 = <&cluster1_opp>; 186 capacity-dmips-mhz = <535>; 187 }; 188 189 a53_1: cpu@101 { 190 compatible = "arm,cortex-a53"; 191 reg = <0x101>; 192 device_type = "cpu"; 193 power-domains = <&sysc R8A77961_PD_CA53_CPU1>; 194 next-level-cache = <&L2_CA53>; 195 enable-method = "psci"; 196 cpu-idle-states = <&CPU_SLEEP_1>; 197 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 198 operating-points-v2 = <&cluster1_opp>; 199 capacity-dmips-mhz = <535>; 200 }; 201 202 a53_2: cpu@102 { 203 compatible = "arm,cortex-a53"; 204 reg = <0x102>; 205 device_type = "cpu"; 206 power-domains = <&sysc R8A77961_PD_CA53_CPU2>; 207 next-level-cache = <&L2_CA53>; 208 enable-method = "psci"; 209 cpu-idle-states = <&CPU_SLEEP_1>; 210 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 211 operating-points-v2 = <&cluster1_opp>; 212 capacity-dmips-mhz = <535>; 213 }; 214 215 a53_3: cpu@103 { 216 compatible = "arm,cortex-a53"; 217 reg = <0x103>; 218 device_type = "cpu"; 219 power-domains = <&sysc R8A77961_PD_CA53_CPU3>; 220 next-level-cache = <&L2_CA53>; 221 enable-method = "psci"; 222 cpu-idle-states = <&CPU_SLEEP_1>; 223 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 224 operating-points-v2 = <&cluster1_opp>; 225 capacity-dmips-mhz = <535>; 226 }; 227 228 L2_CA57: cache-controller-0 { 229 compatible = "cache"; 230 power-domains = <&sysc R8A77961_PD_CA57_SCU>; 231 cache-unified; 232 cache-level = <2>; 233 }; 234 235 L2_CA53: cache-controller-1 { 236 compatible = "cache"; 237 power-domains = <&sysc R8A77961_PD_CA53_SCU>; 238 cache-unified; 239 cache-level = <2>; 240 }; 241 242 idle-states { 243 entry-method = "psci"; 244 245 CPU_SLEEP_0: cpu-sleep-0 { 246 compatible = "arm,idle-state"; 247 arm,psci-suspend-param = <0x0010000>; 248 local-timer-stop; 249 entry-latency-us = <400>; 250 exit-latency-us = <500>; 251 min-residency-us = <4000>; 252 }; 253 254 CPU_SLEEP_1: cpu-sleep-1 { 255 compatible = "arm,idle-state"; 256 arm,psci-suspend-param = <0x0010000>; 257 local-timer-stop; 258 entry-latency-us = <700>; 259 exit-latency-us = <700>; 260 min-residency-us = <5000>; 261 }; 262 }; 263 }; 264 265 extal_clk: extal { 266 compatible = "fixed-clock"; 267 #clock-cells = <0>; 268 /* This value must be overridden by the board */ 269 clock-frequency = <0>; 270 }; 271 272 extalr_clk: extalr { 273 compatible = "fixed-clock"; 274 #clock-cells = <0>; 275 /* This value must be overridden by the board */ 276 clock-frequency = <0>; 277 }; 278 279 /* External PCIe clock - can be overridden by the board */ 280 pcie_bus_clk: pcie_bus { 281 compatible = "fixed-clock"; 282 #clock-cells = <0>; 283 clock-frequency = <0>; 284 }; 285 286 pmu_a53 { 287 compatible = "arm,cortex-a53-pmu"; 288 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 289 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 290 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 291 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 292 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 293 }; 294 295 pmu_a57 { 296 compatible = "arm,cortex-a57-pmu"; 297 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 298 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 299 interrupt-affinity = <&a57_0>, <&a57_1>; 300 }; 301 302 psci { 303 compatible = "arm,psci-1.0", "arm,psci-0.2"; 304 method = "smc"; 305 }; 306 307 /* External SCIF clock - to be overridden by boards that provide it */ 308 scif_clk: scif { 309 compatible = "fixed-clock"; 310 #clock-cells = <0>; 311 clock-frequency = <0>; 312 }; 313 314 soc { 315 compatible = "simple-bus"; 316 interrupt-parent = <&gic>; 317 #address-cells = <2>; 318 #size-cells = <2>; 319 ranges; 320 321 rwdt: watchdog@e6020000 { 322 compatible = "renesas,r8a77961-wdt", 323 "renesas,rcar-gen3-wdt"; 324 reg = <0 0xe6020000 0 0x0c>; 325 clocks = <&cpg CPG_MOD 402>; 326 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 327 resets = <&cpg 402>; 328 status = "disabled"; 329 }; 330 331 gpio0: gpio@e6050000 { 332 compatible = "renesas,gpio-r8a77961", 333 "renesas,rcar-gen3-gpio"; 334 reg = <0 0xe6050000 0 0x50>; 335 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 336 #gpio-cells = <2>; 337 gpio-controller; 338 gpio-ranges = <&pfc 0 0 16>; 339 #interrupt-cells = <2>; 340 interrupt-controller; 341 clocks = <&cpg CPG_MOD 912>; 342 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 343 resets = <&cpg 912>; 344 }; 345 346 gpio1: gpio@e6051000 { 347 compatible = "renesas,gpio-r8a77961", 348 "renesas,rcar-gen3-gpio"; 349 reg = <0 0xe6051000 0 0x50>; 350 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 351 #gpio-cells = <2>; 352 gpio-controller; 353 gpio-ranges = <&pfc 0 32 29>; 354 #interrupt-cells = <2>; 355 interrupt-controller; 356 clocks = <&cpg CPG_MOD 911>; 357 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 358 resets = <&cpg 911>; 359 }; 360 361 gpio2: gpio@e6052000 { 362 compatible = "renesas,gpio-r8a77961", 363 "renesas,rcar-gen3-gpio"; 364 reg = <0 0xe6052000 0 0x50>; 365 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 366 #gpio-cells = <2>; 367 gpio-controller; 368 gpio-ranges = <&pfc 0 64 15>; 369 #interrupt-cells = <2>; 370 interrupt-controller; 371 clocks = <&cpg CPG_MOD 910>; 372 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 373 resets = <&cpg 910>; 374 }; 375 376 gpio3: gpio@e6053000 { 377 compatible = "renesas,gpio-r8a77961", 378 "renesas,rcar-gen3-gpio"; 379 reg = <0 0xe6053000 0 0x50>; 380 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 381 #gpio-cells = <2>; 382 gpio-controller; 383 gpio-ranges = <&pfc 0 96 16>; 384 #interrupt-cells = <2>; 385 interrupt-controller; 386 clocks = <&cpg CPG_MOD 909>; 387 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 388 resets = <&cpg 909>; 389 }; 390 391 gpio4: gpio@e6054000 { 392 compatible = "renesas,gpio-r8a77961", 393 "renesas,rcar-gen3-gpio"; 394 reg = <0 0xe6054000 0 0x50>; 395 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 396 #gpio-cells = <2>; 397 gpio-controller; 398 gpio-ranges = <&pfc 0 128 18>; 399 #interrupt-cells = <2>; 400 interrupt-controller; 401 clocks = <&cpg CPG_MOD 908>; 402 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 403 resets = <&cpg 908>; 404 }; 405 406 gpio5: gpio@e6055000 { 407 compatible = "renesas,gpio-r8a77961", 408 "renesas,rcar-gen3-gpio"; 409 reg = <0 0xe6055000 0 0x50>; 410 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 411 #gpio-cells = <2>; 412 gpio-controller; 413 gpio-ranges = <&pfc 0 160 26>; 414 #interrupt-cells = <2>; 415 interrupt-controller; 416 clocks = <&cpg CPG_MOD 907>; 417 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 418 resets = <&cpg 907>; 419 }; 420 421 gpio6: gpio@e6055400 { 422 compatible = "renesas,gpio-r8a77961", 423 "renesas,rcar-gen3-gpio"; 424 reg = <0 0xe6055400 0 0x50>; 425 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 426 #gpio-cells = <2>; 427 gpio-controller; 428 gpio-ranges = <&pfc 0 192 32>; 429 #interrupt-cells = <2>; 430 interrupt-controller; 431 clocks = <&cpg CPG_MOD 906>; 432 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 433 resets = <&cpg 906>; 434 }; 435 436 gpio7: gpio@e6055800 { 437 compatible = "renesas,gpio-r8a77961", 438 "renesas,rcar-gen3-gpio"; 439 reg = <0 0xe6055800 0 0x50>; 440 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 441 #gpio-cells = <2>; 442 gpio-controller; 443 gpio-ranges = <&pfc 0 224 4>; 444 #interrupt-cells = <2>; 445 interrupt-controller; 446 clocks = <&cpg CPG_MOD 905>; 447 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 448 resets = <&cpg 905>; 449 }; 450 451 pfc: pinctrl@e6060000 { 452 compatible = "renesas,pfc-r8a77961"; 453 reg = <0 0xe6060000 0 0x50c>; 454 }; 455 456 cmt0: timer@e60f0000 { 457 compatible = "renesas,r8a77961-cmt0", 458 "renesas,rcar-gen3-cmt0"; 459 reg = <0 0xe60f0000 0 0x1004>; 460 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&cpg CPG_MOD 303>; 463 clock-names = "fck"; 464 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 465 resets = <&cpg 303>; 466 status = "disabled"; 467 }; 468 469 cmt1: timer@e6130000 { 470 compatible = "renesas,r8a77961-cmt1", 471 "renesas,rcar-gen3-cmt1"; 472 reg = <0 0xe6130000 0 0x1004>; 473 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&cpg CPG_MOD 302>; 482 clock-names = "fck"; 483 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 484 resets = <&cpg 302>; 485 status = "disabled"; 486 }; 487 488 cmt2: timer@e6140000 { 489 compatible = "renesas,r8a77961-cmt1", 490 "renesas,rcar-gen3-cmt1"; 491 reg = <0 0xe6140000 0 0x1004>; 492 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&cpg CPG_MOD 301>; 501 clock-names = "fck"; 502 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 503 resets = <&cpg 301>; 504 status = "disabled"; 505 }; 506 507 cmt3: timer@e6148000 { 508 compatible = "renesas,r8a77961-cmt1", 509 "renesas,rcar-gen3-cmt1"; 510 reg = <0 0xe6148000 0 0x1004>; 511 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&cpg CPG_MOD 300>; 520 clock-names = "fck"; 521 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 522 resets = <&cpg 300>; 523 status = "disabled"; 524 }; 525 526 cpg: clock-controller@e6150000 { 527 compatible = "renesas,r8a77961-cpg-mssr"; 528 reg = <0 0xe6150000 0 0x1000>; 529 clocks = <&extal_clk>, <&extalr_clk>; 530 clock-names = "extal", "extalr"; 531 #clock-cells = <2>; 532 #power-domain-cells = <0>; 533 #reset-cells = <1>; 534 }; 535 536 rst: reset-controller@e6160000 { 537 compatible = "renesas,r8a77961-rst"; 538 reg = <0 0xe6160000 0 0x0200>; 539 }; 540 541 sysc: system-controller@e6180000 { 542 compatible = "renesas,r8a77961-sysc"; 543 reg = <0 0xe6180000 0 0x0400>; 544 #power-domain-cells = <1>; 545 }; 546 547 tsc: thermal@e6198000 { 548 compatible = "renesas,r8a77961-thermal"; 549 reg = <0 0xe6198000 0 0x100>, 550 <0 0xe61a0000 0 0x100>, 551 <0 0xe61a8000 0 0x100>; 552 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&cpg CPG_MOD 522>; 556 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 557 resets = <&cpg 522>; 558 #thermal-sensor-cells = <1>; 559 }; 560 561 intc_ex: interrupt-controller@e61c0000 { 562 #interrupt-cells = <2>; 563 interrupt-controller; 564 reg = <0 0xe61c0000 0 0x200>; 565 /* placeholder */ 566 }; 567 568 tmu0: timer@e61e0000 { 569 compatible = "renesas,tmu-r8a77961", "renesas,tmu"; 570 reg = <0 0xe61e0000 0 0x30>; 571 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&cpg CPG_MOD 125>; 575 clock-names = "fck"; 576 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 577 resets = <&cpg 125>; 578 status = "disabled"; 579 }; 580 581 tmu1: timer@e6fc0000 { 582 compatible = "renesas,tmu-r8a77961", "renesas,tmu"; 583 reg = <0 0xe6fc0000 0 0x30>; 584 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&cpg CPG_MOD 124>; 588 clock-names = "fck"; 589 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 590 resets = <&cpg 124>; 591 status = "disabled"; 592 }; 593 594 tmu2: timer@e6fd0000 { 595 compatible = "renesas,tmu-r8a77961", "renesas,tmu"; 596 reg = <0 0xe6fd0000 0 0x30>; 597 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 600 clocks = <&cpg CPG_MOD 123>; 601 clock-names = "fck"; 602 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 603 resets = <&cpg 123>; 604 status = "disabled"; 605 }; 606 607 tmu3: timer@e6fe0000 { 608 compatible = "renesas,tmu-r8a77961", "renesas,tmu"; 609 reg = <0 0xe6fe0000 0 0x30>; 610 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&cpg CPG_MOD 122>; 614 clock-names = "fck"; 615 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 616 resets = <&cpg 122>; 617 status = "disabled"; 618 }; 619 620 tmu4: timer@ffc00000 { 621 compatible = "renesas,tmu-r8a77961", "renesas,tmu"; 622 reg = <0 0xffc00000 0 0x30>; 623 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&cpg CPG_MOD 121>; 627 clock-names = "fck"; 628 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 629 resets = <&cpg 121>; 630 status = "disabled"; 631 }; 632 633 i2c0: i2c@e6500000 { 634 #address-cells = <1>; 635 #size-cells = <0>; 636 compatible = "renesas,i2c-r8a77961", 637 "renesas,rcar-gen3-i2c"; 638 reg = <0 0xe6500000 0 0x40>; 639 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&cpg CPG_MOD 931>; 641 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 642 resets = <&cpg 931>; 643 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 644 <&dmac2 0x91>, <&dmac2 0x90>; 645 dma-names = "tx", "rx", "tx", "rx"; 646 i2c-scl-internal-delay-ns = <110>; 647 status = "disabled"; 648 }; 649 650 i2c1: i2c@e6508000 { 651 #address-cells = <1>; 652 #size-cells = <0>; 653 compatible = "renesas,i2c-r8a77961", 654 "renesas,rcar-gen3-i2c"; 655 reg = <0 0xe6508000 0 0x40>; 656 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 657 clocks = <&cpg CPG_MOD 930>; 658 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 659 resets = <&cpg 930>; 660 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 661 <&dmac2 0x93>, <&dmac2 0x92>; 662 dma-names = "tx", "rx", "tx", "rx"; 663 i2c-scl-internal-delay-ns = <6>; 664 status = "disabled"; 665 }; 666 667 i2c2: i2c@e6510000 { 668 #address-cells = <1>; 669 #size-cells = <0>; 670 compatible = "renesas,i2c-r8a77961", 671 "renesas,rcar-gen3-i2c"; 672 reg = <0 0xe6510000 0 0x40>; 673 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 674 clocks = <&cpg CPG_MOD 929>; 675 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 676 resets = <&cpg 929>; 677 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 678 <&dmac2 0x95>, <&dmac2 0x94>; 679 dma-names = "tx", "rx", "tx", "rx"; 680 i2c-scl-internal-delay-ns = <6>; 681 status = "disabled"; 682 }; 683 684 i2c3: i2c@e66d0000 { 685 #address-cells = <1>; 686 #size-cells = <0>; 687 compatible = "renesas,i2c-r8a77961", 688 "renesas,rcar-gen3-i2c"; 689 reg = <0 0xe66d0000 0 0x40>; 690 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 691 clocks = <&cpg CPG_MOD 928>; 692 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 693 resets = <&cpg 928>; 694 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 695 dma-names = "tx", "rx"; 696 i2c-scl-internal-delay-ns = <110>; 697 status = "disabled"; 698 }; 699 700 i2c4: i2c@e66d8000 { 701 #address-cells = <1>; 702 #size-cells = <0>; 703 compatible = "renesas,i2c-r8a77961", 704 "renesas,rcar-gen3-i2c"; 705 reg = <0 0xe66d8000 0 0x40>; 706 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&cpg CPG_MOD 927>; 708 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 709 resets = <&cpg 927>; 710 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 711 dma-names = "tx", "rx"; 712 i2c-scl-internal-delay-ns = <110>; 713 status = "disabled"; 714 }; 715 716 i2c5: i2c@e66e0000 { 717 #address-cells = <1>; 718 #size-cells = <0>; 719 compatible = "renesas,i2c-r8a77961", 720 "renesas,rcar-gen3-i2c"; 721 reg = <0 0xe66e0000 0 0x40>; 722 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&cpg CPG_MOD 919>; 724 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 725 resets = <&cpg 919>; 726 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 727 dma-names = "tx", "rx"; 728 i2c-scl-internal-delay-ns = <110>; 729 status = "disabled"; 730 }; 731 732 i2c6: i2c@e66e8000 { 733 #address-cells = <1>; 734 #size-cells = <0>; 735 compatible = "renesas,i2c-r8a77961", 736 "renesas,rcar-gen3-i2c"; 737 reg = <0 0xe66e8000 0 0x40>; 738 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&cpg CPG_MOD 918>; 740 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 741 resets = <&cpg 918>; 742 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 743 dma-names = "tx", "rx"; 744 i2c-scl-internal-delay-ns = <6>; 745 status = "disabled"; 746 }; 747 748 i2c_dvfs: i2c@e60b0000 { 749 #address-cells = <1>; 750 #size-cells = <0>; 751 compatible = "renesas,iic-r8a77961", 752 "renesas,rcar-gen3-iic", 753 "renesas,rmobile-iic"; 754 reg = <0 0xe60b0000 0 0x425>; 755 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&cpg CPG_MOD 926>; 757 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 758 resets = <&cpg 926>; 759 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 760 dma-names = "tx", "rx"; 761 status = "disabled"; 762 }; 763 764 hscif0: serial@e6540000 { 765 compatible = "renesas,hscif-r8a77961", 766 "renesas,rcar-gen3-hscif", 767 "renesas,hscif"; 768 reg = <0 0xe6540000 0 0x60>; 769 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 770 clocks = <&cpg CPG_MOD 520>, 771 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 772 <&scif_clk>; 773 clock-names = "fck", "brg_int", "scif_clk"; 774 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 775 <&dmac2 0x31>, <&dmac2 0x30>; 776 dma-names = "tx", "rx", "tx", "rx"; 777 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 778 resets = <&cpg 520>; 779 status = "disabled"; 780 }; 781 782 hscif1: serial@e6550000 { 783 compatible = "renesas,hscif-r8a77961", 784 "renesas,rcar-gen3-hscif", 785 "renesas,hscif"; 786 reg = <0 0xe6550000 0 0x60>; 787 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&cpg CPG_MOD 519>, 789 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 790 <&scif_clk>; 791 clock-names = "fck", "brg_int", "scif_clk"; 792 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 793 <&dmac2 0x33>, <&dmac2 0x32>; 794 dma-names = "tx", "rx", "tx", "rx"; 795 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 796 resets = <&cpg 519>; 797 status = "disabled"; 798 }; 799 800 hscif2: serial@e6560000 { 801 compatible = "renesas,hscif-r8a77961", 802 "renesas,rcar-gen3-hscif", 803 "renesas,hscif"; 804 reg = <0 0xe6560000 0 0x60>; 805 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 806 clocks = <&cpg CPG_MOD 518>, 807 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 808 <&scif_clk>; 809 clock-names = "fck", "brg_int", "scif_clk"; 810 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 811 <&dmac2 0x35>, <&dmac2 0x34>; 812 dma-names = "tx", "rx", "tx", "rx"; 813 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 814 resets = <&cpg 518>; 815 status = "disabled"; 816 }; 817 818 hscif3: serial@e66a0000 { 819 compatible = "renesas,hscif-r8a77961", 820 "renesas,rcar-gen3-hscif", 821 "renesas,hscif"; 822 reg = <0 0xe66a0000 0 0x60>; 823 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&cpg CPG_MOD 517>, 825 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 826 <&scif_clk>; 827 clock-names = "fck", "brg_int", "scif_clk"; 828 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 829 dma-names = "tx", "rx"; 830 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 831 resets = <&cpg 517>; 832 status = "disabled"; 833 }; 834 835 hscif4: serial@e66b0000 { 836 compatible = "renesas,hscif-r8a77961", 837 "renesas,rcar-gen3-hscif", 838 "renesas,hscif"; 839 reg = <0 0xe66b0000 0 0x60>; 840 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 841 clocks = <&cpg CPG_MOD 516>, 842 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 843 <&scif_clk>; 844 clock-names = "fck", "brg_int", "scif_clk"; 845 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 846 dma-names = "tx", "rx"; 847 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 848 resets = <&cpg 516>; 849 status = "disabled"; 850 }; 851 852 hsusb: usb@e6590000 { 853 compatible = "renesas,usbhs-r8a77961", 854 "renesas,rcar-gen3-usbhs"; 855 reg = <0 0xe6590000 0 0x200>; 856 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 857 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 858 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 859 <&usb_dmac1 0>, <&usb_dmac1 1>; 860 dma-names = "ch0", "ch1", "ch2", "ch3"; 861 renesas,buswait = <11>; 862 phys = <&usb2_phy0 3>; 863 phy-names = "usb"; 864 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 865 resets = <&cpg 704>, <&cpg 703>; 866 status = "disabled"; 867 }; 868 869 usb_dmac0: dma-controller@e65a0000 { 870 compatible = "renesas,r8a77961-usb-dmac", 871 "renesas,usb-dmac"; 872 reg = <0 0xe65a0000 0 0x100>; 873 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 875 interrupt-names = "ch0", "ch1"; 876 clocks = <&cpg CPG_MOD 330>; 877 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 878 resets = <&cpg 330>; 879 #dma-cells = <1>; 880 dma-channels = <2>; 881 }; 882 883 usb_dmac1: dma-controller@e65b0000 { 884 compatible = "renesas,r8a77961-usb-dmac", 885 "renesas,usb-dmac"; 886 reg = <0 0xe65b0000 0 0x100>; 887 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 889 interrupt-names = "ch0", "ch1"; 890 clocks = <&cpg CPG_MOD 331>; 891 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 892 resets = <&cpg 331>; 893 #dma-cells = <1>; 894 dma-channels = <2>; 895 }; 896 897 usb3_phy0: usb-phy@e65ee000 { 898 compatible = "renesas,r8a77961-usb3-phy", 899 "renesas,rcar-gen3-usb3-phy"; 900 reg = <0 0xe65ee000 0 0x90>; 901 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 902 <&usb_extal_clk>; 903 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 904 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 905 resets = <&cpg 328>; 906 #phy-cells = <0>; 907 status = "disabled"; 908 }; 909 910 arm_cc630p: crypto@e6601000 { 911 compatible = "arm,cryptocell-630p-ree"; 912 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 913 reg = <0x0 0xe6601000 0 0x1000>; 914 clocks = <&cpg CPG_MOD 229>; 915 resets = <&cpg 229>; 916 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 917 }; 918 919 dmac0: dma-controller@e6700000 { 920 compatible = "renesas,dmac-r8a77961", 921 "renesas,rcar-dmac"; 922 reg = <0 0xe6700000 0 0x10000>; 923 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 940 interrupt-names = "error", 941 "ch0", "ch1", "ch2", "ch3", 942 "ch4", "ch5", "ch6", "ch7", 943 "ch8", "ch9", "ch10", "ch11", 944 "ch12", "ch13", "ch14", "ch15"; 945 clocks = <&cpg CPG_MOD 219>; 946 clock-names = "fck"; 947 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 948 resets = <&cpg 219>; 949 #dma-cells = <1>; 950 dma-channels = <16>; 951 }; 952 953 dmac1: dma-controller@e7300000 { 954 compatible = "renesas,dmac-r8a77961", 955 "renesas,rcar-dmac"; 956 reg = <0 0xe7300000 0 0x10000>; 957 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 974 interrupt-names = "error", 975 "ch0", "ch1", "ch2", "ch3", 976 "ch4", "ch5", "ch6", "ch7", 977 "ch8", "ch9", "ch10", "ch11", 978 "ch12", "ch13", "ch14", "ch15"; 979 clocks = <&cpg CPG_MOD 218>; 980 clock-names = "fck"; 981 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 982 resets = <&cpg 218>; 983 #dma-cells = <1>; 984 dma-channels = <16>; 985 }; 986 987 dmac2: dma-controller@e7310000 { 988 compatible = "renesas,dmac-r8a77961", 989 "renesas,rcar-dmac"; 990 reg = <0 0xe7310000 0 0x10000>; 991 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 1001 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 1002 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 1003 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 1004 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 1005 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 1006 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 1007 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 1008 interrupt-names = "error", 1009 "ch0", "ch1", "ch2", "ch3", 1010 "ch4", "ch5", "ch6", "ch7", 1011 "ch8", "ch9", "ch10", "ch11", 1012 "ch12", "ch13", "ch14", "ch15"; 1013 clocks = <&cpg CPG_MOD 217>; 1014 clock-names = "fck"; 1015 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1016 resets = <&cpg 217>; 1017 #dma-cells = <1>; 1018 dma-channels = <16>; 1019 }; 1020 1021 ipmmu_ds0: iommu@e6740000 { 1022 compatible = "renesas,ipmmu-r8a77961"; 1023 reg = <0 0xe6740000 0 0x1000>; 1024 renesas,ipmmu-main = <&ipmmu_mm 0>; 1025 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1026 #iommu-cells = <1>; 1027 }; 1028 1029 ipmmu_ds1: iommu@e7740000 { 1030 compatible = "renesas,ipmmu-r8a77961"; 1031 reg = <0 0xe7740000 0 0x1000>; 1032 renesas,ipmmu-main = <&ipmmu_mm 1>; 1033 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1034 #iommu-cells = <1>; 1035 }; 1036 1037 ipmmu_hc: iommu@e6570000 { 1038 compatible = "renesas,ipmmu-r8a77961"; 1039 reg = <0 0xe6570000 0 0x1000>; 1040 renesas,ipmmu-main = <&ipmmu_mm 2>; 1041 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1042 #iommu-cells = <1>; 1043 }; 1044 1045 ipmmu_ir: iommu@ff8b0000 { 1046 compatible = "renesas,ipmmu-r8a77961"; 1047 reg = <0 0xff8b0000 0 0x1000>; 1048 renesas,ipmmu-main = <&ipmmu_mm 3>; 1049 power-domains = <&sysc R8A77961_PD_A3IR>; 1050 #iommu-cells = <1>; 1051 }; 1052 1053 ipmmu_mm: iommu@e67b0000 { 1054 compatible = "renesas,ipmmu-r8a77961"; 1055 reg = <0 0xe67b0000 0 0x1000>; 1056 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1058 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1059 #iommu-cells = <1>; 1060 }; 1061 1062 ipmmu_mp: iommu@ec670000 { 1063 compatible = "renesas,ipmmu-r8a77961"; 1064 reg = <0 0xec670000 0 0x1000>; 1065 renesas,ipmmu-main = <&ipmmu_mm 4>; 1066 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1067 #iommu-cells = <1>; 1068 }; 1069 1070 ipmmu_pv0: iommu@fd800000 { 1071 compatible = "renesas,ipmmu-r8a77961"; 1072 reg = <0 0xfd800000 0 0x1000>; 1073 renesas,ipmmu-main = <&ipmmu_mm 5>; 1074 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1075 #iommu-cells = <1>; 1076 }; 1077 1078 ipmmu_pv1: iommu@fd950000 { 1079 compatible = "renesas,ipmmu-r8a77961"; 1080 reg = <0 0xfd950000 0 0x1000>; 1081 renesas,ipmmu-main = <&ipmmu_mm 6>; 1082 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1083 #iommu-cells = <1>; 1084 }; 1085 1086 ipmmu_rt: iommu@ffc80000 { 1087 compatible = "renesas,ipmmu-r8a77961"; 1088 reg = <0 0xffc80000 0 0x1000>; 1089 renesas,ipmmu-main = <&ipmmu_mm 7>; 1090 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1091 #iommu-cells = <1>; 1092 }; 1093 1094 ipmmu_vc0: iommu@fe6b0000 { 1095 compatible = "renesas,ipmmu-r8a77961"; 1096 reg = <0 0xfe6b0000 0 0x1000>; 1097 renesas,ipmmu-main = <&ipmmu_mm 8>; 1098 power-domains = <&sysc R8A77961_PD_A3VC>; 1099 #iommu-cells = <1>; 1100 }; 1101 1102 ipmmu_vi0: iommu@febd0000 { 1103 compatible = "renesas,ipmmu-r8a77961"; 1104 reg = <0 0xfebd0000 0 0x1000>; 1105 renesas,ipmmu-main = <&ipmmu_mm 9>; 1106 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1107 #iommu-cells = <1>; 1108 }; 1109 1110 avb: ethernet@e6800000 { 1111 compatible = "renesas,etheravb-r8a77961", 1112 "renesas,etheravb-rcar-gen3"; 1113 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 1114 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1139 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1140 "ch4", "ch5", "ch6", "ch7", 1141 "ch8", "ch9", "ch10", "ch11", 1142 "ch12", "ch13", "ch14", "ch15", 1143 "ch16", "ch17", "ch18", "ch19", 1144 "ch20", "ch21", "ch22", "ch23", 1145 "ch24"; 1146 clocks = <&cpg CPG_MOD 812>; 1147 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1148 resets = <&cpg 812>; 1149 phy-mode = "rgmii"; 1150 rx-internal-delay-ps = <0>; 1151 tx-internal-delay-ps = <0>; 1152 #address-cells = <1>; 1153 #size-cells = <0>; 1154 status = "disabled"; 1155 }; 1156 1157 can0: can@e6c30000 { 1158 compatible = "renesas,can-r8a77961", 1159 "renesas,rcar-gen3-can"; 1160 reg = <0 0xe6c30000 0 0x1000>; 1161 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1162 clocks = <&cpg CPG_MOD 916>, 1163 <&cpg CPG_CORE R8A77961_CLK_CANFD>, 1164 <&can_clk>; 1165 clock-names = "clkp1", "clkp2", "can_clk"; 1166 assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>; 1167 assigned-clock-rates = <40000000>; 1168 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1169 resets = <&cpg 916>; 1170 status = "disabled"; 1171 }; 1172 1173 can1: can@e6c38000 { 1174 compatible = "renesas,can-r8a77961", 1175 "renesas,rcar-gen3-can"; 1176 reg = <0 0xe6c38000 0 0x1000>; 1177 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1178 clocks = <&cpg CPG_MOD 915>, 1179 <&cpg CPG_CORE R8A77961_CLK_CANFD>, 1180 <&can_clk>; 1181 clock-names = "clkp1", "clkp2", "can_clk"; 1182 assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>; 1183 assigned-clock-rates = <40000000>; 1184 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1185 resets = <&cpg 915>; 1186 status = "disabled"; 1187 }; 1188 1189 pwm0: pwm@e6e30000 { 1190 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1191 reg = <0 0xe6e30000 0 8>; 1192 #pwm-cells = <2>; 1193 clocks = <&cpg CPG_MOD 523>; 1194 resets = <&cpg 523>; 1195 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1196 status = "disabled"; 1197 }; 1198 1199 pwm1: pwm@e6e31000 { 1200 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1201 reg = <0 0xe6e31000 0 8>; 1202 #pwm-cells = <2>; 1203 clocks = <&cpg CPG_MOD 523>; 1204 resets = <&cpg 523>; 1205 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1206 status = "disabled"; 1207 }; 1208 1209 pwm2: pwm@e6e32000 { 1210 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1211 reg = <0 0xe6e32000 0 8>; 1212 #pwm-cells = <2>; 1213 clocks = <&cpg CPG_MOD 523>; 1214 resets = <&cpg 523>; 1215 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1216 status = "disabled"; 1217 }; 1218 1219 pwm3: pwm@e6e33000 { 1220 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1221 reg = <0 0xe6e33000 0 8>; 1222 #pwm-cells = <2>; 1223 clocks = <&cpg CPG_MOD 523>; 1224 resets = <&cpg 523>; 1225 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1226 status = "disabled"; 1227 }; 1228 1229 pwm4: pwm@e6e34000 { 1230 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1231 reg = <0 0xe6e34000 0 8>; 1232 #pwm-cells = <2>; 1233 clocks = <&cpg CPG_MOD 523>; 1234 resets = <&cpg 523>; 1235 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1236 status = "disabled"; 1237 }; 1238 1239 pwm5: pwm@e6e35000 { 1240 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1241 reg = <0 0xe6e35000 0 8>; 1242 #pwm-cells = <2>; 1243 clocks = <&cpg CPG_MOD 523>; 1244 resets = <&cpg 523>; 1245 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1246 status = "disabled"; 1247 }; 1248 1249 pwm6: pwm@e6e36000 { 1250 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1251 reg = <0 0xe6e36000 0 8>; 1252 #pwm-cells = <2>; 1253 clocks = <&cpg CPG_MOD 523>; 1254 resets = <&cpg 523>; 1255 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1256 status = "disabled"; 1257 }; 1258 1259 scif0: serial@e6e60000 { 1260 compatible = "renesas,scif-r8a77961", 1261 "renesas,rcar-gen3-scif", "renesas,scif"; 1262 reg = <0 0xe6e60000 0 64>; 1263 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1264 clocks = <&cpg CPG_MOD 207>, 1265 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1266 <&scif_clk>; 1267 clock-names = "fck", "brg_int", "scif_clk"; 1268 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1269 <&dmac2 0x51>, <&dmac2 0x50>; 1270 dma-names = "tx", "rx", "tx", "rx"; 1271 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1272 resets = <&cpg 207>; 1273 status = "disabled"; 1274 }; 1275 1276 scif1: serial@e6e68000 { 1277 compatible = "renesas,scif-r8a77961", 1278 "renesas,rcar-gen3-scif", "renesas,scif"; 1279 reg = <0 0xe6e68000 0 64>; 1280 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1281 clocks = <&cpg CPG_MOD 206>, 1282 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1283 <&scif_clk>; 1284 clock-names = "fck", "brg_int", "scif_clk"; 1285 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1286 <&dmac2 0x53>, <&dmac2 0x52>; 1287 dma-names = "tx", "rx", "tx", "rx"; 1288 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1289 resets = <&cpg 206>; 1290 status = "disabled"; 1291 }; 1292 1293 scif2: serial@e6e88000 { 1294 compatible = "renesas,scif-r8a77961", 1295 "renesas,rcar-gen3-scif", "renesas,scif"; 1296 reg = <0 0xe6e88000 0 64>; 1297 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1298 clocks = <&cpg CPG_MOD 310>, 1299 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1300 <&scif_clk>; 1301 clock-names = "fck", "brg_int", "scif_clk"; 1302 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1303 <&dmac2 0x13>, <&dmac2 0x12>; 1304 dma-names = "tx", "rx", "tx", "rx"; 1305 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1306 resets = <&cpg 310>; 1307 status = "disabled"; 1308 }; 1309 1310 scif3: serial@e6c50000 { 1311 compatible = "renesas,scif-r8a77961", 1312 "renesas,rcar-gen3-scif", "renesas,scif"; 1313 reg = <0 0xe6c50000 0 64>; 1314 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1315 clocks = <&cpg CPG_MOD 204>, 1316 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1317 <&scif_clk>; 1318 clock-names = "fck", "brg_int", "scif_clk"; 1319 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1320 dma-names = "tx", "rx"; 1321 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1322 resets = <&cpg 204>; 1323 status = "disabled"; 1324 }; 1325 1326 scif4: serial@e6c40000 { 1327 compatible = "renesas,scif-r8a77961", 1328 "renesas,rcar-gen3-scif", "renesas,scif"; 1329 reg = <0 0xe6c40000 0 64>; 1330 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1331 clocks = <&cpg CPG_MOD 203>, 1332 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1333 <&scif_clk>; 1334 clock-names = "fck", "brg_int", "scif_clk"; 1335 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1336 dma-names = "tx", "rx"; 1337 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1338 resets = <&cpg 203>; 1339 status = "disabled"; 1340 }; 1341 1342 scif5: serial@e6f30000 { 1343 compatible = "renesas,scif-r8a77961", 1344 "renesas,rcar-gen3-scif", "renesas,scif"; 1345 reg = <0 0xe6f30000 0 64>; 1346 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1347 clocks = <&cpg CPG_MOD 202>, 1348 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1349 <&scif_clk>; 1350 clock-names = "fck", "brg_int", "scif_clk"; 1351 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1352 <&dmac2 0x5b>, <&dmac2 0x5a>; 1353 dma-names = "tx", "rx", "tx", "rx"; 1354 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1355 resets = <&cpg 202>; 1356 status = "disabled"; 1357 }; 1358 1359 msiof0: spi@e6e90000 { 1360 compatible = "renesas,msiof-r8a77961", 1361 "renesas,rcar-gen3-msiof"; 1362 reg = <0 0xe6e90000 0 0x0064>; 1363 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1364 clocks = <&cpg CPG_MOD 211>; 1365 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1366 <&dmac2 0x41>, <&dmac2 0x40>; 1367 dma-names = "tx", "rx", "tx", "rx"; 1368 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1369 resets = <&cpg 211>; 1370 #address-cells = <1>; 1371 #size-cells = <0>; 1372 status = "disabled"; 1373 }; 1374 1375 msiof1: spi@e6ea0000 { 1376 compatible = "renesas,msiof-r8a77961", 1377 "renesas,rcar-gen3-msiof"; 1378 reg = <0 0xe6ea0000 0 0x0064>; 1379 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1380 clocks = <&cpg CPG_MOD 210>; 1381 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1382 <&dmac2 0x43>, <&dmac2 0x42>; 1383 dma-names = "tx", "rx", "tx", "rx"; 1384 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1385 resets = <&cpg 210>; 1386 #address-cells = <1>; 1387 #size-cells = <0>; 1388 status = "disabled"; 1389 }; 1390 1391 msiof2: spi@e6c00000 { 1392 compatible = "renesas,msiof-r8a77961", 1393 "renesas,rcar-gen3-msiof"; 1394 reg = <0 0xe6c00000 0 0x0064>; 1395 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1396 clocks = <&cpg CPG_MOD 209>; 1397 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1398 dma-names = "tx", "rx"; 1399 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1400 resets = <&cpg 209>; 1401 #address-cells = <1>; 1402 #size-cells = <0>; 1403 status = "disabled"; 1404 }; 1405 1406 msiof3: spi@e6c10000 { 1407 compatible = "renesas,msiof-r8a77961", 1408 "renesas,rcar-gen3-msiof"; 1409 reg = <0 0xe6c10000 0 0x0064>; 1410 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1411 clocks = <&cpg CPG_MOD 208>; 1412 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1413 dma-names = "tx", "rx"; 1414 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1415 resets = <&cpg 208>; 1416 #address-cells = <1>; 1417 #size-cells = <0>; 1418 status = "disabled"; 1419 }; 1420 1421 vin0: video@e6ef0000 { 1422 reg = <0 0xe6ef0000 0 0x1000>; 1423 /* placeholder */ 1424 }; 1425 1426 vin1: video@e6ef1000 { 1427 reg = <0 0xe6ef1000 0 0x1000>; 1428 /* placeholder */ 1429 }; 1430 1431 vin2: video@e6ef2000 { 1432 reg = <0 0xe6ef2000 0 0x1000>; 1433 /* placeholder */ 1434 }; 1435 1436 vin3: video@e6ef3000 { 1437 reg = <0 0xe6ef3000 0 0x1000>; 1438 /* placeholder */ 1439 }; 1440 1441 vin4: video@e6ef4000 { 1442 reg = <0 0xe6ef4000 0 0x1000>; 1443 /* placeholder */ 1444 }; 1445 1446 vin5: video@e6ef5000 { 1447 reg = <0 0xe6ef5000 0 0x1000>; 1448 /* placeholder */ 1449 }; 1450 1451 vin6: video@e6ef6000 { 1452 reg = <0 0xe6ef6000 0 0x1000>; 1453 /* placeholder */ 1454 }; 1455 1456 vin7: video@e6ef7000 { 1457 reg = <0 0xe6ef7000 0 0x1000>; 1458 /* placeholder */ 1459 }; 1460 1461 rcar_sound: sound@ec500000 { 1462 /* 1463 * #sound-dai-cells is required 1464 * 1465 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1466 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1467 */ 1468 /* 1469 * #clock-cells is required for audio_clkout0/1/2/3 1470 * 1471 * clkout : #clock-cells = <0>; <&rcar_sound>; 1472 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1473 */ 1474 compatible = "renesas,rcar_sound-r8a77961", "renesas,rcar_sound-gen3"; 1475 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1476 <0 0xec5a0000 0 0x100>, /* ADG */ 1477 <0 0xec540000 0 0x1000>, /* SSIU */ 1478 <0 0xec541000 0 0x280>, /* SSI */ 1479 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1480 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1481 1482 clocks = <&cpg CPG_MOD 1005>, 1483 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1484 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1485 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1486 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1487 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1488 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1489 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1490 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1491 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1492 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1493 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1494 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1495 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1496 <&audio_clk_a>, <&audio_clk_b>, 1497 <&audio_clk_c>, 1498 <&cpg CPG_CORE R8A77961_CLK_S0D4>; 1499 clock-names = "ssi-all", 1500 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1501 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1502 "ssi.1", "ssi.0", 1503 "src.9", "src.8", "src.7", "src.6", 1504 "src.5", "src.4", "src.3", "src.2", 1505 "src.1", "src.0", 1506 "mix.1", "mix.0", 1507 "ctu.1", "ctu.0", 1508 "dvc.0", "dvc.1", 1509 "clk_a", "clk_b", "clk_c", "clk_i"; 1510 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1511 resets = <&cpg 1005>, 1512 <&cpg 1006>, <&cpg 1007>, 1513 <&cpg 1008>, <&cpg 1009>, 1514 <&cpg 1010>, <&cpg 1011>, 1515 <&cpg 1012>, <&cpg 1013>, 1516 <&cpg 1014>, <&cpg 1015>; 1517 reset-names = "ssi-all", 1518 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1519 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1520 "ssi.1", "ssi.0"; 1521 status = "disabled"; 1522 1523 rcar_sound,ctu { 1524 ctu00: ctu-0 { }; 1525 ctu01: ctu-1 { }; 1526 ctu02: ctu-2 { }; 1527 ctu03: ctu-3 { }; 1528 ctu10: ctu-4 { }; 1529 ctu11: ctu-5 { }; 1530 ctu12: ctu-6 { }; 1531 ctu13: ctu-7 { }; 1532 }; 1533 1534 rcar_sound,dvc { 1535 dvc0: dvc-0 { 1536 dmas = <&audma1 0xbc>; 1537 dma-names = "tx"; 1538 }; 1539 dvc1: dvc-1 { 1540 dmas = <&audma1 0xbe>; 1541 dma-names = "tx"; 1542 }; 1543 }; 1544 1545 rcar_sound,mix { 1546 mix0: mix-0 { }; 1547 mix1: mix-1 { }; 1548 }; 1549 1550 rcar_sound,src { 1551 src0: src-0 { 1552 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1553 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1554 dma-names = "rx", "tx"; 1555 }; 1556 src1: src-1 { 1557 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1558 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1559 dma-names = "rx", "tx"; 1560 }; 1561 src2: src-2 { 1562 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1563 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1564 dma-names = "rx", "tx"; 1565 }; 1566 src3: src-3 { 1567 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1568 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1569 dma-names = "rx", "tx"; 1570 }; 1571 src4: src-4 { 1572 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1573 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1574 dma-names = "rx", "tx"; 1575 }; 1576 src5: src-5 { 1577 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1578 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1579 dma-names = "rx", "tx"; 1580 }; 1581 src6: src-6 { 1582 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1583 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1584 dma-names = "rx", "tx"; 1585 }; 1586 src7: src-7 { 1587 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1588 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1589 dma-names = "rx", "tx"; 1590 }; 1591 src8: src-8 { 1592 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1593 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1594 dma-names = "rx", "tx"; 1595 }; 1596 src9: src-9 { 1597 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1598 dmas = <&audma0 0x97>, <&audma1 0xba>; 1599 dma-names = "rx", "tx"; 1600 }; 1601 }; 1602 1603 rcar_sound,ssi { 1604 ssi0: ssi-0 { 1605 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1606 dmas = <&audma0 0x01>, <&audma1 0x02>; 1607 dma-names = "rx", "tx"; 1608 }; 1609 ssi1: ssi-1 { 1610 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1611 dmas = <&audma0 0x03>, <&audma1 0x04>; 1612 dma-names = "rx", "tx"; 1613 }; 1614 ssi2: ssi-2 { 1615 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1616 dmas = <&audma0 0x05>, <&audma1 0x06>; 1617 dma-names = "rx", "tx"; 1618 }; 1619 ssi3: ssi-3 { 1620 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1621 dmas = <&audma0 0x07>, <&audma1 0x08>; 1622 dma-names = "rx", "tx"; 1623 }; 1624 ssi4: ssi-4 { 1625 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1626 dmas = <&audma0 0x09>, <&audma1 0x0a>; 1627 dma-names = "rx", "tx"; 1628 }; 1629 ssi5: ssi-5 { 1630 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1631 dmas = <&audma0 0x0b>, <&audma1 0x0c>; 1632 dma-names = "rx", "tx"; 1633 }; 1634 ssi6: ssi-6 { 1635 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1636 dmas = <&audma0 0x0d>, <&audma1 0x0e>; 1637 dma-names = "rx", "tx"; 1638 }; 1639 ssi7: ssi-7 { 1640 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1641 dmas = <&audma0 0x0f>, <&audma1 0x10>; 1642 dma-names = "rx", "tx"; 1643 }; 1644 ssi8: ssi-8 { 1645 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1646 dmas = <&audma0 0x11>, <&audma1 0x12>; 1647 dma-names = "rx", "tx"; 1648 }; 1649 ssi9: ssi-9 { 1650 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1651 dmas = <&audma0 0x13>, <&audma1 0x14>; 1652 dma-names = "rx", "tx"; 1653 }; 1654 }; 1655 1656 rcar_sound,ssiu { 1657 ssiu00: ssiu-0 { 1658 dmas = <&audma0 0x15>, <&audma1 0x16>; 1659 dma-names = "rx", "tx"; 1660 }; 1661 ssiu01: ssiu-1 { 1662 dmas = <&audma0 0x35>, <&audma1 0x36>; 1663 dma-names = "rx", "tx"; 1664 }; 1665 ssiu02: ssiu-2 { 1666 dmas = <&audma0 0x37>, <&audma1 0x38>; 1667 dma-names = "rx", "tx"; 1668 }; 1669 ssiu03: ssiu-3 { 1670 dmas = <&audma0 0x47>, <&audma1 0x48>; 1671 dma-names = "rx", "tx"; 1672 }; 1673 ssiu04: ssiu-4 { 1674 dmas = <&audma0 0x3F>, <&audma1 0x40>; 1675 dma-names = "rx", "tx"; 1676 }; 1677 ssiu05: ssiu-5 { 1678 dmas = <&audma0 0x43>, <&audma1 0x44>; 1679 dma-names = "rx", "tx"; 1680 }; 1681 ssiu06: ssiu-6 { 1682 dmas = <&audma0 0x4F>, <&audma1 0x50>; 1683 dma-names = "rx", "tx"; 1684 }; 1685 ssiu07: ssiu-7 { 1686 dmas = <&audma0 0x53>, <&audma1 0x54>; 1687 dma-names = "rx", "tx"; 1688 }; 1689 ssiu10: ssiu-8 { 1690 dmas = <&audma0 0x49>, <&audma1 0x4a>; 1691 dma-names = "rx", "tx"; 1692 }; 1693 ssiu11: ssiu-9 { 1694 dmas = <&audma0 0x4B>, <&audma1 0x4C>; 1695 dma-names = "rx", "tx"; 1696 }; 1697 ssiu12: ssiu-10 { 1698 dmas = <&audma0 0x57>, <&audma1 0x58>; 1699 dma-names = "rx", "tx"; 1700 }; 1701 ssiu13: ssiu-11 { 1702 dmas = <&audma0 0x59>, <&audma1 0x5A>; 1703 dma-names = "rx", "tx"; 1704 }; 1705 ssiu14: ssiu-12 { 1706 dmas = <&audma0 0x5F>, <&audma1 0x60>; 1707 dma-names = "rx", "tx"; 1708 }; 1709 ssiu15: ssiu-13 { 1710 dmas = <&audma0 0xC3>, <&audma1 0xC4>; 1711 dma-names = "rx", "tx"; 1712 }; 1713 ssiu16: ssiu-14 { 1714 dmas = <&audma0 0xC7>, <&audma1 0xC8>; 1715 dma-names = "rx", "tx"; 1716 }; 1717 ssiu17: ssiu-15 { 1718 dmas = <&audma0 0xCB>, <&audma1 0xCC>; 1719 dma-names = "rx", "tx"; 1720 }; 1721 ssiu20: ssiu-16 { 1722 dmas = <&audma0 0x63>, <&audma1 0x64>; 1723 dma-names = "rx", "tx"; 1724 }; 1725 ssiu21: ssiu-17 { 1726 dmas = <&audma0 0x67>, <&audma1 0x68>; 1727 dma-names = "rx", "tx"; 1728 }; 1729 ssiu22: ssiu-18 { 1730 dmas = <&audma0 0x6B>, <&audma1 0x6C>; 1731 dma-names = "rx", "tx"; 1732 }; 1733 ssiu23: ssiu-19 { 1734 dmas = <&audma0 0x6D>, <&audma1 0x6E>; 1735 dma-names = "rx", "tx"; 1736 }; 1737 ssiu24: ssiu-20 { 1738 dmas = <&audma0 0xCF>, <&audma1 0xCE>; 1739 dma-names = "rx", "tx"; 1740 }; 1741 ssiu25: ssiu-21 { 1742 dmas = <&audma0 0xEB>, <&audma1 0xEC>; 1743 dma-names = "rx", "tx"; 1744 }; 1745 ssiu26: ssiu-22 { 1746 dmas = <&audma0 0xED>, <&audma1 0xEE>; 1747 dma-names = "rx", "tx"; 1748 }; 1749 ssiu27: ssiu-23 { 1750 dmas = <&audma0 0xEF>, <&audma1 0xF0>; 1751 dma-names = "rx", "tx"; 1752 }; 1753 ssiu30: ssiu-24 { 1754 dmas = <&audma0 0x6f>, <&audma1 0x70>; 1755 dma-names = "rx", "tx"; 1756 }; 1757 ssiu31: ssiu-25 { 1758 dmas = <&audma0 0x21>, <&audma1 0x22>; 1759 dma-names = "rx", "tx"; 1760 }; 1761 ssiu32: ssiu-26 { 1762 dmas = <&audma0 0x23>, <&audma1 0x24>; 1763 dma-names = "rx", "tx"; 1764 }; 1765 ssiu33: ssiu-27 { 1766 dmas = <&audma0 0x25>, <&audma1 0x26>; 1767 dma-names = "rx", "tx"; 1768 }; 1769 ssiu34: ssiu-28 { 1770 dmas = <&audma0 0x27>, <&audma1 0x28>; 1771 dma-names = "rx", "tx"; 1772 }; 1773 ssiu35: ssiu-29 { 1774 dmas = <&audma0 0x29>, <&audma1 0x2A>; 1775 dma-names = "rx", "tx"; 1776 }; 1777 ssiu36: ssiu-30 { 1778 dmas = <&audma0 0x2B>, <&audma1 0x2C>; 1779 dma-names = "rx", "tx"; 1780 }; 1781 ssiu37: ssiu-31 { 1782 dmas = <&audma0 0x2D>, <&audma1 0x2E>; 1783 dma-names = "rx", "tx"; 1784 }; 1785 ssiu40: ssiu-32 { 1786 dmas = <&audma0 0x71>, <&audma1 0x72>; 1787 dma-names = "rx", "tx"; 1788 }; 1789 ssiu41: ssiu-33 { 1790 dmas = <&audma0 0x17>, <&audma1 0x18>; 1791 dma-names = "rx", "tx"; 1792 }; 1793 ssiu42: ssiu-34 { 1794 dmas = <&audma0 0x19>, <&audma1 0x1A>; 1795 dma-names = "rx", "tx"; 1796 }; 1797 ssiu43: ssiu-35 { 1798 dmas = <&audma0 0x1B>, <&audma1 0x1C>; 1799 dma-names = "rx", "tx"; 1800 }; 1801 ssiu44: ssiu-36 { 1802 dmas = <&audma0 0x1D>, <&audma1 0x1E>; 1803 dma-names = "rx", "tx"; 1804 }; 1805 ssiu45: ssiu-37 { 1806 dmas = <&audma0 0x1F>, <&audma1 0x20>; 1807 dma-names = "rx", "tx"; 1808 }; 1809 ssiu46: ssiu-38 { 1810 dmas = <&audma0 0x31>, <&audma1 0x32>; 1811 dma-names = "rx", "tx"; 1812 }; 1813 ssiu47: ssiu-39 { 1814 dmas = <&audma0 0x33>, <&audma1 0x34>; 1815 dma-names = "rx", "tx"; 1816 }; 1817 ssiu50: ssiu-40 { 1818 dmas = <&audma0 0x73>, <&audma1 0x74>; 1819 dma-names = "rx", "tx"; 1820 }; 1821 ssiu60: ssiu-41 { 1822 dmas = <&audma0 0x75>, <&audma1 0x76>; 1823 dma-names = "rx", "tx"; 1824 }; 1825 ssiu70: ssiu-42 { 1826 dmas = <&audma0 0x79>, <&audma1 0x7a>; 1827 dma-names = "rx", "tx"; 1828 }; 1829 ssiu80: ssiu-43 { 1830 dmas = <&audma0 0x7b>, <&audma1 0x7c>; 1831 dma-names = "rx", "tx"; 1832 }; 1833 ssiu90: ssiu-44 { 1834 dmas = <&audma0 0x7d>, <&audma1 0x7e>; 1835 dma-names = "rx", "tx"; 1836 }; 1837 ssiu91: ssiu-45 { 1838 dmas = <&audma0 0x7F>, <&audma1 0x80>; 1839 dma-names = "rx", "tx"; 1840 }; 1841 ssiu92: ssiu-46 { 1842 dmas = <&audma0 0x81>, <&audma1 0x82>; 1843 dma-names = "rx", "tx"; 1844 }; 1845 ssiu93: ssiu-47 { 1846 dmas = <&audma0 0x83>, <&audma1 0x84>; 1847 dma-names = "rx", "tx"; 1848 }; 1849 ssiu94: ssiu-48 { 1850 dmas = <&audma0 0xA3>, <&audma1 0xA4>; 1851 dma-names = "rx", "tx"; 1852 }; 1853 ssiu95: ssiu-49 { 1854 dmas = <&audma0 0xA5>, <&audma1 0xA6>; 1855 dma-names = "rx", "tx"; 1856 }; 1857 ssiu96: ssiu-50 { 1858 dmas = <&audma0 0xA7>, <&audma1 0xA8>; 1859 dma-names = "rx", "tx"; 1860 }; 1861 ssiu97: ssiu-51 { 1862 dmas = <&audma0 0xA9>, <&audma1 0xAA>; 1863 dma-names = "rx", "tx"; 1864 }; 1865 }; 1866 }; 1867 1868 audma0: dma-controller@ec700000 { 1869 compatible = "renesas,dmac-r8a77961", 1870 "renesas,rcar-dmac"; 1871 reg = <0 0xec700000 0 0x10000>; 1872 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1877 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1879 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1880 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1883 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1884 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1885 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1886 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1887 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1888 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1889 interrupt-names = "error", 1890 "ch0", "ch1", "ch2", "ch3", 1891 "ch4", "ch5", "ch6", "ch7", 1892 "ch8", "ch9", "ch10", "ch11", 1893 "ch12", "ch13", "ch14", "ch15"; 1894 clocks = <&cpg CPG_MOD 502>; 1895 clock-names = "fck"; 1896 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1897 resets = <&cpg 502>; 1898 #dma-cells = <1>; 1899 dma-channels = <16>; 1900 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 1901 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 1902 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 1903 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 1904 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 1905 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 1906 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 1907 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 1908 }; 1909 1910 audma1: dma-controller@ec720000 { 1911 compatible = "renesas,dmac-r8a77961", 1912 "renesas,rcar-dmac"; 1913 reg = <0 0xec720000 0 0x10000>; 1914 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 1915 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1916 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1917 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1918 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1919 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1920 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1921 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1922 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1923 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1924 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1925 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 1926 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1927 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 1928 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1929 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 1930 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 1931 interrupt-names = "error", 1932 "ch0", "ch1", "ch2", "ch3", 1933 "ch4", "ch5", "ch6", "ch7", 1934 "ch8", "ch9", "ch10", "ch11", 1935 "ch12", "ch13", "ch14", "ch15"; 1936 clocks = <&cpg CPG_MOD 501>; 1937 clock-names = "fck"; 1938 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1939 resets = <&cpg 501>; 1940 #dma-cells = <1>; 1941 dma-channels = <16>; 1942 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, 1943 <&ipmmu_mp 18>, <&ipmmu_mp 19>, 1944 <&ipmmu_mp 20>, <&ipmmu_mp 21>, 1945 <&ipmmu_mp 22>, <&ipmmu_mp 23>, 1946 <&ipmmu_mp 24>, <&ipmmu_mp 25>, 1947 <&ipmmu_mp 26>, <&ipmmu_mp 27>, 1948 <&ipmmu_mp 28>, <&ipmmu_mp 29>, 1949 <&ipmmu_mp 30>, <&ipmmu_mp 31>; 1950 }; 1951 1952 xhci0: usb@ee000000 { 1953 compatible = "renesas,xhci-r8a77961", 1954 "renesas,rcar-gen3-xhci"; 1955 reg = <0 0xee000000 0 0xc00>; 1956 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1957 clocks = <&cpg CPG_MOD 328>; 1958 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1959 resets = <&cpg 328>; 1960 status = "disabled"; 1961 }; 1962 1963 usb3_peri0: usb@ee020000 { 1964 compatible = "renesas,r8a77961-usb3-peri", 1965 "renesas,rcar-gen3-usb3-peri"; 1966 reg = <0 0xee020000 0 0x400>; 1967 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1968 clocks = <&cpg CPG_MOD 328>; 1969 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1970 resets = <&cpg 328>; 1971 status = "disabled"; 1972 }; 1973 1974 ohci0: usb@ee080000 { 1975 compatible = "generic-ohci"; 1976 reg = <0 0xee080000 0 0x100>; 1977 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1978 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1979 phys = <&usb2_phy0 1>; 1980 phy-names = "usb"; 1981 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1982 resets = <&cpg 703>, <&cpg 704>; 1983 status = "disabled"; 1984 }; 1985 1986 ohci1: usb@ee0a0000 { 1987 compatible = "generic-ohci"; 1988 reg = <0 0xee0a0000 0 0x100>; 1989 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1990 clocks = <&cpg CPG_MOD 702>; 1991 phys = <&usb2_phy1 1>; 1992 phy-names = "usb"; 1993 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1994 resets = <&cpg 702>; 1995 status = "disabled"; 1996 }; 1997 1998 ehci0: usb@ee080100 { 1999 compatible = "generic-ehci"; 2000 reg = <0 0xee080100 0 0x100>; 2001 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2002 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2003 phys = <&usb2_phy0 2>; 2004 phy-names = "usb"; 2005 companion = <&ohci0>; 2006 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2007 resets = <&cpg 703>, <&cpg 704>; 2008 status = "disabled"; 2009 }; 2010 2011 ehci1: usb@ee0a0100 { 2012 compatible = "generic-ehci"; 2013 reg = <0 0xee0a0100 0 0x100>; 2014 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2015 clocks = <&cpg CPG_MOD 702>; 2016 phys = <&usb2_phy1 2>; 2017 phy-names = "usb"; 2018 companion = <&ohci1>; 2019 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2020 resets = <&cpg 702>; 2021 status = "disabled"; 2022 }; 2023 2024 usb2_phy0: usb-phy@ee080200 { 2025 compatible = "renesas,usb2-phy-r8a77961", 2026 "renesas,rcar-gen3-usb2-phy"; 2027 reg = <0 0xee080200 0 0x700>; 2028 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2029 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2030 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2031 resets = <&cpg 703>, <&cpg 704>; 2032 #phy-cells = <1>; 2033 status = "disabled"; 2034 }; 2035 2036 usb2_phy1: usb-phy@ee0a0200 { 2037 compatible = "renesas,usb2-phy-r8a77961", 2038 "renesas,rcar-gen3-usb2-phy"; 2039 reg = <0 0xee0a0200 0 0x700>; 2040 clocks = <&cpg CPG_MOD 702>; 2041 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2042 resets = <&cpg 702>; 2043 #phy-cells = <1>; 2044 status = "disabled"; 2045 }; 2046 2047 sdhi0: mmc@ee100000 { 2048 compatible = "renesas,sdhi-r8a77961", 2049 "renesas,rcar-gen3-sdhi"; 2050 reg = <0 0xee100000 0 0x2000>; 2051 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 2052 clocks = <&cpg CPG_MOD 314>; 2053 max-frequency = <200000000>; 2054 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2055 resets = <&cpg 314>; 2056 status = "disabled"; 2057 }; 2058 2059 sdhi1: mmc@ee120000 { 2060 compatible = "renesas,sdhi-r8a77961", 2061 "renesas,rcar-gen3-sdhi"; 2062 reg = <0 0xee120000 0 0x2000>; 2063 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 2064 clocks = <&cpg CPG_MOD 313>; 2065 max-frequency = <200000000>; 2066 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2067 resets = <&cpg 313>; 2068 status = "disabled"; 2069 }; 2070 2071 sdhi2: mmc@ee140000 { 2072 compatible = "renesas,sdhi-r8a77961", 2073 "renesas,rcar-gen3-sdhi"; 2074 reg = <0 0xee140000 0 0x2000>; 2075 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 2076 clocks = <&cpg CPG_MOD 312>; 2077 max-frequency = <200000000>; 2078 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2079 resets = <&cpg 312>; 2080 status = "disabled"; 2081 }; 2082 2083 sdhi3: mmc@ee160000 { 2084 compatible = "renesas,sdhi-r8a77961", 2085 "renesas,rcar-gen3-sdhi"; 2086 reg = <0 0xee160000 0 0x2000>; 2087 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 2088 clocks = <&cpg CPG_MOD 311>; 2089 max-frequency = <200000000>; 2090 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2091 resets = <&cpg 311>; 2092 status = "disabled"; 2093 }; 2094 2095 gic: interrupt-controller@f1010000 { 2096 compatible = "arm,gic-400"; 2097 #interrupt-cells = <3>; 2098 #address-cells = <0>; 2099 interrupt-controller; 2100 reg = <0x0 0xf1010000 0 0x1000>, 2101 <0x0 0xf1020000 0 0x20000>, 2102 <0x0 0xf1040000 0 0x20000>, 2103 <0x0 0xf1060000 0 0x20000>; 2104 interrupts = <GIC_PPI 9 2105 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 2106 clocks = <&cpg CPG_MOD 408>; 2107 clock-names = "clk"; 2108 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2109 resets = <&cpg 408>; 2110 }; 2111 2112 pciec0: pcie@fe000000 { 2113 compatible = "renesas,pcie-r8a77961", 2114 "renesas,pcie-rcar-gen3"; 2115 reg = <0 0xfe000000 0 0x80000>; 2116 #address-cells = <3>; 2117 #size-cells = <2>; 2118 bus-range = <0x00 0xff>; 2119 device_type = "pci"; 2120 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 2121 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 2122 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 2123 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 2124 /* Map all possible DDR as inbound ranges */ 2125 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2126 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2127 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2128 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2129 #interrupt-cells = <1>; 2130 interrupt-map-mask = <0 0 0 0>; 2131 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2132 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 2133 clock-names = "pcie", "pcie_bus"; 2134 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2135 resets = <&cpg 319>; 2136 status = "disabled"; 2137 }; 2138 2139 pciec1: pcie@ee800000 { 2140 compatible = "renesas,pcie-r8a77961", 2141 "renesas,pcie-rcar-gen3"; 2142 reg = <0 0xee800000 0 0x80000>; 2143 #address-cells = <3>; 2144 #size-cells = <2>; 2145 bus-range = <0x00 0xff>; 2146 device_type = "pci"; 2147 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, 2148 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, 2149 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, 2150 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 2151 /* Map all possible DDR as inbound ranges */ 2152 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2153 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2154 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2155 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2156 #interrupt-cells = <1>; 2157 interrupt-map-mask = <0 0 0 0>; 2158 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2159 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 2160 clock-names = "pcie", "pcie_bus"; 2161 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2162 resets = <&cpg 318>; 2163 status = "disabled"; 2164 }; 2165 2166 fcpf0: fcp@fe950000 { 2167 compatible = "renesas,fcpf"; 2168 reg = <0 0xfe950000 0 0x200>; 2169 clocks = <&cpg CPG_MOD 615>; 2170 power-domains = <&sysc R8A77961_PD_A3VC>; 2171 resets = <&cpg 615>; 2172 }; 2173 2174 fcpvb0: fcp@fe96f000 { 2175 compatible = "renesas,fcpv"; 2176 reg = <0 0xfe96f000 0 0x200>; 2177 clocks = <&cpg CPG_MOD 607>; 2178 power-domains = <&sysc R8A77961_PD_A3VC>; 2179 resets = <&cpg 607>; 2180 }; 2181 2182 fcpvi0: fcp@fe9af000 { 2183 compatible = "renesas,fcpv"; 2184 reg = <0 0xfe9af000 0 0x200>; 2185 clocks = <&cpg CPG_MOD 611>; 2186 power-domains = <&sysc R8A77961_PD_A3VC>; 2187 resets = <&cpg 611>; 2188 iommus = <&ipmmu_vc0 19>; 2189 }; 2190 2191 fcpvd0: fcp@fea27000 { 2192 compatible = "renesas,fcpv"; 2193 reg = <0 0xfea27000 0 0x200>; 2194 clocks = <&cpg CPG_MOD 603>; 2195 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2196 resets = <&cpg 603>; 2197 iommus = <&ipmmu_vi0 8>; 2198 }; 2199 2200 fcpvd1: fcp@fea2f000 { 2201 compatible = "renesas,fcpv"; 2202 reg = <0 0xfea2f000 0 0x200>; 2203 clocks = <&cpg CPG_MOD 602>; 2204 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2205 resets = <&cpg 602>; 2206 iommus = <&ipmmu_vi0 9>; 2207 }; 2208 2209 fcpvd2: fcp@fea37000 { 2210 compatible = "renesas,fcpv"; 2211 reg = <0 0xfea37000 0 0x200>; 2212 clocks = <&cpg CPG_MOD 601>; 2213 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2214 resets = <&cpg 601>; 2215 iommus = <&ipmmu_vi0 10>; 2216 }; 2217 2218 vspb: vsp@fe960000 { 2219 compatible = "renesas,vsp2"; 2220 reg = <0 0xfe960000 0 0x8000>; 2221 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 2222 clocks = <&cpg CPG_MOD 626>; 2223 power-domains = <&sysc R8A77961_PD_A3VC>; 2224 resets = <&cpg 626>; 2225 2226 renesas,fcp = <&fcpvb0>; 2227 }; 2228 2229 vspd0: vsp@fea20000 { 2230 compatible = "renesas,vsp2"; 2231 reg = <0 0xfea20000 0 0x5000>; 2232 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 2233 clocks = <&cpg CPG_MOD 623>; 2234 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2235 resets = <&cpg 623>; 2236 2237 renesas,fcp = <&fcpvd0>; 2238 }; 2239 2240 vspd1: vsp@fea28000 { 2241 compatible = "renesas,vsp2"; 2242 reg = <0 0xfea28000 0 0x5000>; 2243 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 2244 clocks = <&cpg CPG_MOD 622>; 2245 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2246 resets = <&cpg 622>; 2247 2248 renesas,fcp = <&fcpvd1>; 2249 }; 2250 2251 vspd2: vsp@fea30000 { 2252 compatible = "renesas,vsp2"; 2253 reg = <0 0xfea30000 0 0x5000>; 2254 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 2255 clocks = <&cpg CPG_MOD 621>; 2256 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2257 resets = <&cpg 621>; 2258 2259 renesas,fcp = <&fcpvd2>; 2260 }; 2261 2262 vspi0: vsp@fe9a0000 { 2263 compatible = "renesas,vsp2"; 2264 reg = <0 0xfe9a0000 0 0x8000>; 2265 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 2266 clocks = <&cpg CPG_MOD 631>; 2267 power-domains = <&sysc R8A77961_PD_A3VC>; 2268 resets = <&cpg 631>; 2269 2270 renesas,fcp = <&fcpvi0>; 2271 }; 2272 2273 csi20: csi2@fea80000 { 2274 reg = <0 0xfea80000 0 0x10000>; 2275 /* placeholder */ 2276 2277 ports { 2278 #address-cells = <1>; 2279 #size-cells = <0>; 2280 2281 port@1 { 2282 #address-cells = <1>; 2283 #size-cells = <0>; 2284 reg = <1>; 2285 }; 2286 }; 2287 }; 2288 2289 csi40: csi2@feaa0000 { 2290 reg = <0 0xfeaa0000 0 0x10000>; 2291 /* placeholder */ 2292 2293 ports { 2294 #address-cells = <1>; 2295 #size-cells = <0>; 2296 2297 port@1 { 2298 #address-cells = <1>; 2299 #size-cells = <0>; 2300 2301 reg = <1>; 2302 }; 2303 }; 2304 }; 2305 2306 hdmi0: hdmi@fead0000 { 2307 compatible = "renesas,r8a77961-hdmi", "renesas,rcar-gen3-hdmi"; 2308 reg = <0 0xfead0000 0 0x10000>; 2309 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 2310 clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A77961_CLK_HDMI>; 2311 clock-names = "iahb", "isfr"; 2312 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2313 resets = <&cpg 729>; 2314 status = "disabled"; 2315 2316 ports { 2317 #address-cells = <1>; 2318 #size-cells = <0>; 2319 port@0 { 2320 reg = <0>; 2321 dw_hdmi0_in: endpoint { 2322 remote-endpoint = <&du_out_hdmi0>; 2323 }; 2324 }; 2325 port@1 { 2326 reg = <1>; 2327 }; 2328 port@2 { 2329 /* HDMI sound */ 2330 reg = <2>; 2331 }; 2332 }; 2333 }; 2334 2335 du: display@feb00000 { 2336 compatible = "renesas,du-r8a77961"; 2337 reg = <0 0xfeb00000 0 0x70000>; 2338 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2339 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2340 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2341 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, 2342 <&cpg CPG_MOD 722>; 2343 clock-names = "du.0", "du.1", "du.2"; 2344 resets = <&cpg 724>, <&cpg 722>; 2345 reset-names = "du.0", "du.2"; 2346 2347 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; 2348 status = "disabled"; 2349 2350 ports { 2351 #address-cells = <1>; 2352 #size-cells = <0>; 2353 2354 port@0 { 2355 reg = <0>; 2356 du_out_rgb: endpoint { 2357 }; 2358 }; 2359 port@1 { 2360 reg = <1>; 2361 du_out_hdmi0: endpoint { 2362 remote-endpoint = <&dw_hdmi0_in>; 2363 }; 2364 }; 2365 port@2 { 2366 reg = <2>; 2367 du_out_lvds0: endpoint { 2368 }; 2369 }; 2370 }; 2371 }; 2372 2373 prr: chipid@fff00044 { 2374 compatible = "renesas,prr"; 2375 reg = <0 0xfff00044 0 4>; 2376 }; 2377 }; 2378 2379 thermal-zones { 2380 sensor_thermal1: sensor-thermal1 { 2381 polling-delay-passive = <250>; 2382 polling-delay = <1000>; 2383 thermal-sensors = <&tsc 0>; 2384 sustainable-power = <3874>; 2385 2386 trips { 2387 sensor1_crit: sensor1-crit { 2388 temperature = <120000>; 2389 hysteresis = <1000>; 2390 type = "critical"; 2391 }; 2392 }; 2393 }; 2394 2395 sensor_thermal2: sensor-thermal2 { 2396 polling-delay-passive = <250>; 2397 polling-delay = <1000>; 2398 thermal-sensors = <&tsc 1>; 2399 sustainable-power = <3874>; 2400 2401 trips { 2402 sensor2_crit: sensor2-crit { 2403 temperature = <120000>; 2404 hysteresis = <1000>; 2405 type = "critical"; 2406 }; 2407 }; 2408 }; 2409 2410 sensor_thermal3: sensor-thermal3 { 2411 polling-delay-passive = <250>; 2412 polling-delay = <1000>; 2413 thermal-sensors = <&tsc 2>; 2414 sustainable-power = <3874>; 2415 2416 cooling-maps { 2417 map0 { 2418 trip = <&target>; 2419 cooling-device = <&a57_0 2 4>; 2420 contribution = <1024>; 2421 }; 2422 map1 { 2423 trip = <&target>; 2424 cooling-device = <&a53_0 0 2>; 2425 contribution = <1024>; 2426 }; 2427 }; 2428 trips { 2429 target: trip-point1 { 2430 temperature = <100000>; 2431 hysteresis = <1000>; 2432 type = "passive"; 2433 }; 2434 2435 sensor3_crit: sensor3-crit { 2436 temperature = <120000>; 2437 hysteresis = <1000>; 2438 type = "critical"; 2439 }; 2440 }; 2441 }; 2442 }; 2443 2444 timer { 2445 compatible = "arm,armv8-timer"; 2446 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2447 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2448 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2449 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 2450 }; 2451 2452 /* External USB clocks - can be overridden by the board */ 2453 usb3s0_clk: usb3s0 { 2454 compatible = "fixed-clock"; 2455 #clock-cells = <0>; 2456 clock-frequency = <0>; 2457 }; 2458 2459 usb_extal_clk: usb_extal { 2460 compatible = "fixed-clock"; 2461 #clock-cells = <0>; 2462 clock-frequency = <0>; 2463 }; 2464}; 2465