1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC 4 * 5 * Copyright (C) 2016-2017 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a77961-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a77961-sysc.h> 11 12#define CPG_AUDIO_CLK_I R8A77961_CLK_S0D4 13 14/ { 15 compatible = "renesas,r8a77961"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* 20 * The external audio clocks are configured as 0 Hz fixed frequency 21 * clocks by default. 22 * Boards that provide audio clocks should override them. 23 */ 24 audio_clk_a: audio_clk_a { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <0>; 28 }; 29 30 audio_clk_b: audio_clk_b { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <0>; 34 }; 35 36 audio_clk_c: audio_clk_c { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <0>; 40 }; 41 42 /* External CAN clock - to be overridden by boards that provide it */ 43 can_clk: can { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <0>; 47 }; 48 49 cluster0_opp: opp_table0 { 50 compatible = "operating-points-v2"; 51 opp-shared; 52 53 opp-500000000 { 54 opp-hz = /bits/ 64 <500000000>; 55 opp-microvolt = <820000>; 56 clock-latency-ns = <300000>; 57 }; 58 opp-1000000000 { 59 opp-hz = /bits/ 64 <1000000000>; 60 opp-microvolt = <820000>; 61 clock-latency-ns = <300000>; 62 }; 63 opp-1500000000 { 64 opp-hz = /bits/ 64 <1500000000>; 65 opp-microvolt = <820000>; 66 clock-latency-ns = <300000>; 67 }; 68 opp-1600000000 { 69 opp-hz = /bits/ 64 <1600000000>; 70 opp-microvolt = <900000>; 71 clock-latency-ns = <300000>; 72 turbo-mode; 73 }; 74 opp-1700000000 { 75 opp-hz = /bits/ 64 <1700000000>; 76 opp-microvolt = <900000>; 77 clock-latency-ns = <300000>; 78 turbo-mode; 79 }; 80 opp-1800000000 { 81 opp-hz = /bits/ 64 <1800000000>; 82 opp-microvolt = <960000>; 83 clock-latency-ns = <300000>; 84 turbo-mode; 85 }; 86 }; 87 88 cluster1_opp: opp_table1 { 89 compatible = "operating-points-v2"; 90 opp-shared; 91 92 opp-800000000 { 93 opp-hz = /bits/ 64 <800000000>; 94 opp-microvolt = <820000>; 95 clock-latency-ns = <300000>; 96 }; 97 opp-1000000000 { 98 opp-hz = /bits/ 64 <1000000000>; 99 opp-microvolt = <820000>; 100 clock-latency-ns = <300000>; 101 }; 102 opp-1200000000 { 103 opp-hz = /bits/ 64 <1200000000>; 104 opp-microvolt = <820000>; 105 clock-latency-ns = <300000>; 106 }; 107 opp-1300000000 { 108 opp-hz = /bits/ 64 <1300000000>; 109 opp-microvolt = <820000>; 110 clock-latency-ns = <300000>; 111 turbo-mode; 112 }; 113 }; 114 115 cpus { 116 #address-cells = <1>; 117 #size-cells = <0>; 118 119 cpu-map { 120 cluster0 { 121 core0 { 122 cpu = <&a57_0>; 123 }; 124 core1 { 125 cpu = <&a57_1>; 126 }; 127 }; 128 129 cluster1 { 130 core0 { 131 cpu = <&a53_0>; 132 }; 133 core1 { 134 cpu = <&a53_1>; 135 }; 136 core2 { 137 cpu = <&a53_2>; 138 }; 139 core3 { 140 cpu = <&a53_3>; 141 }; 142 }; 143 }; 144 145 a57_0: cpu@0 { 146 compatible = "arm,cortex-a57"; 147 reg = <0x0>; 148 device_type = "cpu"; 149 power-domains = <&sysc R8A77961_PD_CA57_CPU0>; 150 next-level-cache = <&L2_CA57>; 151 enable-method = "psci"; 152 cpu-idle-states = <&CPU_SLEEP_0>; 153 dynamic-power-coefficient = <854>; 154 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; 155 operating-points-v2 = <&cluster0_opp>; 156 capacity-dmips-mhz = <1024>; 157 #cooling-cells = <2>; 158 }; 159 160 a57_1: cpu@1 { 161 compatible = "arm,cortex-a57"; 162 reg = <0x1>; 163 device_type = "cpu"; 164 power-domains = <&sysc R8A77961_PD_CA57_CPU1>; 165 next-level-cache = <&L2_CA57>; 166 enable-method = "psci"; 167 cpu-idle-states = <&CPU_SLEEP_0>; 168 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; 169 operating-points-v2 = <&cluster0_opp>; 170 capacity-dmips-mhz = <1024>; 171 #cooling-cells = <2>; 172 }; 173 174 a53_0: cpu@100 { 175 compatible = "arm,cortex-a53"; 176 reg = <0x100>; 177 device_type = "cpu"; 178 power-domains = <&sysc R8A77961_PD_CA53_CPU0>; 179 next-level-cache = <&L2_CA53>; 180 enable-method = "psci"; 181 cpu-idle-states = <&CPU_SLEEP_1>; 182 #cooling-cells = <2>; 183 dynamic-power-coefficient = <277>; 184 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 185 operating-points-v2 = <&cluster1_opp>; 186 capacity-dmips-mhz = <535>; 187 }; 188 189 a53_1: cpu@101 { 190 compatible = "arm,cortex-a53"; 191 reg = <0x101>; 192 device_type = "cpu"; 193 power-domains = <&sysc R8A77961_PD_CA53_CPU1>; 194 next-level-cache = <&L2_CA53>; 195 enable-method = "psci"; 196 cpu-idle-states = <&CPU_SLEEP_1>; 197 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 198 operating-points-v2 = <&cluster1_opp>; 199 capacity-dmips-mhz = <535>; 200 }; 201 202 a53_2: cpu@102 { 203 compatible = "arm,cortex-a53"; 204 reg = <0x102>; 205 device_type = "cpu"; 206 power-domains = <&sysc R8A77961_PD_CA53_CPU2>; 207 next-level-cache = <&L2_CA53>; 208 enable-method = "psci"; 209 cpu-idle-states = <&CPU_SLEEP_1>; 210 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 211 operating-points-v2 = <&cluster1_opp>; 212 capacity-dmips-mhz = <535>; 213 }; 214 215 a53_3: cpu@103 { 216 compatible = "arm,cortex-a53"; 217 reg = <0x103>; 218 device_type = "cpu"; 219 power-domains = <&sysc R8A77961_PD_CA53_CPU3>; 220 next-level-cache = <&L2_CA53>; 221 enable-method = "psci"; 222 cpu-idle-states = <&CPU_SLEEP_1>; 223 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 224 operating-points-v2 = <&cluster1_opp>; 225 capacity-dmips-mhz = <535>; 226 }; 227 228 L2_CA57: cache-controller-0 { 229 compatible = "cache"; 230 power-domains = <&sysc R8A77961_PD_CA57_SCU>; 231 cache-unified; 232 cache-level = <2>; 233 }; 234 235 L2_CA53: cache-controller-1 { 236 compatible = "cache"; 237 power-domains = <&sysc R8A77961_PD_CA53_SCU>; 238 cache-unified; 239 cache-level = <2>; 240 }; 241 242 idle-states { 243 entry-method = "psci"; 244 245 CPU_SLEEP_0: cpu-sleep-0 { 246 compatible = "arm,idle-state"; 247 arm,psci-suspend-param = <0x0010000>; 248 local-timer-stop; 249 entry-latency-us = <400>; 250 exit-latency-us = <500>; 251 min-residency-us = <4000>; 252 }; 253 254 CPU_SLEEP_1: cpu-sleep-1 { 255 compatible = "arm,idle-state"; 256 arm,psci-suspend-param = <0x0010000>; 257 local-timer-stop; 258 entry-latency-us = <700>; 259 exit-latency-us = <700>; 260 min-residency-us = <5000>; 261 }; 262 }; 263 }; 264 265 extal_clk: extal { 266 compatible = "fixed-clock"; 267 #clock-cells = <0>; 268 /* This value must be overridden by the board */ 269 clock-frequency = <0>; 270 }; 271 272 extalr_clk: extalr { 273 compatible = "fixed-clock"; 274 #clock-cells = <0>; 275 /* This value must be overridden by the board */ 276 clock-frequency = <0>; 277 }; 278 279 /* External PCIe clock - can be overridden by the board */ 280 pcie_bus_clk: pcie_bus { 281 compatible = "fixed-clock"; 282 #clock-cells = <0>; 283 clock-frequency = <0>; 284 }; 285 286 pmu_a53 { 287 compatible = "arm,cortex-a53-pmu"; 288 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 289 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 290 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 291 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 292 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 293 }; 294 295 pmu_a57 { 296 compatible = "arm,cortex-a57-pmu"; 297 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 298 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 299 interrupt-affinity = <&a57_0>, <&a57_1>; 300 }; 301 302 psci { 303 compatible = "arm,psci-1.0", "arm,psci-0.2"; 304 method = "smc"; 305 }; 306 307 /* External SCIF clock - to be overridden by boards that provide it */ 308 scif_clk: scif { 309 compatible = "fixed-clock"; 310 #clock-cells = <0>; 311 clock-frequency = <0>; 312 }; 313 314 soc { 315 compatible = "simple-bus"; 316 interrupt-parent = <&gic>; 317 #address-cells = <2>; 318 #size-cells = <2>; 319 ranges; 320 321 rwdt: watchdog@e6020000 { 322 compatible = "renesas,r8a77961-wdt", 323 "renesas,rcar-gen3-wdt"; 324 reg = <0 0xe6020000 0 0x0c>; 325 clocks = <&cpg CPG_MOD 402>; 326 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 327 resets = <&cpg 402>; 328 status = "disabled"; 329 }; 330 331 gpio0: gpio@e6050000 { 332 compatible = "renesas,gpio-r8a77961", 333 "renesas,rcar-gen3-gpio"; 334 reg = <0 0xe6050000 0 0x50>; 335 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 336 #gpio-cells = <2>; 337 gpio-controller; 338 gpio-ranges = <&pfc 0 0 16>; 339 #interrupt-cells = <2>; 340 interrupt-controller; 341 clocks = <&cpg CPG_MOD 912>; 342 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 343 resets = <&cpg 912>; 344 }; 345 346 gpio1: gpio@e6051000 { 347 compatible = "renesas,gpio-r8a77961", 348 "renesas,rcar-gen3-gpio"; 349 reg = <0 0xe6051000 0 0x50>; 350 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 351 #gpio-cells = <2>; 352 gpio-controller; 353 gpio-ranges = <&pfc 0 32 29>; 354 #interrupt-cells = <2>; 355 interrupt-controller; 356 clocks = <&cpg CPG_MOD 911>; 357 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 358 resets = <&cpg 911>; 359 }; 360 361 gpio2: gpio@e6052000 { 362 compatible = "renesas,gpio-r8a77961", 363 "renesas,rcar-gen3-gpio"; 364 reg = <0 0xe6052000 0 0x50>; 365 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 366 #gpio-cells = <2>; 367 gpio-controller; 368 gpio-ranges = <&pfc 0 64 15>; 369 #interrupt-cells = <2>; 370 interrupt-controller; 371 clocks = <&cpg CPG_MOD 910>; 372 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 373 resets = <&cpg 910>; 374 }; 375 376 gpio3: gpio@e6053000 { 377 compatible = "renesas,gpio-r8a77961", 378 "renesas,rcar-gen3-gpio"; 379 reg = <0 0xe6053000 0 0x50>; 380 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 381 #gpio-cells = <2>; 382 gpio-controller; 383 gpio-ranges = <&pfc 0 96 16>; 384 #interrupt-cells = <2>; 385 interrupt-controller; 386 clocks = <&cpg CPG_MOD 909>; 387 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 388 resets = <&cpg 909>; 389 }; 390 391 gpio4: gpio@e6054000 { 392 compatible = "renesas,gpio-r8a77961", 393 "renesas,rcar-gen3-gpio"; 394 reg = <0 0xe6054000 0 0x50>; 395 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 396 #gpio-cells = <2>; 397 gpio-controller; 398 gpio-ranges = <&pfc 0 128 18>; 399 #interrupt-cells = <2>; 400 interrupt-controller; 401 clocks = <&cpg CPG_MOD 908>; 402 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 403 resets = <&cpg 908>; 404 }; 405 406 gpio5: gpio@e6055000 { 407 compatible = "renesas,gpio-r8a77961", 408 "renesas,rcar-gen3-gpio"; 409 reg = <0 0xe6055000 0 0x50>; 410 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 411 #gpio-cells = <2>; 412 gpio-controller; 413 gpio-ranges = <&pfc 0 160 26>; 414 #interrupt-cells = <2>; 415 interrupt-controller; 416 clocks = <&cpg CPG_MOD 907>; 417 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 418 resets = <&cpg 907>; 419 }; 420 421 gpio6: gpio@e6055400 { 422 compatible = "renesas,gpio-r8a77961", 423 "renesas,rcar-gen3-gpio"; 424 reg = <0 0xe6055400 0 0x50>; 425 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 426 #gpio-cells = <2>; 427 gpio-controller; 428 gpio-ranges = <&pfc 0 192 32>; 429 #interrupt-cells = <2>; 430 interrupt-controller; 431 clocks = <&cpg CPG_MOD 906>; 432 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 433 resets = <&cpg 906>; 434 }; 435 436 gpio7: gpio@e6055800 { 437 compatible = "renesas,gpio-r8a77961", 438 "renesas,rcar-gen3-gpio"; 439 reg = <0 0xe6055800 0 0x50>; 440 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 441 #gpio-cells = <2>; 442 gpio-controller; 443 gpio-ranges = <&pfc 0 224 4>; 444 #interrupt-cells = <2>; 445 interrupt-controller; 446 clocks = <&cpg CPG_MOD 905>; 447 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 448 resets = <&cpg 905>; 449 }; 450 451 pfc: pinctrl@e6060000 { 452 compatible = "renesas,pfc-r8a77961"; 453 reg = <0 0xe6060000 0 0x50c>; 454 }; 455 456 cmt0: timer@e60f0000 { 457 compatible = "renesas,r8a77961-cmt0", 458 "renesas,rcar-gen3-cmt0"; 459 reg = <0 0xe60f0000 0 0x1004>; 460 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&cpg CPG_MOD 303>; 463 clock-names = "fck"; 464 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 465 resets = <&cpg 303>; 466 status = "disabled"; 467 }; 468 469 cmt1: timer@e6130000 { 470 compatible = "renesas,r8a77961-cmt1", 471 "renesas,rcar-gen3-cmt1"; 472 reg = <0 0xe6130000 0 0x1004>; 473 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&cpg CPG_MOD 302>; 482 clock-names = "fck"; 483 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 484 resets = <&cpg 302>; 485 status = "disabled"; 486 }; 487 488 cmt2: timer@e6140000 { 489 compatible = "renesas,r8a77961-cmt1", 490 "renesas,rcar-gen3-cmt1"; 491 reg = <0 0xe6140000 0 0x1004>; 492 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&cpg CPG_MOD 301>; 501 clock-names = "fck"; 502 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 503 resets = <&cpg 301>; 504 status = "disabled"; 505 }; 506 507 cmt3: timer@e6148000 { 508 compatible = "renesas,r8a77961-cmt1", 509 "renesas,rcar-gen3-cmt1"; 510 reg = <0 0xe6148000 0 0x1004>; 511 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&cpg CPG_MOD 300>; 520 clock-names = "fck"; 521 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 522 resets = <&cpg 300>; 523 status = "disabled"; 524 }; 525 526 cpg: clock-controller@e6150000 { 527 compatible = "renesas,r8a77961-cpg-mssr"; 528 reg = <0 0xe6150000 0 0x1000>; 529 clocks = <&extal_clk>, <&extalr_clk>; 530 clock-names = "extal", "extalr"; 531 #clock-cells = <2>; 532 #power-domain-cells = <0>; 533 #reset-cells = <1>; 534 }; 535 536 rst: reset-controller@e6160000 { 537 compatible = "renesas,r8a77961-rst"; 538 reg = <0 0xe6160000 0 0x0200>; 539 }; 540 541 sysc: system-controller@e6180000 { 542 compatible = "renesas,r8a77961-sysc"; 543 reg = <0 0xe6180000 0 0x0400>; 544 #power-domain-cells = <1>; 545 }; 546 547 tsc: thermal@e6198000 { 548 compatible = "renesas,r8a77961-thermal"; 549 reg = <0 0xe6198000 0 0x100>, 550 <0 0xe61a0000 0 0x100>, 551 <0 0xe61a8000 0 0x100>; 552 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&cpg CPG_MOD 522>; 556 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 557 resets = <&cpg 522>; 558 #thermal-sensor-cells = <1>; 559 }; 560 561 intc_ex: interrupt-controller@e61c0000 { 562 #interrupt-cells = <2>; 563 interrupt-controller; 564 reg = <0 0xe61c0000 0 0x200>; 565 /* placeholder */ 566 }; 567 568 tmu0: timer@e61e0000 { 569 compatible = "renesas,tmu-r8a77961", "renesas,tmu"; 570 reg = <0 0xe61e0000 0 0x30>; 571 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&cpg CPG_MOD 125>; 575 clock-names = "fck"; 576 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 577 resets = <&cpg 125>; 578 status = "disabled"; 579 }; 580 581 tmu1: timer@e6fc0000 { 582 compatible = "renesas,tmu-r8a77961", "renesas,tmu"; 583 reg = <0 0xe6fc0000 0 0x30>; 584 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&cpg CPG_MOD 124>; 588 clock-names = "fck"; 589 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 590 resets = <&cpg 124>; 591 status = "disabled"; 592 }; 593 594 tmu2: timer@e6fd0000 { 595 compatible = "renesas,tmu-r8a77961", "renesas,tmu"; 596 reg = <0 0xe6fd0000 0 0x30>; 597 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 600 clocks = <&cpg CPG_MOD 123>; 601 clock-names = "fck"; 602 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 603 resets = <&cpg 123>; 604 status = "disabled"; 605 }; 606 607 tmu3: timer@e6fe0000 { 608 compatible = "renesas,tmu-r8a77961", "renesas,tmu"; 609 reg = <0 0xe6fe0000 0 0x30>; 610 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&cpg CPG_MOD 122>; 614 clock-names = "fck"; 615 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 616 resets = <&cpg 122>; 617 status = "disabled"; 618 }; 619 620 tmu4: timer@ffc00000 { 621 compatible = "renesas,tmu-r8a77961", "renesas,tmu"; 622 reg = <0 0xffc00000 0 0x30>; 623 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&cpg CPG_MOD 121>; 627 clock-names = "fck"; 628 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 629 resets = <&cpg 121>; 630 status = "disabled"; 631 }; 632 633 i2c0: i2c@e6500000 { 634 #address-cells = <1>; 635 #size-cells = <0>; 636 compatible = "renesas,i2c-r8a77961", 637 "renesas,rcar-gen3-i2c"; 638 reg = <0 0xe6500000 0 0x40>; 639 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&cpg CPG_MOD 931>; 641 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 642 resets = <&cpg 931>; 643 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 644 <&dmac2 0x91>, <&dmac2 0x90>; 645 dma-names = "tx", "rx", "tx", "rx"; 646 i2c-scl-internal-delay-ns = <110>; 647 status = "disabled"; 648 }; 649 650 i2c1: i2c@e6508000 { 651 #address-cells = <1>; 652 #size-cells = <0>; 653 compatible = "renesas,i2c-r8a77961", 654 "renesas,rcar-gen3-i2c"; 655 reg = <0 0xe6508000 0 0x40>; 656 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 657 clocks = <&cpg CPG_MOD 930>; 658 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 659 resets = <&cpg 930>; 660 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 661 <&dmac2 0x93>, <&dmac2 0x92>; 662 dma-names = "tx", "rx", "tx", "rx"; 663 i2c-scl-internal-delay-ns = <6>; 664 status = "disabled"; 665 }; 666 667 i2c2: i2c@e6510000 { 668 #address-cells = <1>; 669 #size-cells = <0>; 670 compatible = "renesas,i2c-r8a77961", 671 "renesas,rcar-gen3-i2c"; 672 reg = <0 0xe6510000 0 0x40>; 673 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 674 clocks = <&cpg CPG_MOD 929>; 675 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 676 resets = <&cpg 929>; 677 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 678 <&dmac2 0x95>, <&dmac2 0x94>; 679 dma-names = "tx", "rx", "tx", "rx"; 680 i2c-scl-internal-delay-ns = <6>; 681 status = "disabled"; 682 }; 683 684 i2c3: i2c@e66d0000 { 685 #address-cells = <1>; 686 #size-cells = <0>; 687 compatible = "renesas,i2c-r8a77961", 688 "renesas,rcar-gen3-i2c"; 689 reg = <0 0xe66d0000 0 0x40>; 690 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 691 clocks = <&cpg CPG_MOD 928>; 692 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 693 resets = <&cpg 928>; 694 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 695 dma-names = "tx", "rx"; 696 i2c-scl-internal-delay-ns = <110>; 697 status = "disabled"; 698 }; 699 700 i2c4: i2c@e66d8000 { 701 #address-cells = <1>; 702 #size-cells = <0>; 703 compatible = "renesas,i2c-r8a77961", 704 "renesas,rcar-gen3-i2c"; 705 reg = <0 0xe66d8000 0 0x40>; 706 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&cpg CPG_MOD 927>; 708 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 709 resets = <&cpg 927>; 710 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 711 dma-names = "tx", "rx"; 712 i2c-scl-internal-delay-ns = <110>; 713 status = "disabled"; 714 }; 715 716 i2c5: i2c@e66e0000 { 717 #address-cells = <1>; 718 #size-cells = <0>; 719 compatible = "renesas,i2c-r8a77961", 720 "renesas,rcar-gen3-i2c"; 721 reg = <0 0xe66e0000 0 0x40>; 722 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&cpg CPG_MOD 919>; 724 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 725 resets = <&cpg 919>; 726 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 727 dma-names = "tx", "rx"; 728 i2c-scl-internal-delay-ns = <110>; 729 status = "disabled"; 730 }; 731 732 i2c6: i2c@e66e8000 { 733 #address-cells = <1>; 734 #size-cells = <0>; 735 compatible = "renesas,i2c-r8a77961", 736 "renesas,rcar-gen3-i2c"; 737 reg = <0 0xe66e8000 0 0x40>; 738 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&cpg CPG_MOD 918>; 740 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 741 resets = <&cpg 918>; 742 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 743 dma-names = "tx", "rx"; 744 i2c-scl-internal-delay-ns = <6>; 745 status = "disabled"; 746 }; 747 748 i2c_dvfs: i2c@e60b0000 { 749 #address-cells = <1>; 750 #size-cells = <0>; 751 compatible = "renesas,iic-r8a77961", 752 "renesas,rcar-gen3-iic", 753 "renesas,rmobile-iic"; 754 reg = <0 0xe60b0000 0 0x425>; 755 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&cpg CPG_MOD 926>; 757 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 758 resets = <&cpg 926>; 759 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 760 dma-names = "tx", "rx"; 761 status = "disabled"; 762 }; 763 764 hscif0: serial@e6540000 { 765 compatible = "renesas,hscif-r8a77961", 766 "renesas,rcar-gen3-hscif", 767 "renesas,hscif"; 768 reg = <0 0xe6540000 0 0x60>; 769 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 770 clocks = <&cpg CPG_MOD 520>, 771 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 772 <&scif_clk>; 773 clock-names = "fck", "brg_int", "scif_clk"; 774 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 775 <&dmac2 0x31>, <&dmac2 0x30>; 776 dma-names = "tx", "rx", "tx", "rx"; 777 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 778 resets = <&cpg 520>; 779 status = "disabled"; 780 }; 781 782 hscif1: serial@e6550000 { 783 compatible = "renesas,hscif-r8a77961", 784 "renesas,rcar-gen3-hscif", 785 "renesas,hscif"; 786 reg = <0 0xe6550000 0 0x60>; 787 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&cpg CPG_MOD 519>, 789 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 790 <&scif_clk>; 791 clock-names = "fck", "brg_int", "scif_clk"; 792 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 793 <&dmac2 0x33>, <&dmac2 0x32>; 794 dma-names = "tx", "rx", "tx", "rx"; 795 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 796 resets = <&cpg 519>; 797 status = "disabled"; 798 }; 799 800 hscif2: serial@e6560000 { 801 compatible = "renesas,hscif-r8a77961", 802 "renesas,rcar-gen3-hscif", 803 "renesas,hscif"; 804 reg = <0 0xe6560000 0 0x60>; 805 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 806 clocks = <&cpg CPG_MOD 518>, 807 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 808 <&scif_clk>; 809 clock-names = "fck", "brg_int", "scif_clk"; 810 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 811 <&dmac2 0x35>, <&dmac2 0x34>; 812 dma-names = "tx", "rx", "tx", "rx"; 813 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 814 resets = <&cpg 518>; 815 status = "disabled"; 816 }; 817 818 hscif3: serial@e66a0000 { 819 compatible = "renesas,hscif-r8a77961", 820 "renesas,rcar-gen3-hscif", 821 "renesas,hscif"; 822 reg = <0 0xe66a0000 0 0x60>; 823 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&cpg CPG_MOD 517>, 825 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 826 <&scif_clk>; 827 clock-names = "fck", "brg_int", "scif_clk"; 828 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 829 dma-names = "tx", "rx"; 830 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 831 resets = <&cpg 517>; 832 status = "disabled"; 833 }; 834 835 hscif4: serial@e66b0000 { 836 compatible = "renesas,hscif-r8a77961", 837 "renesas,rcar-gen3-hscif", 838 "renesas,hscif"; 839 reg = <0 0xe66b0000 0 0x60>; 840 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 841 clocks = <&cpg CPG_MOD 516>, 842 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 843 <&scif_clk>; 844 clock-names = "fck", "brg_int", "scif_clk"; 845 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 846 dma-names = "tx", "rx"; 847 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 848 resets = <&cpg 516>; 849 status = "disabled"; 850 }; 851 852 hsusb: usb@e6590000 { 853 compatible = "renesas,usbhs-r8a77961", 854 "renesas,rcar-gen3-usbhs"; 855 reg = <0 0xe6590000 0 0x200>; 856 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 857 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 858 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 859 <&usb_dmac1 0>, <&usb_dmac1 1>; 860 dma-names = "ch0", "ch1", "ch2", "ch3"; 861 renesas,buswait = <11>; 862 phys = <&usb2_phy0 3>; 863 phy-names = "usb"; 864 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 865 resets = <&cpg 704>, <&cpg 703>; 866 status = "disabled"; 867 }; 868 869 usb_dmac0: dma-controller@e65a0000 { 870 compatible = "renesas,r8a77961-usb-dmac", 871 "renesas,usb-dmac"; 872 reg = <0 0xe65a0000 0 0x100>; 873 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 875 interrupt-names = "ch0", "ch1"; 876 clocks = <&cpg CPG_MOD 330>; 877 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 878 resets = <&cpg 330>; 879 #dma-cells = <1>; 880 dma-channels = <2>; 881 }; 882 883 usb_dmac1: dma-controller@e65b0000 { 884 compatible = "renesas,r8a77961-usb-dmac", 885 "renesas,usb-dmac"; 886 reg = <0 0xe65b0000 0 0x100>; 887 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 889 interrupt-names = "ch0", "ch1"; 890 clocks = <&cpg CPG_MOD 331>; 891 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 892 resets = <&cpg 331>; 893 #dma-cells = <1>; 894 dma-channels = <2>; 895 }; 896 897 usb3_phy0: usb-phy@e65ee000 { 898 compatible = "renesas,r8a77961-usb3-phy", 899 "renesas,rcar-gen3-usb3-phy"; 900 reg = <0 0xe65ee000 0 0x90>; 901 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 902 <&usb_extal_clk>; 903 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 904 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 905 resets = <&cpg 328>; 906 #phy-cells = <0>; 907 status = "disabled"; 908 }; 909 910 arm_cc630p: crypto@e6601000 { 911 compatible = "arm,cryptocell-630p-ree"; 912 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 913 reg = <0x0 0xe6601000 0 0x1000>; 914 clocks = <&cpg CPG_MOD 229>; 915 resets = <&cpg 229>; 916 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 917 }; 918 919 dmac0: dma-controller@e6700000 { 920 compatible = "renesas,dmac-r8a77961", 921 "renesas,rcar-dmac"; 922 reg = <0 0xe6700000 0 0x10000>; 923 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 940 interrupt-names = "error", 941 "ch0", "ch1", "ch2", "ch3", 942 "ch4", "ch5", "ch6", "ch7", 943 "ch8", "ch9", "ch10", "ch11", 944 "ch12", "ch13", "ch14", "ch15"; 945 clocks = <&cpg CPG_MOD 219>; 946 clock-names = "fck"; 947 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 948 resets = <&cpg 219>; 949 #dma-cells = <1>; 950 dma-channels = <16>; 951 }; 952 953 dmac1: dma-controller@e7300000 { 954 compatible = "renesas,dmac-r8a77961", 955 "renesas,rcar-dmac"; 956 reg = <0 0xe7300000 0 0x10000>; 957 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 974 interrupt-names = "error", 975 "ch0", "ch1", "ch2", "ch3", 976 "ch4", "ch5", "ch6", "ch7", 977 "ch8", "ch9", "ch10", "ch11", 978 "ch12", "ch13", "ch14", "ch15"; 979 clocks = <&cpg CPG_MOD 218>; 980 clock-names = "fck"; 981 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 982 resets = <&cpg 218>; 983 #dma-cells = <1>; 984 dma-channels = <16>; 985 }; 986 987 dmac2: dma-controller@e7310000 { 988 compatible = "renesas,dmac-r8a77961", 989 "renesas,rcar-dmac"; 990 reg = <0 0xe7310000 0 0x10000>; 991 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 1001 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 1002 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 1003 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 1004 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 1005 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 1006 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 1007 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 1008 interrupt-names = "error", 1009 "ch0", "ch1", "ch2", "ch3", 1010 "ch4", "ch5", "ch6", "ch7", 1011 "ch8", "ch9", "ch10", "ch11", 1012 "ch12", "ch13", "ch14", "ch15"; 1013 clocks = <&cpg CPG_MOD 217>; 1014 clock-names = "fck"; 1015 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1016 resets = <&cpg 217>; 1017 #dma-cells = <1>; 1018 dma-channels = <16>; 1019 }; 1020 1021 ipmmu_ds0: iommu@e6740000 { 1022 compatible = "renesas,ipmmu-r8a77961"; 1023 reg = <0 0xe6740000 0 0x1000>; 1024 renesas,ipmmu-main = <&ipmmu_mm 0>; 1025 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1026 #iommu-cells = <1>; 1027 }; 1028 1029 ipmmu_ds1: iommu@e7740000 { 1030 compatible = "renesas,ipmmu-r8a77961"; 1031 reg = <0 0xe7740000 0 0x1000>; 1032 renesas,ipmmu-main = <&ipmmu_mm 1>; 1033 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1034 #iommu-cells = <1>; 1035 }; 1036 1037 ipmmu_hc: iommu@e6570000 { 1038 compatible = "renesas,ipmmu-r8a77961"; 1039 reg = <0 0xe6570000 0 0x1000>; 1040 renesas,ipmmu-main = <&ipmmu_mm 2>; 1041 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1042 #iommu-cells = <1>; 1043 }; 1044 1045 ipmmu_ir: iommu@ff8b0000 { 1046 compatible = "renesas,ipmmu-r8a77961"; 1047 reg = <0 0xff8b0000 0 0x1000>; 1048 renesas,ipmmu-main = <&ipmmu_mm 3>; 1049 power-domains = <&sysc R8A77961_PD_A3IR>; 1050 #iommu-cells = <1>; 1051 }; 1052 1053 ipmmu_mm: iommu@e67b0000 { 1054 compatible = "renesas,ipmmu-r8a77961"; 1055 reg = <0 0xe67b0000 0 0x1000>; 1056 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1058 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1059 #iommu-cells = <1>; 1060 }; 1061 1062 ipmmu_mp: iommu@ec670000 { 1063 compatible = "renesas,ipmmu-r8a77961"; 1064 reg = <0 0xec670000 0 0x1000>; 1065 renesas,ipmmu-main = <&ipmmu_mm 4>; 1066 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1067 #iommu-cells = <1>; 1068 }; 1069 1070 ipmmu_pv0: iommu@fd800000 { 1071 compatible = "renesas,ipmmu-r8a77961"; 1072 reg = <0 0xfd800000 0 0x1000>; 1073 renesas,ipmmu-main = <&ipmmu_mm 5>; 1074 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1075 #iommu-cells = <1>; 1076 }; 1077 1078 ipmmu_pv1: iommu@fd950000 { 1079 compatible = "renesas,ipmmu-r8a77961"; 1080 reg = <0 0xfd950000 0 0x1000>; 1081 renesas,ipmmu-main = <&ipmmu_mm 6>; 1082 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1083 #iommu-cells = <1>; 1084 }; 1085 1086 ipmmu_rt: iommu@ffc80000 { 1087 compatible = "renesas,ipmmu-r8a77961"; 1088 reg = <0 0xffc80000 0 0x1000>; 1089 renesas,ipmmu-main = <&ipmmu_mm 7>; 1090 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1091 #iommu-cells = <1>; 1092 }; 1093 1094 ipmmu_vc0: iommu@fe6b0000 { 1095 compatible = "renesas,ipmmu-r8a77961"; 1096 reg = <0 0xfe6b0000 0 0x1000>; 1097 renesas,ipmmu-main = <&ipmmu_mm 8>; 1098 power-domains = <&sysc R8A77961_PD_A3VC>; 1099 #iommu-cells = <1>; 1100 }; 1101 1102 ipmmu_vi0: iommu@febd0000 { 1103 compatible = "renesas,ipmmu-r8a77961"; 1104 reg = <0 0xfebd0000 0 0x1000>; 1105 renesas,ipmmu-main = <&ipmmu_mm 9>; 1106 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1107 #iommu-cells = <1>; 1108 }; 1109 1110 avb: ethernet@e6800000 { 1111 compatible = "renesas,etheravb-r8a77961", 1112 "renesas,etheravb-rcar-gen3"; 1113 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 1114 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1139 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1140 "ch4", "ch5", "ch6", "ch7", 1141 "ch8", "ch9", "ch10", "ch11", 1142 "ch12", "ch13", "ch14", "ch15", 1143 "ch16", "ch17", "ch18", "ch19", 1144 "ch20", "ch21", "ch22", "ch23", 1145 "ch24"; 1146 clocks = <&cpg CPG_MOD 812>; 1147 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1148 resets = <&cpg 812>; 1149 phy-mode = "rgmii"; 1150 rx-internal-delay-ps = <0>; 1151 tx-internal-delay-ps = <0>; 1152 #address-cells = <1>; 1153 #size-cells = <0>; 1154 status = "disabled"; 1155 }; 1156 1157 can0: can@e6c30000 { 1158 reg = <0 0xe6c30000 0 0x1000>; 1159 /* placeholder */ 1160 }; 1161 1162 can1: can@e6c38000 { 1163 reg = <0 0xe6c38000 0 0x1000>; 1164 /* placeholder */ 1165 }; 1166 1167 pwm0: pwm@e6e30000 { 1168 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1169 reg = <0 0xe6e30000 0 8>; 1170 #pwm-cells = <2>; 1171 clocks = <&cpg CPG_MOD 523>; 1172 resets = <&cpg 523>; 1173 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1174 status = "disabled"; 1175 }; 1176 1177 pwm1: pwm@e6e31000 { 1178 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1179 reg = <0 0xe6e31000 0 8>; 1180 #pwm-cells = <2>; 1181 clocks = <&cpg CPG_MOD 523>; 1182 resets = <&cpg 523>; 1183 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1184 status = "disabled"; 1185 }; 1186 1187 pwm2: pwm@e6e32000 { 1188 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1189 reg = <0 0xe6e32000 0 8>; 1190 #pwm-cells = <2>; 1191 clocks = <&cpg CPG_MOD 523>; 1192 resets = <&cpg 523>; 1193 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1194 status = "disabled"; 1195 }; 1196 1197 pwm3: pwm@e6e33000 { 1198 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1199 reg = <0 0xe6e33000 0 8>; 1200 #pwm-cells = <2>; 1201 clocks = <&cpg CPG_MOD 523>; 1202 resets = <&cpg 523>; 1203 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1204 status = "disabled"; 1205 }; 1206 1207 pwm4: pwm@e6e34000 { 1208 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1209 reg = <0 0xe6e34000 0 8>; 1210 #pwm-cells = <2>; 1211 clocks = <&cpg CPG_MOD 523>; 1212 resets = <&cpg 523>; 1213 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1214 status = "disabled"; 1215 }; 1216 1217 pwm5: pwm@e6e35000 { 1218 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1219 reg = <0 0xe6e35000 0 8>; 1220 #pwm-cells = <2>; 1221 clocks = <&cpg CPG_MOD 523>; 1222 resets = <&cpg 523>; 1223 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1224 status = "disabled"; 1225 }; 1226 1227 pwm6: pwm@e6e36000 { 1228 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1229 reg = <0 0xe6e36000 0 8>; 1230 #pwm-cells = <2>; 1231 clocks = <&cpg CPG_MOD 523>; 1232 resets = <&cpg 523>; 1233 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1234 status = "disabled"; 1235 }; 1236 1237 scif0: serial@e6e60000 { 1238 compatible = "renesas,scif-r8a77961", 1239 "renesas,rcar-gen3-scif", "renesas,scif"; 1240 reg = <0 0xe6e60000 0 64>; 1241 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1242 clocks = <&cpg CPG_MOD 207>, 1243 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1244 <&scif_clk>; 1245 clock-names = "fck", "brg_int", "scif_clk"; 1246 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1247 <&dmac2 0x51>, <&dmac2 0x50>; 1248 dma-names = "tx", "rx", "tx", "rx"; 1249 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1250 resets = <&cpg 207>; 1251 status = "disabled"; 1252 }; 1253 1254 scif1: serial@e6e68000 { 1255 compatible = "renesas,scif-r8a77961", 1256 "renesas,rcar-gen3-scif", "renesas,scif"; 1257 reg = <0 0xe6e68000 0 64>; 1258 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1259 clocks = <&cpg CPG_MOD 206>, 1260 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1261 <&scif_clk>; 1262 clock-names = "fck", "brg_int", "scif_clk"; 1263 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1264 <&dmac2 0x53>, <&dmac2 0x52>; 1265 dma-names = "tx", "rx", "tx", "rx"; 1266 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1267 resets = <&cpg 206>; 1268 status = "disabled"; 1269 }; 1270 1271 scif2: serial@e6e88000 { 1272 compatible = "renesas,scif-r8a77961", 1273 "renesas,rcar-gen3-scif", "renesas,scif"; 1274 reg = <0 0xe6e88000 0 64>; 1275 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1276 clocks = <&cpg CPG_MOD 310>, 1277 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1278 <&scif_clk>; 1279 clock-names = "fck", "brg_int", "scif_clk"; 1280 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1281 <&dmac2 0x13>, <&dmac2 0x12>; 1282 dma-names = "tx", "rx", "tx", "rx"; 1283 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1284 resets = <&cpg 310>; 1285 status = "disabled"; 1286 }; 1287 1288 scif3: serial@e6c50000 { 1289 compatible = "renesas,scif-r8a77961", 1290 "renesas,rcar-gen3-scif", "renesas,scif"; 1291 reg = <0 0xe6c50000 0 64>; 1292 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1293 clocks = <&cpg CPG_MOD 204>, 1294 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1295 <&scif_clk>; 1296 clock-names = "fck", "brg_int", "scif_clk"; 1297 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1298 dma-names = "tx", "rx"; 1299 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1300 resets = <&cpg 204>; 1301 status = "disabled"; 1302 }; 1303 1304 scif4: serial@e6c40000 { 1305 compatible = "renesas,scif-r8a77961", 1306 "renesas,rcar-gen3-scif", "renesas,scif"; 1307 reg = <0 0xe6c40000 0 64>; 1308 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1309 clocks = <&cpg CPG_MOD 203>, 1310 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1311 <&scif_clk>; 1312 clock-names = "fck", "brg_int", "scif_clk"; 1313 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1314 dma-names = "tx", "rx"; 1315 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1316 resets = <&cpg 203>; 1317 status = "disabled"; 1318 }; 1319 1320 scif5: serial@e6f30000 { 1321 compatible = "renesas,scif-r8a77961", 1322 "renesas,rcar-gen3-scif", "renesas,scif"; 1323 reg = <0 0xe6f30000 0 64>; 1324 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1325 clocks = <&cpg CPG_MOD 202>, 1326 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1327 <&scif_clk>; 1328 clock-names = "fck", "brg_int", "scif_clk"; 1329 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1330 <&dmac2 0x5b>, <&dmac2 0x5a>; 1331 dma-names = "tx", "rx", "tx", "rx"; 1332 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1333 resets = <&cpg 202>; 1334 status = "disabled"; 1335 }; 1336 1337 msiof0: spi@e6e90000 { 1338 compatible = "renesas,msiof-r8a77961", 1339 "renesas,rcar-gen3-msiof"; 1340 reg = <0 0xe6e90000 0 0x0064>; 1341 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1342 clocks = <&cpg CPG_MOD 211>; 1343 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1344 <&dmac2 0x41>, <&dmac2 0x40>; 1345 dma-names = "tx", "rx", "tx", "rx"; 1346 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1347 resets = <&cpg 211>; 1348 #address-cells = <1>; 1349 #size-cells = <0>; 1350 status = "disabled"; 1351 }; 1352 1353 msiof1: spi@e6ea0000 { 1354 compatible = "renesas,msiof-r8a77961", 1355 "renesas,rcar-gen3-msiof"; 1356 reg = <0 0xe6ea0000 0 0x0064>; 1357 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1358 clocks = <&cpg CPG_MOD 210>; 1359 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1360 <&dmac2 0x43>, <&dmac2 0x42>; 1361 dma-names = "tx", "rx", "tx", "rx"; 1362 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1363 resets = <&cpg 210>; 1364 #address-cells = <1>; 1365 #size-cells = <0>; 1366 status = "disabled"; 1367 }; 1368 1369 msiof2: spi@e6c00000 { 1370 compatible = "renesas,msiof-r8a77961", 1371 "renesas,rcar-gen3-msiof"; 1372 reg = <0 0xe6c00000 0 0x0064>; 1373 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1374 clocks = <&cpg CPG_MOD 209>; 1375 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1376 dma-names = "tx", "rx"; 1377 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1378 resets = <&cpg 209>; 1379 #address-cells = <1>; 1380 #size-cells = <0>; 1381 status = "disabled"; 1382 }; 1383 1384 msiof3: spi@e6c10000 { 1385 compatible = "renesas,msiof-r8a77961", 1386 "renesas,rcar-gen3-msiof"; 1387 reg = <0 0xe6c10000 0 0x0064>; 1388 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1389 clocks = <&cpg CPG_MOD 208>; 1390 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1391 dma-names = "tx", "rx"; 1392 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1393 resets = <&cpg 208>; 1394 #address-cells = <1>; 1395 #size-cells = <0>; 1396 status = "disabled"; 1397 }; 1398 1399 vin0: video@e6ef0000 { 1400 reg = <0 0xe6ef0000 0 0x1000>; 1401 /* placeholder */ 1402 }; 1403 1404 vin1: video@e6ef1000 { 1405 reg = <0 0xe6ef1000 0 0x1000>; 1406 /* placeholder */ 1407 }; 1408 1409 vin2: video@e6ef2000 { 1410 reg = <0 0xe6ef2000 0 0x1000>; 1411 /* placeholder */ 1412 }; 1413 1414 vin3: video@e6ef3000 { 1415 reg = <0 0xe6ef3000 0 0x1000>; 1416 /* placeholder */ 1417 }; 1418 1419 vin4: video@e6ef4000 { 1420 reg = <0 0xe6ef4000 0 0x1000>; 1421 /* placeholder */ 1422 }; 1423 1424 vin5: video@e6ef5000 { 1425 reg = <0 0xe6ef5000 0 0x1000>; 1426 /* placeholder */ 1427 }; 1428 1429 vin6: video@e6ef6000 { 1430 reg = <0 0xe6ef6000 0 0x1000>; 1431 /* placeholder */ 1432 }; 1433 1434 vin7: video@e6ef7000 { 1435 reg = <0 0xe6ef7000 0 0x1000>; 1436 /* placeholder */ 1437 }; 1438 1439 rcar_sound: sound@ec500000 { 1440 /* 1441 * #sound-dai-cells is required 1442 * 1443 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1444 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1445 */ 1446 /* 1447 * #clock-cells is required for audio_clkout0/1/2/3 1448 * 1449 * clkout : #clock-cells = <0>; <&rcar_sound>; 1450 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1451 */ 1452 compatible = "renesas,rcar_sound-r8a77961", "renesas,rcar_sound-gen3"; 1453 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1454 <0 0xec5a0000 0 0x100>, /* ADG */ 1455 <0 0xec540000 0 0x1000>, /* SSIU */ 1456 <0 0xec541000 0 0x280>, /* SSI */ 1457 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1458 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1459 1460 clocks = <&cpg CPG_MOD 1005>, 1461 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1462 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1463 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1464 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1465 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1466 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1467 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1468 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1469 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1470 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1471 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1472 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1473 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1474 <&audio_clk_a>, <&audio_clk_b>, 1475 <&audio_clk_c>, 1476 <&cpg CPG_CORE R8A77961_CLK_S0D4>; 1477 clock-names = "ssi-all", 1478 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1479 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1480 "ssi.1", "ssi.0", 1481 "src.9", "src.8", "src.7", "src.6", 1482 "src.5", "src.4", "src.3", "src.2", 1483 "src.1", "src.0", 1484 "mix.1", "mix.0", 1485 "ctu.1", "ctu.0", 1486 "dvc.0", "dvc.1", 1487 "clk_a", "clk_b", "clk_c", "clk_i"; 1488 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1489 resets = <&cpg 1005>, 1490 <&cpg 1006>, <&cpg 1007>, 1491 <&cpg 1008>, <&cpg 1009>, 1492 <&cpg 1010>, <&cpg 1011>, 1493 <&cpg 1012>, <&cpg 1013>, 1494 <&cpg 1014>, <&cpg 1015>; 1495 reset-names = "ssi-all", 1496 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1497 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1498 "ssi.1", "ssi.0"; 1499 status = "disabled"; 1500 1501 rcar_sound,ctu { 1502 ctu00: ctu-0 { }; 1503 ctu01: ctu-1 { }; 1504 ctu02: ctu-2 { }; 1505 ctu03: ctu-3 { }; 1506 ctu10: ctu-4 { }; 1507 ctu11: ctu-5 { }; 1508 ctu12: ctu-6 { }; 1509 ctu13: ctu-7 { }; 1510 }; 1511 1512 rcar_sound,dvc { 1513 dvc0: dvc-0 { 1514 dmas = <&audma1 0xbc>; 1515 dma-names = "tx"; 1516 }; 1517 dvc1: dvc-1 { 1518 dmas = <&audma1 0xbe>; 1519 dma-names = "tx"; 1520 }; 1521 }; 1522 1523 rcar_sound,mix { 1524 mix0: mix-0 { }; 1525 mix1: mix-1 { }; 1526 }; 1527 1528 rcar_sound,src { 1529 src0: src-0 { 1530 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1531 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1532 dma-names = "rx", "tx"; 1533 }; 1534 src1: src-1 { 1535 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1536 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1537 dma-names = "rx", "tx"; 1538 }; 1539 src2: src-2 { 1540 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1541 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1542 dma-names = "rx", "tx"; 1543 }; 1544 src3: src-3 { 1545 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1546 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1547 dma-names = "rx", "tx"; 1548 }; 1549 src4: src-4 { 1550 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1551 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1552 dma-names = "rx", "tx"; 1553 }; 1554 src5: src-5 { 1555 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1556 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1557 dma-names = "rx", "tx"; 1558 }; 1559 src6: src-6 { 1560 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1561 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1562 dma-names = "rx", "tx"; 1563 }; 1564 src7: src-7 { 1565 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1566 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1567 dma-names = "rx", "tx"; 1568 }; 1569 src8: src-8 { 1570 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1571 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1572 dma-names = "rx", "tx"; 1573 }; 1574 src9: src-9 { 1575 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1576 dmas = <&audma0 0x97>, <&audma1 0xba>; 1577 dma-names = "rx", "tx"; 1578 }; 1579 }; 1580 1581 rcar_sound,ssi { 1582 ssi0: ssi-0 { 1583 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1584 dmas = <&audma0 0x01>, <&audma1 0x02>; 1585 dma-names = "rx", "tx"; 1586 }; 1587 ssi1: ssi-1 { 1588 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1589 dmas = <&audma0 0x03>, <&audma1 0x04>; 1590 dma-names = "rx", "tx"; 1591 }; 1592 ssi2: ssi-2 { 1593 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1594 dmas = <&audma0 0x05>, <&audma1 0x06>; 1595 dma-names = "rx", "tx"; 1596 }; 1597 ssi3: ssi-3 { 1598 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1599 dmas = <&audma0 0x07>, <&audma1 0x08>; 1600 dma-names = "rx", "tx"; 1601 }; 1602 ssi4: ssi-4 { 1603 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1604 dmas = <&audma0 0x09>, <&audma1 0x0a>; 1605 dma-names = "rx", "tx"; 1606 }; 1607 ssi5: ssi-5 { 1608 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1609 dmas = <&audma0 0x0b>, <&audma1 0x0c>; 1610 dma-names = "rx", "tx"; 1611 }; 1612 ssi6: ssi-6 { 1613 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1614 dmas = <&audma0 0x0d>, <&audma1 0x0e>; 1615 dma-names = "rx", "tx"; 1616 }; 1617 ssi7: ssi-7 { 1618 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1619 dmas = <&audma0 0x0f>, <&audma1 0x10>; 1620 dma-names = "rx", "tx"; 1621 }; 1622 ssi8: ssi-8 { 1623 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1624 dmas = <&audma0 0x11>, <&audma1 0x12>; 1625 dma-names = "rx", "tx"; 1626 }; 1627 ssi9: ssi-9 { 1628 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1629 dmas = <&audma0 0x13>, <&audma1 0x14>; 1630 dma-names = "rx", "tx"; 1631 }; 1632 }; 1633 1634 rcar_sound,ssiu { 1635 ssiu00: ssiu-0 { 1636 dmas = <&audma0 0x15>, <&audma1 0x16>; 1637 dma-names = "rx", "tx"; 1638 }; 1639 ssiu01: ssiu-1 { 1640 dmas = <&audma0 0x35>, <&audma1 0x36>; 1641 dma-names = "rx", "tx"; 1642 }; 1643 ssiu02: ssiu-2 { 1644 dmas = <&audma0 0x37>, <&audma1 0x38>; 1645 dma-names = "rx", "tx"; 1646 }; 1647 ssiu03: ssiu-3 { 1648 dmas = <&audma0 0x47>, <&audma1 0x48>; 1649 dma-names = "rx", "tx"; 1650 }; 1651 ssiu04: ssiu-4 { 1652 dmas = <&audma0 0x3F>, <&audma1 0x40>; 1653 dma-names = "rx", "tx"; 1654 }; 1655 ssiu05: ssiu-5 { 1656 dmas = <&audma0 0x43>, <&audma1 0x44>; 1657 dma-names = "rx", "tx"; 1658 }; 1659 ssiu06: ssiu-6 { 1660 dmas = <&audma0 0x4F>, <&audma1 0x50>; 1661 dma-names = "rx", "tx"; 1662 }; 1663 ssiu07: ssiu-7 { 1664 dmas = <&audma0 0x53>, <&audma1 0x54>; 1665 dma-names = "rx", "tx"; 1666 }; 1667 ssiu10: ssiu-8 { 1668 dmas = <&audma0 0x49>, <&audma1 0x4a>; 1669 dma-names = "rx", "tx"; 1670 }; 1671 ssiu11: ssiu-9 { 1672 dmas = <&audma0 0x4B>, <&audma1 0x4C>; 1673 dma-names = "rx", "tx"; 1674 }; 1675 ssiu12: ssiu-10 { 1676 dmas = <&audma0 0x57>, <&audma1 0x58>; 1677 dma-names = "rx", "tx"; 1678 }; 1679 ssiu13: ssiu-11 { 1680 dmas = <&audma0 0x59>, <&audma1 0x5A>; 1681 dma-names = "rx", "tx"; 1682 }; 1683 ssiu14: ssiu-12 { 1684 dmas = <&audma0 0x5F>, <&audma1 0x60>; 1685 dma-names = "rx", "tx"; 1686 }; 1687 ssiu15: ssiu-13 { 1688 dmas = <&audma0 0xC3>, <&audma1 0xC4>; 1689 dma-names = "rx", "tx"; 1690 }; 1691 ssiu16: ssiu-14 { 1692 dmas = <&audma0 0xC7>, <&audma1 0xC8>; 1693 dma-names = "rx", "tx"; 1694 }; 1695 ssiu17: ssiu-15 { 1696 dmas = <&audma0 0xCB>, <&audma1 0xCC>; 1697 dma-names = "rx", "tx"; 1698 }; 1699 ssiu20: ssiu-16 { 1700 dmas = <&audma0 0x63>, <&audma1 0x64>; 1701 dma-names = "rx", "tx"; 1702 }; 1703 ssiu21: ssiu-17 { 1704 dmas = <&audma0 0x67>, <&audma1 0x68>; 1705 dma-names = "rx", "tx"; 1706 }; 1707 ssiu22: ssiu-18 { 1708 dmas = <&audma0 0x6B>, <&audma1 0x6C>; 1709 dma-names = "rx", "tx"; 1710 }; 1711 ssiu23: ssiu-19 { 1712 dmas = <&audma0 0x6D>, <&audma1 0x6E>; 1713 dma-names = "rx", "tx"; 1714 }; 1715 ssiu24: ssiu-20 { 1716 dmas = <&audma0 0xCF>, <&audma1 0xCE>; 1717 dma-names = "rx", "tx"; 1718 }; 1719 ssiu25: ssiu-21 { 1720 dmas = <&audma0 0xEB>, <&audma1 0xEC>; 1721 dma-names = "rx", "tx"; 1722 }; 1723 ssiu26: ssiu-22 { 1724 dmas = <&audma0 0xED>, <&audma1 0xEE>; 1725 dma-names = "rx", "tx"; 1726 }; 1727 ssiu27: ssiu-23 { 1728 dmas = <&audma0 0xEF>, <&audma1 0xF0>; 1729 dma-names = "rx", "tx"; 1730 }; 1731 ssiu30: ssiu-24 { 1732 dmas = <&audma0 0x6f>, <&audma1 0x70>; 1733 dma-names = "rx", "tx"; 1734 }; 1735 ssiu31: ssiu-25 { 1736 dmas = <&audma0 0x21>, <&audma1 0x22>; 1737 dma-names = "rx", "tx"; 1738 }; 1739 ssiu32: ssiu-26 { 1740 dmas = <&audma0 0x23>, <&audma1 0x24>; 1741 dma-names = "rx", "tx"; 1742 }; 1743 ssiu33: ssiu-27 { 1744 dmas = <&audma0 0x25>, <&audma1 0x26>; 1745 dma-names = "rx", "tx"; 1746 }; 1747 ssiu34: ssiu-28 { 1748 dmas = <&audma0 0x27>, <&audma1 0x28>; 1749 dma-names = "rx", "tx"; 1750 }; 1751 ssiu35: ssiu-29 { 1752 dmas = <&audma0 0x29>, <&audma1 0x2A>; 1753 dma-names = "rx", "tx"; 1754 }; 1755 ssiu36: ssiu-30 { 1756 dmas = <&audma0 0x2B>, <&audma1 0x2C>; 1757 dma-names = "rx", "tx"; 1758 }; 1759 ssiu37: ssiu-31 { 1760 dmas = <&audma0 0x2D>, <&audma1 0x2E>; 1761 dma-names = "rx", "tx"; 1762 }; 1763 ssiu40: ssiu-32 { 1764 dmas = <&audma0 0x71>, <&audma1 0x72>; 1765 dma-names = "rx", "tx"; 1766 }; 1767 ssiu41: ssiu-33 { 1768 dmas = <&audma0 0x17>, <&audma1 0x18>; 1769 dma-names = "rx", "tx"; 1770 }; 1771 ssiu42: ssiu-34 { 1772 dmas = <&audma0 0x19>, <&audma1 0x1A>; 1773 dma-names = "rx", "tx"; 1774 }; 1775 ssiu43: ssiu-35 { 1776 dmas = <&audma0 0x1B>, <&audma1 0x1C>; 1777 dma-names = "rx", "tx"; 1778 }; 1779 ssiu44: ssiu-36 { 1780 dmas = <&audma0 0x1D>, <&audma1 0x1E>; 1781 dma-names = "rx", "tx"; 1782 }; 1783 ssiu45: ssiu-37 { 1784 dmas = <&audma0 0x1F>, <&audma1 0x20>; 1785 dma-names = "rx", "tx"; 1786 }; 1787 ssiu46: ssiu-38 { 1788 dmas = <&audma0 0x31>, <&audma1 0x32>; 1789 dma-names = "rx", "tx"; 1790 }; 1791 ssiu47: ssiu-39 { 1792 dmas = <&audma0 0x33>, <&audma1 0x34>; 1793 dma-names = "rx", "tx"; 1794 }; 1795 ssiu50: ssiu-40 { 1796 dmas = <&audma0 0x73>, <&audma1 0x74>; 1797 dma-names = "rx", "tx"; 1798 }; 1799 ssiu60: ssiu-41 { 1800 dmas = <&audma0 0x75>, <&audma1 0x76>; 1801 dma-names = "rx", "tx"; 1802 }; 1803 ssiu70: ssiu-42 { 1804 dmas = <&audma0 0x79>, <&audma1 0x7a>; 1805 dma-names = "rx", "tx"; 1806 }; 1807 ssiu80: ssiu-43 { 1808 dmas = <&audma0 0x7b>, <&audma1 0x7c>; 1809 dma-names = "rx", "tx"; 1810 }; 1811 ssiu90: ssiu-44 { 1812 dmas = <&audma0 0x7d>, <&audma1 0x7e>; 1813 dma-names = "rx", "tx"; 1814 }; 1815 ssiu91: ssiu-45 { 1816 dmas = <&audma0 0x7F>, <&audma1 0x80>; 1817 dma-names = "rx", "tx"; 1818 }; 1819 ssiu92: ssiu-46 { 1820 dmas = <&audma0 0x81>, <&audma1 0x82>; 1821 dma-names = "rx", "tx"; 1822 }; 1823 ssiu93: ssiu-47 { 1824 dmas = <&audma0 0x83>, <&audma1 0x84>; 1825 dma-names = "rx", "tx"; 1826 }; 1827 ssiu94: ssiu-48 { 1828 dmas = <&audma0 0xA3>, <&audma1 0xA4>; 1829 dma-names = "rx", "tx"; 1830 }; 1831 ssiu95: ssiu-49 { 1832 dmas = <&audma0 0xA5>, <&audma1 0xA6>; 1833 dma-names = "rx", "tx"; 1834 }; 1835 ssiu96: ssiu-50 { 1836 dmas = <&audma0 0xA7>, <&audma1 0xA8>; 1837 dma-names = "rx", "tx"; 1838 }; 1839 ssiu97: ssiu-51 { 1840 dmas = <&audma0 0xA9>, <&audma1 0xAA>; 1841 dma-names = "rx", "tx"; 1842 }; 1843 }; 1844 }; 1845 1846 audma0: dma-controller@ec700000 { 1847 compatible = "renesas,dmac-r8a77961", 1848 "renesas,rcar-dmac"; 1849 reg = <0 0xec700000 0 0x10000>; 1850 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1867 interrupt-names = "error", 1868 "ch0", "ch1", "ch2", "ch3", 1869 "ch4", "ch5", "ch6", "ch7", 1870 "ch8", "ch9", "ch10", "ch11", 1871 "ch12", "ch13", "ch14", "ch15"; 1872 clocks = <&cpg CPG_MOD 502>; 1873 clock-names = "fck"; 1874 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1875 resets = <&cpg 502>; 1876 #dma-cells = <1>; 1877 dma-channels = <16>; 1878 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 1879 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 1880 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 1881 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 1882 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 1883 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 1884 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 1885 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 1886 }; 1887 1888 audma1: dma-controller@ec720000 { 1889 compatible = "renesas,dmac-r8a77961", 1890 "renesas,rcar-dmac"; 1891 reg = <0 0xec720000 0 0x10000>; 1892 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 1893 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1894 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1895 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1896 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1897 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1898 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1899 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1900 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1901 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1902 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1903 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 1904 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1905 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 1906 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1907 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 1908 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 1909 interrupt-names = "error", 1910 "ch0", "ch1", "ch2", "ch3", 1911 "ch4", "ch5", "ch6", "ch7", 1912 "ch8", "ch9", "ch10", "ch11", 1913 "ch12", "ch13", "ch14", "ch15"; 1914 clocks = <&cpg CPG_MOD 501>; 1915 clock-names = "fck"; 1916 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1917 resets = <&cpg 501>; 1918 #dma-cells = <1>; 1919 dma-channels = <16>; 1920 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, 1921 <&ipmmu_mp 18>, <&ipmmu_mp 19>, 1922 <&ipmmu_mp 20>, <&ipmmu_mp 21>, 1923 <&ipmmu_mp 22>, <&ipmmu_mp 23>, 1924 <&ipmmu_mp 24>, <&ipmmu_mp 25>, 1925 <&ipmmu_mp 26>, <&ipmmu_mp 27>, 1926 <&ipmmu_mp 28>, <&ipmmu_mp 29>, 1927 <&ipmmu_mp 30>, <&ipmmu_mp 31>; 1928 }; 1929 1930 xhci0: usb@ee000000 { 1931 compatible = "renesas,xhci-r8a77961", 1932 "renesas,rcar-gen3-xhci"; 1933 reg = <0 0xee000000 0 0xc00>; 1934 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1935 clocks = <&cpg CPG_MOD 328>; 1936 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1937 resets = <&cpg 328>; 1938 status = "disabled"; 1939 }; 1940 1941 usb3_peri0: usb@ee020000 { 1942 compatible = "renesas,r8a77961-usb3-peri", 1943 "renesas,rcar-gen3-usb3-peri"; 1944 reg = <0 0xee020000 0 0x400>; 1945 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1946 clocks = <&cpg CPG_MOD 328>; 1947 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1948 resets = <&cpg 328>; 1949 status = "disabled"; 1950 }; 1951 1952 ohci0: usb@ee080000 { 1953 compatible = "generic-ohci"; 1954 reg = <0 0xee080000 0 0x100>; 1955 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1956 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1957 phys = <&usb2_phy0 1>; 1958 phy-names = "usb"; 1959 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1960 resets = <&cpg 703>, <&cpg 704>; 1961 status = "disabled"; 1962 }; 1963 1964 ohci1: usb@ee0a0000 { 1965 compatible = "generic-ohci"; 1966 reg = <0 0xee0a0000 0 0x100>; 1967 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1968 clocks = <&cpg CPG_MOD 702>; 1969 phys = <&usb2_phy1 1>; 1970 phy-names = "usb"; 1971 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1972 resets = <&cpg 702>; 1973 status = "disabled"; 1974 }; 1975 1976 ehci0: usb@ee080100 { 1977 compatible = "generic-ehci"; 1978 reg = <0 0xee080100 0 0x100>; 1979 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1980 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1981 phys = <&usb2_phy0 2>; 1982 phy-names = "usb"; 1983 companion = <&ohci0>; 1984 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1985 resets = <&cpg 703>, <&cpg 704>; 1986 status = "disabled"; 1987 }; 1988 1989 ehci1: usb@ee0a0100 { 1990 compatible = "generic-ehci"; 1991 reg = <0 0xee0a0100 0 0x100>; 1992 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1993 clocks = <&cpg CPG_MOD 702>; 1994 phys = <&usb2_phy1 2>; 1995 phy-names = "usb"; 1996 companion = <&ohci1>; 1997 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1998 resets = <&cpg 702>; 1999 status = "disabled"; 2000 }; 2001 2002 usb2_phy0: usb-phy@ee080200 { 2003 compatible = "renesas,usb2-phy-r8a77961", 2004 "renesas,rcar-gen3-usb2-phy"; 2005 reg = <0 0xee080200 0 0x700>; 2006 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2007 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2008 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2009 resets = <&cpg 703>, <&cpg 704>; 2010 #phy-cells = <1>; 2011 status = "disabled"; 2012 }; 2013 2014 usb2_phy1: usb-phy@ee0a0200 { 2015 compatible = "renesas,usb2-phy-r8a77961", 2016 "renesas,rcar-gen3-usb2-phy"; 2017 reg = <0 0xee0a0200 0 0x700>; 2018 clocks = <&cpg CPG_MOD 702>; 2019 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2020 resets = <&cpg 702>; 2021 #phy-cells = <1>; 2022 status = "disabled"; 2023 }; 2024 2025 sdhi0: mmc@ee100000 { 2026 compatible = "renesas,sdhi-r8a77961", 2027 "renesas,rcar-gen3-sdhi"; 2028 reg = <0 0xee100000 0 0x2000>; 2029 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 2030 clocks = <&cpg CPG_MOD 314>; 2031 max-frequency = <200000000>; 2032 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2033 resets = <&cpg 314>; 2034 status = "disabled"; 2035 }; 2036 2037 sdhi1: mmc@ee120000 { 2038 compatible = "renesas,sdhi-r8a77961", 2039 "renesas,rcar-gen3-sdhi"; 2040 reg = <0 0xee120000 0 0x2000>; 2041 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 2042 clocks = <&cpg CPG_MOD 313>; 2043 max-frequency = <200000000>; 2044 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2045 resets = <&cpg 313>; 2046 status = "disabled"; 2047 }; 2048 2049 sdhi2: mmc@ee140000 { 2050 compatible = "renesas,sdhi-r8a77961", 2051 "renesas,rcar-gen3-sdhi"; 2052 reg = <0 0xee140000 0 0x2000>; 2053 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 2054 clocks = <&cpg CPG_MOD 312>; 2055 max-frequency = <200000000>; 2056 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2057 resets = <&cpg 312>; 2058 status = "disabled"; 2059 }; 2060 2061 sdhi3: mmc@ee160000 { 2062 compatible = "renesas,sdhi-r8a77961", 2063 "renesas,rcar-gen3-sdhi"; 2064 reg = <0 0xee160000 0 0x2000>; 2065 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 2066 clocks = <&cpg CPG_MOD 311>; 2067 max-frequency = <200000000>; 2068 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2069 resets = <&cpg 311>; 2070 status = "disabled"; 2071 }; 2072 2073 gic: interrupt-controller@f1010000 { 2074 compatible = "arm,gic-400"; 2075 #interrupt-cells = <3>; 2076 #address-cells = <0>; 2077 interrupt-controller; 2078 reg = <0x0 0xf1010000 0 0x1000>, 2079 <0x0 0xf1020000 0 0x20000>, 2080 <0x0 0xf1040000 0 0x20000>, 2081 <0x0 0xf1060000 0 0x20000>; 2082 interrupts = <GIC_PPI 9 2083 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 2084 clocks = <&cpg CPG_MOD 408>; 2085 clock-names = "clk"; 2086 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2087 resets = <&cpg 408>; 2088 }; 2089 2090 pciec0: pcie@fe000000 { 2091 compatible = "renesas,pcie-r8a77961", 2092 "renesas,pcie-rcar-gen3"; 2093 reg = <0 0xfe000000 0 0x80000>; 2094 #address-cells = <3>; 2095 #size-cells = <2>; 2096 bus-range = <0x00 0xff>; 2097 device_type = "pci"; 2098 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 2099 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 2100 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 2101 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 2102 /* Map all possible DDR as inbound ranges */ 2103 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2104 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2107 #interrupt-cells = <1>; 2108 interrupt-map-mask = <0 0 0 0>; 2109 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2110 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 2111 clock-names = "pcie", "pcie_bus"; 2112 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2113 resets = <&cpg 319>; 2114 status = "disabled"; 2115 }; 2116 2117 pciec1: pcie@ee800000 { 2118 compatible = "renesas,pcie-r8a77961", 2119 "renesas,pcie-rcar-gen3"; 2120 reg = <0 0xee800000 0 0x80000>; 2121 #address-cells = <3>; 2122 #size-cells = <2>; 2123 bus-range = <0x00 0xff>; 2124 device_type = "pci"; 2125 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, 2126 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, 2127 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, 2128 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 2129 /* Map all possible DDR as inbound ranges */ 2130 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2131 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2132 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2133 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2134 #interrupt-cells = <1>; 2135 interrupt-map-mask = <0 0 0 0>; 2136 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2137 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 2138 clock-names = "pcie", "pcie_bus"; 2139 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2140 resets = <&cpg 318>; 2141 status = "disabled"; 2142 }; 2143 2144 fcpf0: fcp@fe950000 { 2145 compatible = "renesas,fcpf"; 2146 reg = <0 0xfe950000 0 0x200>; 2147 clocks = <&cpg CPG_MOD 615>; 2148 power-domains = <&sysc R8A77961_PD_A3VC>; 2149 resets = <&cpg 615>; 2150 }; 2151 2152 fcpvb0: fcp@fe96f000 { 2153 compatible = "renesas,fcpv"; 2154 reg = <0 0xfe96f000 0 0x200>; 2155 clocks = <&cpg CPG_MOD 607>; 2156 power-domains = <&sysc R8A77961_PD_A3VC>; 2157 resets = <&cpg 607>; 2158 }; 2159 2160 fcpvi0: fcp@fe9af000 { 2161 compatible = "renesas,fcpv"; 2162 reg = <0 0xfe9af000 0 0x200>; 2163 clocks = <&cpg CPG_MOD 611>; 2164 power-domains = <&sysc R8A77961_PD_A3VC>; 2165 resets = <&cpg 611>; 2166 iommus = <&ipmmu_vc0 19>; 2167 }; 2168 2169 fcpvd0: fcp@fea27000 { 2170 compatible = "renesas,fcpv"; 2171 reg = <0 0xfea27000 0 0x200>; 2172 clocks = <&cpg CPG_MOD 603>; 2173 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2174 resets = <&cpg 603>; 2175 iommus = <&ipmmu_vi0 8>; 2176 }; 2177 2178 fcpvd1: fcp@fea2f000 { 2179 compatible = "renesas,fcpv"; 2180 reg = <0 0xfea2f000 0 0x200>; 2181 clocks = <&cpg CPG_MOD 602>; 2182 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2183 resets = <&cpg 602>; 2184 iommus = <&ipmmu_vi0 9>; 2185 }; 2186 2187 fcpvd2: fcp@fea37000 { 2188 compatible = "renesas,fcpv"; 2189 reg = <0 0xfea37000 0 0x200>; 2190 clocks = <&cpg CPG_MOD 601>; 2191 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2192 resets = <&cpg 601>; 2193 iommus = <&ipmmu_vi0 10>; 2194 }; 2195 2196 vspb: vsp@fe960000 { 2197 compatible = "renesas,vsp2"; 2198 reg = <0 0xfe960000 0 0x8000>; 2199 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 2200 clocks = <&cpg CPG_MOD 626>; 2201 power-domains = <&sysc R8A77961_PD_A3VC>; 2202 resets = <&cpg 626>; 2203 2204 renesas,fcp = <&fcpvb0>; 2205 }; 2206 2207 vspd0: vsp@fea20000 { 2208 compatible = "renesas,vsp2"; 2209 reg = <0 0xfea20000 0 0x5000>; 2210 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 2211 clocks = <&cpg CPG_MOD 623>; 2212 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2213 resets = <&cpg 623>; 2214 2215 renesas,fcp = <&fcpvd0>; 2216 }; 2217 2218 vspd1: vsp@fea28000 { 2219 compatible = "renesas,vsp2"; 2220 reg = <0 0xfea28000 0 0x5000>; 2221 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 2222 clocks = <&cpg CPG_MOD 622>; 2223 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2224 resets = <&cpg 622>; 2225 2226 renesas,fcp = <&fcpvd1>; 2227 }; 2228 2229 vspd2: vsp@fea30000 { 2230 compatible = "renesas,vsp2"; 2231 reg = <0 0xfea30000 0 0x5000>; 2232 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 2233 clocks = <&cpg CPG_MOD 621>; 2234 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2235 resets = <&cpg 621>; 2236 2237 renesas,fcp = <&fcpvd2>; 2238 }; 2239 2240 vspi0: vsp@fe9a0000 { 2241 compatible = "renesas,vsp2"; 2242 reg = <0 0xfe9a0000 0 0x8000>; 2243 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 2244 clocks = <&cpg CPG_MOD 631>; 2245 power-domains = <&sysc R8A77961_PD_A3VC>; 2246 resets = <&cpg 631>; 2247 2248 renesas,fcp = <&fcpvi0>; 2249 }; 2250 2251 csi20: csi2@fea80000 { 2252 reg = <0 0xfea80000 0 0x10000>; 2253 /* placeholder */ 2254 2255 ports { 2256 #address-cells = <1>; 2257 #size-cells = <0>; 2258 2259 port@1 { 2260 #address-cells = <1>; 2261 #size-cells = <0>; 2262 reg = <1>; 2263 }; 2264 }; 2265 }; 2266 2267 csi40: csi2@feaa0000 { 2268 reg = <0 0xfeaa0000 0 0x10000>; 2269 /* placeholder */ 2270 2271 ports { 2272 #address-cells = <1>; 2273 #size-cells = <0>; 2274 2275 port@1 { 2276 #address-cells = <1>; 2277 #size-cells = <0>; 2278 2279 reg = <1>; 2280 }; 2281 }; 2282 }; 2283 2284 hdmi0: hdmi@fead0000 { 2285 compatible = "renesas,r8a77961-hdmi", "renesas,rcar-gen3-hdmi"; 2286 reg = <0 0xfead0000 0 0x10000>; 2287 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 2288 clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A77961_CLK_HDMI>; 2289 clock-names = "iahb", "isfr"; 2290 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2291 resets = <&cpg 729>; 2292 status = "disabled"; 2293 2294 ports { 2295 #address-cells = <1>; 2296 #size-cells = <0>; 2297 port@0 { 2298 reg = <0>; 2299 dw_hdmi0_in: endpoint { 2300 remote-endpoint = <&du_out_hdmi0>; 2301 }; 2302 }; 2303 port@1 { 2304 reg = <1>; 2305 }; 2306 port@2 { 2307 /* HDMI sound */ 2308 reg = <2>; 2309 }; 2310 }; 2311 }; 2312 2313 du: display@feb00000 { 2314 compatible = "renesas,du-r8a77961"; 2315 reg = <0 0xfeb00000 0 0x70000>; 2316 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2317 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2318 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2319 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, 2320 <&cpg CPG_MOD 722>; 2321 clock-names = "du.0", "du.1", "du.2"; 2322 resets = <&cpg 724>, <&cpg 722>; 2323 reset-names = "du.0", "du.2"; 2324 2325 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; 2326 status = "disabled"; 2327 2328 ports { 2329 #address-cells = <1>; 2330 #size-cells = <0>; 2331 2332 port@0 { 2333 reg = <0>; 2334 du_out_rgb: endpoint { 2335 }; 2336 }; 2337 port@1 { 2338 reg = <1>; 2339 du_out_hdmi0: endpoint { 2340 remote-endpoint = <&dw_hdmi0_in>; 2341 }; 2342 }; 2343 port@2 { 2344 reg = <2>; 2345 du_out_lvds0: endpoint { 2346 }; 2347 }; 2348 }; 2349 }; 2350 2351 prr: chipid@fff00044 { 2352 compatible = "renesas,prr"; 2353 reg = <0 0xfff00044 0 4>; 2354 }; 2355 }; 2356 2357 thermal-zones { 2358 sensor_thermal1: sensor-thermal1 { 2359 polling-delay-passive = <250>; 2360 polling-delay = <1000>; 2361 thermal-sensors = <&tsc 0>; 2362 sustainable-power = <3874>; 2363 2364 trips { 2365 sensor1_crit: sensor1-crit { 2366 temperature = <120000>; 2367 hysteresis = <1000>; 2368 type = "critical"; 2369 }; 2370 }; 2371 }; 2372 2373 sensor_thermal2: sensor-thermal2 { 2374 polling-delay-passive = <250>; 2375 polling-delay = <1000>; 2376 thermal-sensors = <&tsc 1>; 2377 sustainable-power = <3874>; 2378 2379 trips { 2380 sensor2_crit: sensor2-crit { 2381 temperature = <120000>; 2382 hysteresis = <1000>; 2383 type = "critical"; 2384 }; 2385 }; 2386 }; 2387 2388 sensor_thermal3: sensor-thermal3 { 2389 polling-delay-passive = <250>; 2390 polling-delay = <1000>; 2391 thermal-sensors = <&tsc 2>; 2392 sustainable-power = <3874>; 2393 2394 cooling-maps { 2395 map0 { 2396 trip = <&target>; 2397 cooling-device = <&a57_0 2 4>; 2398 contribution = <1024>; 2399 }; 2400 map1 { 2401 trip = <&target>; 2402 cooling-device = <&a53_0 0 2>; 2403 contribution = <1024>; 2404 }; 2405 }; 2406 trips { 2407 target: trip-point1 { 2408 temperature = <100000>; 2409 hysteresis = <1000>; 2410 type = "passive"; 2411 }; 2412 2413 sensor3_crit: sensor3-crit { 2414 temperature = <120000>; 2415 hysteresis = <1000>; 2416 type = "critical"; 2417 }; 2418 }; 2419 }; 2420 }; 2421 2422 timer { 2423 compatible = "arm,armv8-timer"; 2424 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2425 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2426 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2427 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 2428 }; 2429 2430 /* External USB clocks - can be overridden by the board */ 2431 usb3s0_clk: usb3s0 { 2432 compatible = "fixed-clock"; 2433 #clock-cells = <0>; 2434 clock-frequency = <0>; 2435 }; 2436 2437 usb_extal_clk: usb_extal { 2438 compatible = "fixed-clock"; 2439 #clock-cells = <0>; 2440 clock-frequency = <0>; 2441 }; 2442}; 2443