1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC 4 * 5 * Copyright (C) 2016-2017 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a77961-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a77961-sysc.h> 11 12#define CPG_AUDIO_CLK_I R8A77961_CLK_S0D4 13 14/ { 15 compatible = "renesas,r8a77961"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* 20 * The external audio clocks are configured as 0 Hz fixed frequency 21 * clocks by default. 22 * Boards that provide audio clocks should override them. 23 */ 24 audio_clk_a: audio_clk_a { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <0>; 28 }; 29 30 audio_clk_b: audio_clk_b { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <0>; 34 }; 35 36 audio_clk_c: audio_clk_c { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <0>; 40 }; 41 42 /* External CAN clock - to be overridden by boards that provide it */ 43 can_clk: can { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <0>; 47 }; 48 49 cluster0_opp: opp_table0 { 50 compatible = "operating-points-v2"; 51 opp-shared; 52 53 opp-500000000 { 54 opp-hz = /bits/ 64 <500000000>; 55 opp-microvolt = <820000>; 56 clock-latency-ns = <300000>; 57 }; 58 opp-1000000000 { 59 opp-hz = /bits/ 64 <1000000000>; 60 opp-microvolt = <820000>; 61 clock-latency-ns = <300000>; 62 }; 63 opp-1500000000 { 64 opp-hz = /bits/ 64 <1500000000>; 65 opp-microvolt = <820000>; 66 clock-latency-ns = <300000>; 67 }; 68 opp-1600000000 { 69 opp-hz = /bits/ 64 <1600000000>; 70 opp-microvolt = <900000>; 71 clock-latency-ns = <300000>; 72 turbo-mode; 73 }; 74 opp-1700000000 { 75 opp-hz = /bits/ 64 <1700000000>; 76 opp-microvolt = <900000>; 77 clock-latency-ns = <300000>; 78 turbo-mode; 79 }; 80 opp-1800000000 { 81 opp-hz = /bits/ 64 <1800000000>; 82 opp-microvolt = <960000>; 83 clock-latency-ns = <300000>; 84 turbo-mode; 85 }; 86 }; 87 88 cluster1_opp: opp_table1 { 89 compatible = "operating-points-v2"; 90 opp-shared; 91 92 opp-800000000 { 93 opp-hz = /bits/ 64 <800000000>; 94 opp-microvolt = <820000>; 95 clock-latency-ns = <300000>; 96 }; 97 opp-1000000000 { 98 opp-hz = /bits/ 64 <1000000000>; 99 opp-microvolt = <820000>; 100 clock-latency-ns = <300000>; 101 }; 102 opp-1200000000 { 103 opp-hz = /bits/ 64 <1200000000>; 104 opp-microvolt = <820000>; 105 clock-latency-ns = <300000>; 106 }; 107 opp-1300000000 { 108 opp-hz = /bits/ 64 <1300000000>; 109 opp-microvolt = <820000>; 110 clock-latency-ns = <300000>; 111 turbo-mode; 112 }; 113 }; 114 115 cpus { 116 #address-cells = <1>; 117 #size-cells = <0>; 118 119 cpu-map { 120 cluster0 { 121 core0 { 122 cpu = <&a57_0>; 123 }; 124 core1 { 125 cpu = <&a57_1>; 126 }; 127 }; 128 129 cluster1 { 130 core0 { 131 cpu = <&a53_0>; 132 }; 133 core1 { 134 cpu = <&a53_1>; 135 }; 136 core2 { 137 cpu = <&a53_2>; 138 }; 139 core3 { 140 cpu = <&a53_3>; 141 }; 142 }; 143 }; 144 145 a57_0: cpu@0 { 146 compatible = "arm,cortex-a57"; 147 reg = <0x0>; 148 device_type = "cpu"; 149 power-domains = <&sysc R8A77961_PD_CA57_CPU0>; 150 next-level-cache = <&L2_CA57>; 151 enable-method = "psci"; 152 cpu-idle-states = <&CPU_SLEEP_0>; 153 dynamic-power-coefficient = <854>; 154 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; 155 operating-points-v2 = <&cluster0_opp>; 156 capacity-dmips-mhz = <1024>; 157 #cooling-cells = <2>; 158 }; 159 160 a57_1: cpu@1 { 161 compatible = "arm,cortex-a57"; 162 reg = <0x1>; 163 device_type = "cpu"; 164 power-domains = <&sysc R8A77961_PD_CA57_CPU1>; 165 next-level-cache = <&L2_CA57>; 166 enable-method = "psci"; 167 cpu-idle-states = <&CPU_SLEEP_0>; 168 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; 169 operating-points-v2 = <&cluster0_opp>; 170 capacity-dmips-mhz = <1024>; 171 #cooling-cells = <2>; 172 }; 173 174 a53_0: cpu@100 { 175 compatible = "arm,cortex-a53"; 176 reg = <0x100>; 177 device_type = "cpu"; 178 power-domains = <&sysc R8A77961_PD_CA53_CPU0>; 179 next-level-cache = <&L2_CA53>; 180 enable-method = "psci"; 181 cpu-idle-states = <&CPU_SLEEP_1>; 182 #cooling-cells = <2>; 183 dynamic-power-coefficient = <277>; 184 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 185 operating-points-v2 = <&cluster1_opp>; 186 capacity-dmips-mhz = <535>; 187 }; 188 189 a53_1: cpu@101 { 190 compatible = "arm,cortex-a53"; 191 reg = <0x101>; 192 device_type = "cpu"; 193 power-domains = <&sysc R8A77961_PD_CA53_CPU1>; 194 next-level-cache = <&L2_CA53>; 195 enable-method = "psci"; 196 cpu-idle-states = <&CPU_SLEEP_1>; 197 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 198 operating-points-v2 = <&cluster1_opp>; 199 capacity-dmips-mhz = <535>; 200 }; 201 202 a53_2: cpu@102 { 203 compatible = "arm,cortex-a53"; 204 reg = <0x102>; 205 device_type = "cpu"; 206 power-domains = <&sysc R8A77961_PD_CA53_CPU2>; 207 next-level-cache = <&L2_CA53>; 208 enable-method = "psci"; 209 cpu-idle-states = <&CPU_SLEEP_1>; 210 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 211 operating-points-v2 = <&cluster1_opp>; 212 capacity-dmips-mhz = <535>; 213 }; 214 215 a53_3: cpu@103 { 216 compatible = "arm,cortex-a53"; 217 reg = <0x103>; 218 device_type = "cpu"; 219 power-domains = <&sysc R8A77961_PD_CA53_CPU3>; 220 next-level-cache = <&L2_CA53>; 221 enable-method = "psci"; 222 cpu-idle-states = <&CPU_SLEEP_1>; 223 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 224 operating-points-v2 = <&cluster1_opp>; 225 capacity-dmips-mhz = <535>; 226 }; 227 228 L2_CA57: cache-controller-0 { 229 compatible = "cache"; 230 power-domains = <&sysc R8A77961_PD_CA57_SCU>; 231 cache-unified; 232 cache-level = <2>; 233 }; 234 235 L2_CA53: cache-controller-1 { 236 compatible = "cache"; 237 power-domains = <&sysc R8A77961_PD_CA53_SCU>; 238 cache-unified; 239 cache-level = <2>; 240 }; 241 242 idle-states { 243 entry-method = "psci"; 244 245 CPU_SLEEP_0: cpu-sleep-0 { 246 compatible = "arm,idle-state"; 247 arm,psci-suspend-param = <0x0010000>; 248 local-timer-stop; 249 entry-latency-us = <400>; 250 exit-latency-us = <500>; 251 min-residency-us = <4000>; 252 }; 253 254 CPU_SLEEP_1: cpu-sleep-1 { 255 compatible = "arm,idle-state"; 256 arm,psci-suspend-param = <0x0010000>; 257 local-timer-stop; 258 entry-latency-us = <700>; 259 exit-latency-us = <700>; 260 min-residency-us = <5000>; 261 }; 262 }; 263 }; 264 265 extal_clk: extal { 266 compatible = "fixed-clock"; 267 #clock-cells = <0>; 268 /* This value must be overridden by the board */ 269 clock-frequency = <0>; 270 }; 271 272 extalr_clk: extalr { 273 compatible = "fixed-clock"; 274 #clock-cells = <0>; 275 /* This value must be overridden by the board */ 276 clock-frequency = <0>; 277 }; 278 279 /* External PCIe clock - can be overridden by the board */ 280 pcie_bus_clk: pcie_bus { 281 compatible = "fixed-clock"; 282 #clock-cells = <0>; 283 clock-frequency = <0>; 284 }; 285 286 pmu_a53 { 287 compatible = "arm,cortex-a53-pmu"; 288 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 289 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 290 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 291 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 292 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 293 }; 294 295 pmu_a57 { 296 compatible = "arm,cortex-a57-pmu"; 297 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 298 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 299 interrupt-affinity = <&a57_0>, <&a57_1>; 300 }; 301 302 psci { 303 compatible = "arm,psci-1.0", "arm,psci-0.2"; 304 method = "smc"; 305 }; 306 307 /* External SCIF clock - to be overridden by boards that provide it */ 308 scif_clk: scif { 309 compatible = "fixed-clock"; 310 #clock-cells = <0>; 311 clock-frequency = <0>; 312 }; 313 314 soc { 315 compatible = "simple-bus"; 316 interrupt-parent = <&gic>; 317 #address-cells = <2>; 318 #size-cells = <2>; 319 ranges; 320 321 rwdt: watchdog@e6020000 { 322 compatible = "renesas,r8a77961-wdt", 323 "renesas,rcar-gen3-wdt"; 324 reg = <0 0xe6020000 0 0x0c>; 325 clocks = <&cpg CPG_MOD 402>; 326 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 327 resets = <&cpg 402>; 328 status = "disabled"; 329 }; 330 331 gpio0: gpio@e6050000 { 332 compatible = "renesas,gpio-r8a77961", 333 "renesas,rcar-gen3-gpio"; 334 reg = <0 0xe6050000 0 0x50>; 335 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 336 #gpio-cells = <2>; 337 gpio-controller; 338 gpio-ranges = <&pfc 0 0 16>; 339 #interrupt-cells = <2>; 340 interrupt-controller; 341 clocks = <&cpg CPG_MOD 912>; 342 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 343 resets = <&cpg 912>; 344 }; 345 346 gpio1: gpio@e6051000 { 347 compatible = "renesas,gpio-r8a77961", 348 "renesas,rcar-gen3-gpio"; 349 reg = <0 0xe6051000 0 0x50>; 350 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 351 #gpio-cells = <2>; 352 gpio-controller; 353 gpio-ranges = <&pfc 0 32 29>; 354 #interrupt-cells = <2>; 355 interrupt-controller; 356 clocks = <&cpg CPG_MOD 911>; 357 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 358 resets = <&cpg 911>; 359 }; 360 361 gpio2: gpio@e6052000 { 362 compatible = "renesas,gpio-r8a77961", 363 "renesas,rcar-gen3-gpio"; 364 reg = <0 0xe6052000 0 0x50>; 365 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 366 #gpio-cells = <2>; 367 gpio-controller; 368 gpio-ranges = <&pfc 0 64 15>; 369 #interrupt-cells = <2>; 370 interrupt-controller; 371 clocks = <&cpg CPG_MOD 910>; 372 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 373 resets = <&cpg 910>; 374 }; 375 376 gpio3: gpio@e6053000 { 377 compatible = "renesas,gpio-r8a77961", 378 "renesas,rcar-gen3-gpio"; 379 reg = <0 0xe6053000 0 0x50>; 380 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 381 #gpio-cells = <2>; 382 gpio-controller; 383 gpio-ranges = <&pfc 0 96 16>; 384 #interrupt-cells = <2>; 385 interrupt-controller; 386 clocks = <&cpg CPG_MOD 909>; 387 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 388 resets = <&cpg 909>; 389 }; 390 391 gpio4: gpio@e6054000 { 392 compatible = "renesas,gpio-r8a77961", 393 "renesas,rcar-gen3-gpio"; 394 reg = <0 0xe6054000 0 0x50>; 395 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 396 #gpio-cells = <2>; 397 gpio-controller; 398 gpio-ranges = <&pfc 0 128 18>; 399 #interrupt-cells = <2>; 400 interrupt-controller; 401 clocks = <&cpg CPG_MOD 908>; 402 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 403 resets = <&cpg 908>; 404 }; 405 406 gpio5: gpio@e6055000 { 407 compatible = "renesas,gpio-r8a77961", 408 "renesas,rcar-gen3-gpio"; 409 reg = <0 0xe6055000 0 0x50>; 410 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 411 #gpio-cells = <2>; 412 gpio-controller; 413 gpio-ranges = <&pfc 0 160 26>; 414 #interrupt-cells = <2>; 415 interrupt-controller; 416 clocks = <&cpg CPG_MOD 907>; 417 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 418 resets = <&cpg 907>; 419 }; 420 421 gpio6: gpio@e6055400 { 422 compatible = "renesas,gpio-r8a77961", 423 "renesas,rcar-gen3-gpio"; 424 reg = <0 0xe6055400 0 0x50>; 425 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 426 #gpio-cells = <2>; 427 gpio-controller; 428 gpio-ranges = <&pfc 0 192 32>; 429 #interrupt-cells = <2>; 430 interrupt-controller; 431 clocks = <&cpg CPG_MOD 906>; 432 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 433 resets = <&cpg 906>; 434 }; 435 436 gpio7: gpio@e6055800 { 437 compatible = "renesas,gpio-r8a77961", 438 "renesas,rcar-gen3-gpio"; 439 reg = <0 0xe6055800 0 0x50>; 440 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 441 #gpio-cells = <2>; 442 gpio-controller; 443 gpio-ranges = <&pfc 0 224 4>; 444 #interrupt-cells = <2>; 445 interrupt-controller; 446 clocks = <&cpg CPG_MOD 905>; 447 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 448 resets = <&cpg 905>; 449 }; 450 451 pfc: pinctrl@e6060000 { 452 compatible = "renesas,pfc-r8a77961"; 453 reg = <0 0xe6060000 0 0x50c>; 454 }; 455 456 cpg: clock-controller@e6150000 { 457 compatible = "renesas,r8a77961-cpg-mssr"; 458 reg = <0 0xe6150000 0 0x1000>; 459 clocks = <&extal_clk>, <&extalr_clk>; 460 clock-names = "extal", "extalr"; 461 #clock-cells = <2>; 462 #power-domain-cells = <0>; 463 #reset-cells = <1>; 464 }; 465 466 rst: reset-controller@e6160000 { 467 compatible = "renesas,r8a77961-rst"; 468 reg = <0 0xe6160000 0 0x0200>; 469 }; 470 471 sysc: system-controller@e6180000 { 472 compatible = "renesas,r8a77961-sysc"; 473 reg = <0 0xe6180000 0 0x0400>; 474 #power-domain-cells = <1>; 475 }; 476 477 tsc: thermal@e6198000 { 478 compatible = "renesas,r8a77961-thermal"; 479 reg = <0 0xe6198000 0 0x100>, 480 <0 0xe61a0000 0 0x100>, 481 <0 0xe61a8000 0 0x100>; 482 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 485 clocks = <&cpg CPG_MOD 522>; 486 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 487 resets = <&cpg 522>; 488 #thermal-sensor-cells = <1>; 489 }; 490 491 intc_ex: interrupt-controller@e61c0000 { 492 #interrupt-cells = <2>; 493 interrupt-controller; 494 reg = <0 0xe61c0000 0 0x200>; 495 /* placeholder */ 496 }; 497 498 i2c0: i2c@e6500000 { 499 #address-cells = <1>; 500 #size-cells = <0>; 501 compatible = "renesas,i2c-r8a77961", 502 "renesas,rcar-gen3-i2c"; 503 reg = <0 0xe6500000 0 0x40>; 504 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&cpg CPG_MOD 931>; 506 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 507 resets = <&cpg 931>; 508 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 509 <&dmac2 0x91>, <&dmac2 0x90>; 510 dma-names = "tx", "rx", "tx", "rx"; 511 i2c-scl-internal-delay-ns = <110>; 512 status = "disabled"; 513 }; 514 515 i2c1: i2c@e6508000 { 516 #address-cells = <1>; 517 #size-cells = <0>; 518 compatible = "renesas,i2c-r8a77961", 519 "renesas,rcar-gen3-i2c"; 520 reg = <0 0xe6508000 0 0x40>; 521 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&cpg CPG_MOD 930>; 523 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 524 resets = <&cpg 930>; 525 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 526 <&dmac2 0x93>, <&dmac2 0x92>; 527 dma-names = "tx", "rx", "tx", "rx"; 528 i2c-scl-internal-delay-ns = <6>; 529 status = "disabled"; 530 }; 531 532 i2c2: i2c@e6510000 { 533 #address-cells = <1>; 534 #size-cells = <0>; 535 compatible = "renesas,i2c-r8a77961", 536 "renesas,rcar-gen3-i2c"; 537 reg = <0 0xe6510000 0 0x40>; 538 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&cpg CPG_MOD 929>; 540 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 541 resets = <&cpg 929>; 542 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 543 <&dmac2 0x95>, <&dmac2 0x94>; 544 dma-names = "tx", "rx", "tx", "rx"; 545 i2c-scl-internal-delay-ns = <6>; 546 status = "disabled"; 547 }; 548 549 i2c3: i2c@e66d0000 { 550 #address-cells = <1>; 551 #size-cells = <0>; 552 compatible = "renesas,i2c-r8a77961", 553 "renesas,rcar-gen3-i2c"; 554 reg = <0 0xe66d0000 0 0x40>; 555 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&cpg CPG_MOD 928>; 557 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 558 resets = <&cpg 928>; 559 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 560 dma-names = "tx", "rx"; 561 i2c-scl-internal-delay-ns = <110>; 562 status = "disabled"; 563 }; 564 565 i2c4: i2c@e66d8000 { 566 #address-cells = <1>; 567 #size-cells = <0>; 568 compatible = "renesas,i2c-r8a77961", 569 "renesas,rcar-gen3-i2c"; 570 reg = <0 0xe66d8000 0 0x40>; 571 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&cpg CPG_MOD 927>; 573 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 574 resets = <&cpg 927>; 575 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 576 dma-names = "tx", "rx"; 577 i2c-scl-internal-delay-ns = <110>; 578 status = "disabled"; 579 }; 580 581 i2c5: i2c@e66e0000 { 582 #address-cells = <1>; 583 #size-cells = <0>; 584 compatible = "renesas,i2c-r8a77961", 585 "renesas,rcar-gen3-i2c"; 586 reg = <0 0xe66e0000 0 0x40>; 587 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&cpg CPG_MOD 919>; 589 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 590 resets = <&cpg 919>; 591 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 592 dma-names = "tx", "rx"; 593 i2c-scl-internal-delay-ns = <110>; 594 status = "disabled"; 595 }; 596 597 i2c6: i2c@e66e8000 { 598 #address-cells = <1>; 599 #size-cells = <0>; 600 compatible = "renesas,i2c-r8a77961", 601 "renesas,rcar-gen3-i2c"; 602 reg = <0 0xe66e8000 0 0x40>; 603 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&cpg CPG_MOD 918>; 605 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 606 resets = <&cpg 918>; 607 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 608 dma-names = "tx", "rx"; 609 i2c-scl-internal-delay-ns = <6>; 610 status = "disabled"; 611 }; 612 613 i2c_dvfs: i2c@e60b0000 { 614 #address-cells = <1>; 615 #size-cells = <0>; 616 compatible = "renesas,iic-r8a77961", 617 "renesas,rcar-gen3-iic", 618 "renesas,rmobile-iic"; 619 reg = <0 0xe60b0000 0 0x425>; 620 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&cpg CPG_MOD 926>; 622 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 623 resets = <&cpg 926>; 624 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 625 dma-names = "tx", "rx"; 626 status = "disabled"; 627 }; 628 629 hscif0: serial@e6540000 { 630 compatible = "renesas,hscif-r8a77961", 631 "renesas,rcar-gen3-hscif", 632 "renesas,hscif"; 633 reg = <0 0xe6540000 0 0x60>; 634 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 635 clocks = <&cpg CPG_MOD 520>, 636 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 637 <&scif_clk>; 638 clock-names = "fck", "brg_int", "scif_clk"; 639 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 640 <&dmac2 0x31>, <&dmac2 0x30>; 641 dma-names = "tx", "rx", "tx", "rx"; 642 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 643 resets = <&cpg 520>; 644 status = "disabled"; 645 }; 646 647 hscif1: serial@e6550000 { 648 compatible = "renesas,hscif-r8a77961", 649 "renesas,rcar-gen3-hscif", 650 "renesas,hscif"; 651 reg = <0 0xe6550000 0 0x60>; 652 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 653 clocks = <&cpg CPG_MOD 519>, 654 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 655 <&scif_clk>; 656 clock-names = "fck", "brg_int", "scif_clk"; 657 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 658 <&dmac2 0x33>, <&dmac2 0x32>; 659 dma-names = "tx", "rx", "tx", "rx"; 660 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 661 resets = <&cpg 519>; 662 status = "disabled"; 663 }; 664 665 hscif2: serial@e6560000 { 666 compatible = "renesas,hscif-r8a77961", 667 "renesas,rcar-gen3-hscif", 668 "renesas,hscif"; 669 reg = <0 0xe6560000 0 0x60>; 670 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&cpg CPG_MOD 518>, 672 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 673 <&scif_clk>; 674 clock-names = "fck", "brg_int", "scif_clk"; 675 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 676 <&dmac2 0x35>, <&dmac2 0x34>; 677 dma-names = "tx", "rx", "tx", "rx"; 678 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 679 resets = <&cpg 518>; 680 status = "disabled"; 681 }; 682 683 hscif3: serial@e66a0000 { 684 compatible = "renesas,hscif-r8a77961", 685 "renesas,rcar-gen3-hscif", 686 "renesas,hscif"; 687 reg = <0 0xe66a0000 0 0x60>; 688 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&cpg CPG_MOD 517>, 690 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 691 <&scif_clk>; 692 clock-names = "fck", "brg_int", "scif_clk"; 693 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 694 dma-names = "tx", "rx"; 695 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 696 resets = <&cpg 517>; 697 status = "disabled"; 698 }; 699 700 hscif4: serial@e66b0000 { 701 compatible = "renesas,hscif-r8a77961", 702 "renesas,rcar-gen3-hscif", 703 "renesas,hscif"; 704 reg = <0 0xe66b0000 0 0x60>; 705 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 706 clocks = <&cpg CPG_MOD 516>, 707 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 708 <&scif_clk>; 709 clock-names = "fck", "brg_int", "scif_clk"; 710 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 711 dma-names = "tx", "rx"; 712 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 713 resets = <&cpg 516>; 714 status = "disabled"; 715 }; 716 717 hsusb: usb@e6590000 { 718 compatible = "renesas,usbhs-r8a77961", 719 "renesas,rcar-gen3-usbhs"; 720 reg = <0 0xe6590000 0 0x200>; 721 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 723 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 724 <&usb_dmac1 0>, <&usb_dmac1 1>; 725 dma-names = "ch0", "ch1", "ch2", "ch3"; 726 renesas,buswait = <11>; 727 phys = <&usb2_phy0 3>; 728 phy-names = "usb"; 729 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 730 resets = <&cpg 704>, <&cpg 703>; 731 status = "disabled"; 732 }; 733 734 usb_dmac0: dma-controller@e65a0000 { 735 compatible = "renesas,r8a77961-usb-dmac", 736 "renesas,usb-dmac"; 737 reg = <0 0xe65a0000 0 0x100>; 738 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 740 interrupt-names = "ch0", "ch1"; 741 clocks = <&cpg CPG_MOD 330>; 742 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 743 resets = <&cpg 330>; 744 #dma-cells = <1>; 745 dma-channels = <2>; 746 }; 747 748 usb_dmac1: dma-controller@e65b0000 { 749 compatible = "renesas,r8a77961-usb-dmac", 750 "renesas,usb-dmac"; 751 reg = <0 0xe65b0000 0 0x100>; 752 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 754 interrupt-names = "ch0", "ch1"; 755 clocks = <&cpg CPG_MOD 331>; 756 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 757 resets = <&cpg 331>; 758 #dma-cells = <1>; 759 dma-channels = <2>; 760 }; 761 762 usb3_phy0: usb-phy@e65ee000 { 763 compatible = "renesas,r8a77961-usb3-phy", 764 "renesas,rcar-gen3-usb3-phy"; 765 reg = <0 0xe65ee000 0 0x90>; 766 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 767 <&usb_extal_clk>; 768 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 769 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 770 resets = <&cpg 328>; 771 #phy-cells = <0>; 772 status = "disabled"; 773 }; 774 775 arm_cc630p: crypto@e6601000 { 776 compatible = "arm,cryptocell-630p-ree"; 777 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 778 reg = <0x0 0xe6601000 0 0x1000>; 779 clocks = <&cpg CPG_MOD 229>; 780 resets = <&cpg 229>; 781 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 782 }; 783 784 dmac0: dma-controller@e6700000 { 785 compatible = "renesas,dmac-r8a77961", 786 "renesas,rcar-dmac"; 787 reg = <0 0xe6700000 0 0x10000>; 788 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 800 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 805 interrupt-names = "error", 806 "ch0", "ch1", "ch2", "ch3", 807 "ch4", "ch5", "ch6", "ch7", 808 "ch8", "ch9", "ch10", "ch11", 809 "ch12", "ch13", "ch14", "ch15"; 810 clocks = <&cpg CPG_MOD 219>; 811 clock-names = "fck"; 812 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 813 resets = <&cpg 219>; 814 #dma-cells = <1>; 815 dma-channels = <16>; 816 }; 817 818 dmac1: dma-controller@e7300000 { 819 compatible = "renesas,dmac-r8a77961", 820 "renesas,rcar-dmac"; 821 reg = <0 0xe7300000 0 0x10000>; 822 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 828 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 830 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 839 interrupt-names = "error", 840 "ch0", "ch1", "ch2", "ch3", 841 "ch4", "ch5", "ch6", "ch7", 842 "ch8", "ch9", "ch10", "ch11", 843 "ch12", "ch13", "ch14", "ch15"; 844 clocks = <&cpg CPG_MOD 218>; 845 clock-names = "fck"; 846 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 847 resets = <&cpg 218>; 848 #dma-cells = <1>; 849 dma-channels = <16>; 850 }; 851 852 dmac2: dma-controller@e7310000 { 853 compatible = "renesas,dmac-r8a77961", 854 "renesas,rcar-dmac"; 855 reg = <0 0xe7310000 0 0x10000>; 856 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 873 interrupt-names = "error", 874 "ch0", "ch1", "ch2", "ch3", 875 "ch4", "ch5", "ch6", "ch7", 876 "ch8", "ch9", "ch10", "ch11", 877 "ch12", "ch13", "ch14", "ch15"; 878 clocks = <&cpg CPG_MOD 217>; 879 clock-names = "fck"; 880 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 881 resets = <&cpg 217>; 882 #dma-cells = <1>; 883 dma-channels = <16>; 884 }; 885 886 ipmmu_ds0: iommu@e6740000 { 887 compatible = "renesas,ipmmu-r8a77961"; 888 reg = <0 0xe6740000 0 0x1000>; 889 renesas,ipmmu-main = <&ipmmu_mm 0>; 890 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 891 #iommu-cells = <1>; 892 }; 893 894 ipmmu_ds1: iommu@e7740000 { 895 compatible = "renesas,ipmmu-r8a77961"; 896 reg = <0 0xe7740000 0 0x1000>; 897 renesas,ipmmu-main = <&ipmmu_mm 1>; 898 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 899 #iommu-cells = <1>; 900 }; 901 902 ipmmu_hc: iommu@e6570000 { 903 compatible = "renesas,ipmmu-r8a77961"; 904 reg = <0 0xe6570000 0 0x1000>; 905 renesas,ipmmu-main = <&ipmmu_mm 2>; 906 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 907 #iommu-cells = <1>; 908 }; 909 910 ipmmu_ir: iommu@ff8b0000 { 911 compatible = "renesas,ipmmu-r8a77961"; 912 reg = <0 0xff8b0000 0 0x1000>; 913 renesas,ipmmu-main = <&ipmmu_mm 3>; 914 power-domains = <&sysc R8A77961_PD_A3IR>; 915 #iommu-cells = <1>; 916 }; 917 918 ipmmu_mm: iommu@e67b0000 { 919 compatible = "renesas,ipmmu-r8a77961"; 920 reg = <0 0xe67b0000 0 0x1000>; 921 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 923 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 924 #iommu-cells = <1>; 925 }; 926 927 ipmmu_mp: iommu@ec670000 { 928 compatible = "renesas,ipmmu-r8a77961"; 929 reg = <0 0xec670000 0 0x1000>; 930 renesas,ipmmu-main = <&ipmmu_mm 4>; 931 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 932 #iommu-cells = <1>; 933 }; 934 935 ipmmu_pv0: iommu@fd800000 { 936 compatible = "renesas,ipmmu-r8a77961"; 937 reg = <0 0xfd800000 0 0x1000>; 938 renesas,ipmmu-main = <&ipmmu_mm 5>; 939 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 940 #iommu-cells = <1>; 941 }; 942 943 ipmmu_pv1: iommu@fd950000 { 944 compatible = "renesas,ipmmu-r8a77961"; 945 reg = <0 0xfd950000 0 0x1000>; 946 renesas,ipmmu-main = <&ipmmu_mm 6>; 947 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 948 #iommu-cells = <1>; 949 }; 950 951 ipmmu_rt: iommu@ffc80000 { 952 compatible = "renesas,ipmmu-r8a77961"; 953 reg = <0 0xffc80000 0 0x1000>; 954 renesas,ipmmu-main = <&ipmmu_mm 7>; 955 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 956 #iommu-cells = <1>; 957 }; 958 959 ipmmu_vc0: iommu@fe6b0000 { 960 compatible = "renesas,ipmmu-r8a77961"; 961 reg = <0 0xfe6b0000 0 0x1000>; 962 renesas,ipmmu-main = <&ipmmu_mm 8>; 963 power-domains = <&sysc R8A77961_PD_A3VC>; 964 #iommu-cells = <1>; 965 }; 966 967 ipmmu_vi0: iommu@febd0000 { 968 compatible = "renesas,ipmmu-r8a77961"; 969 reg = <0 0xfebd0000 0 0x1000>; 970 renesas,ipmmu-main = <&ipmmu_mm 9>; 971 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 972 #iommu-cells = <1>; 973 }; 974 975 avb: ethernet@e6800000 { 976 compatible = "renesas,etheravb-r8a77961", 977 "renesas,etheravb-rcar-gen3"; 978 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 979 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 981 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 982 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1001 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1002 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1003 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1004 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1005 "ch4", "ch5", "ch6", "ch7", 1006 "ch8", "ch9", "ch10", "ch11", 1007 "ch12", "ch13", "ch14", "ch15", 1008 "ch16", "ch17", "ch18", "ch19", 1009 "ch20", "ch21", "ch22", "ch23", 1010 "ch24"; 1011 clocks = <&cpg CPG_MOD 812>; 1012 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1013 resets = <&cpg 812>; 1014 phy-mode = "rgmii"; 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 status = "disabled"; 1018 }; 1019 1020 pwm0: pwm@e6e30000 { 1021 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1022 reg = <0 0xe6e30000 0 8>; 1023 #pwm-cells = <2>; 1024 clocks = <&cpg CPG_MOD 523>; 1025 resets = <&cpg 523>; 1026 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1027 status = "disabled"; 1028 }; 1029 1030 pwm1: pwm@e6e31000 { 1031 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1032 reg = <0 0xe6e31000 0 8>; 1033 #pwm-cells = <2>; 1034 clocks = <&cpg CPG_MOD 523>; 1035 resets = <&cpg 523>; 1036 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1037 status = "disabled"; 1038 }; 1039 1040 pwm2: pwm@e6e32000 { 1041 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1042 reg = <0 0xe6e32000 0 8>; 1043 #pwm-cells = <2>; 1044 clocks = <&cpg CPG_MOD 523>; 1045 resets = <&cpg 523>; 1046 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1047 status = "disabled"; 1048 }; 1049 1050 pwm3: pwm@e6e33000 { 1051 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1052 reg = <0 0xe6e33000 0 8>; 1053 #pwm-cells = <2>; 1054 clocks = <&cpg CPG_MOD 523>; 1055 resets = <&cpg 523>; 1056 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1057 status = "disabled"; 1058 }; 1059 1060 pwm4: pwm@e6e34000 { 1061 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1062 reg = <0 0xe6e34000 0 8>; 1063 #pwm-cells = <2>; 1064 clocks = <&cpg CPG_MOD 523>; 1065 resets = <&cpg 523>; 1066 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1067 status = "disabled"; 1068 }; 1069 1070 pwm5: pwm@e6e35000 { 1071 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1072 reg = <0 0xe6e35000 0 8>; 1073 #pwm-cells = <2>; 1074 clocks = <&cpg CPG_MOD 523>; 1075 resets = <&cpg 523>; 1076 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1077 status = "disabled"; 1078 }; 1079 1080 pwm6: pwm@e6e36000 { 1081 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1082 reg = <0 0xe6e36000 0 8>; 1083 #pwm-cells = <2>; 1084 clocks = <&cpg CPG_MOD 523>; 1085 resets = <&cpg 523>; 1086 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1087 status = "disabled"; 1088 }; 1089 1090 scif0: serial@e6e60000 { 1091 compatible = "renesas,scif-r8a77961", 1092 "renesas,rcar-gen3-scif", "renesas,scif"; 1093 reg = <0 0xe6e60000 0 64>; 1094 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1095 clocks = <&cpg CPG_MOD 207>, 1096 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1097 <&scif_clk>; 1098 clock-names = "fck", "brg_int", "scif_clk"; 1099 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1100 <&dmac2 0x51>, <&dmac2 0x50>; 1101 dma-names = "tx", "rx", "tx", "rx"; 1102 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1103 resets = <&cpg 207>; 1104 status = "disabled"; 1105 }; 1106 1107 scif1: serial@e6e68000 { 1108 compatible = "renesas,scif-r8a77961", 1109 "renesas,rcar-gen3-scif", "renesas,scif"; 1110 reg = <0 0xe6e68000 0 64>; 1111 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1112 clocks = <&cpg CPG_MOD 206>, 1113 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1114 <&scif_clk>; 1115 clock-names = "fck", "brg_int", "scif_clk"; 1116 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1117 <&dmac2 0x53>, <&dmac2 0x52>; 1118 dma-names = "tx", "rx", "tx", "rx"; 1119 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1120 resets = <&cpg 206>; 1121 status = "disabled"; 1122 }; 1123 1124 scif2: serial@e6e88000 { 1125 compatible = "renesas,scif-r8a77961", 1126 "renesas,rcar-gen3-scif", "renesas,scif"; 1127 reg = <0 0xe6e88000 0 64>; 1128 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1129 clocks = <&cpg CPG_MOD 310>, 1130 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1131 <&scif_clk>; 1132 clock-names = "fck", "brg_int", "scif_clk"; 1133 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1134 <&dmac2 0x13>, <&dmac2 0x12>; 1135 dma-names = "tx", "rx", "tx", "rx"; 1136 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1137 resets = <&cpg 310>; 1138 status = "disabled"; 1139 }; 1140 1141 scif3: serial@e6c50000 { 1142 compatible = "renesas,scif-r8a77961", 1143 "renesas,rcar-gen3-scif", "renesas,scif"; 1144 reg = <0 0xe6c50000 0 64>; 1145 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1146 clocks = <&cpg CPG_MOD 204>, 1147 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1148 <&scif_clk>; 1149 clock-names = "fck", "brg_int", "scif_clk"; 1150 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1151 dma-names = "tx", "rx"; 1152 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1153 resets = <&cpg 204>; 1154 status = "disabled"; 1155 }; 1156 1157 scif4: serial@e6c40000 { 1158 compatible = "renesas,scif-r8a77961", 1159 "renesas,rcar-gen3-scif", "renesas,scif"; 1160 reg = <0 0xe6c40000 0 64>; 1161 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1162 clocks = <&cpg CPG_MOD 203>, 1163 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1164 <&scif_clk>; 1165 clock-names = "fck", "brg_int", "scif_clk"; 1166 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1167 dma-names = "tx", "rx"; 1168 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1169 resets = <&cpg 203>; 1170 status = "disabled"; 1171 }; 1172 1173 scif5: serial@e6f30000 { 1174 compatible = "renesas,scif-r8a77961", 1175 "renesas,rcar-gen3-scif", "renesas,scif"; 1176 reg = <0 0xe6f30000 0 64>; 1177 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1178 clocks = <&cpg CPG_MOD 202>, 1179 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1180 <&scif_clk>; 1181 clock-names = "fck", "brg_int", "scif_clk"; 1182 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1183 <&dmac2 0x5b>, <&dmac2 0x5a>; 1184 dma-names = "tx", "rx", "tx", "rx"; 1185 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1186 resets = <&cpg 202>; 1187 status = "disabled"; 1188 }; 1189 1190 msiof0: spi@e6e90000 { 1191 compatible = "renesas,msiof-r8a77961", 1192 "renesas,rcar-gen3-msiof"; 1193 reg = <0 0xe6e90000 0 0x0064>; 1194 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1195 clocks = <&cpg CPG_MOD 211>; 1196 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1197 <&dmac2 0x41>, <&dmac2 0x40>; 1198 dma-names = "tx", "rx", "tx", "rx"; 1199 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1200 resets = <&cpg 211>; 1201 #address-cells = <1>; 1202 #size-cells = <0>; 1203 status = "disabled"; 1204 }; 1205 1206 msiof1: spi@e6ea0000 { 1207 compatible = "renesas,msiof-r8a77961", 1208 "renesas,rcar-gen3-msiof"; 1209 reg = <0 0xe6ea0000 0 0x0064>; 1210 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1211 clocks = <&cpg CPG_MOD 210>; 1212 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1213 <&dmac2 0x43>, <&dmac2 0x42>; 1214 dma-names = "tx", "rx", "tx", "rx"; 1215 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1216 resets = <&cpg 210>; 1217 #address-cells = <1>; 1218 #size-cells = <0>; 1219 status = "disabled"; 1220 }; 1221 1222 msiof2: spi@e6c00000 { 1223 compatible = "renesas,msiof-r8a77961", 1224 "renesas,rcar-gen3-msiof"; 1225 reg = <0 0xe6c00000 0 0x0064>; 1226 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1227 clocks = <&cpg CPG_MOD 209>; 1228 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1229 dma-names = "tx", "rx"; 1230 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1231 resets = <&cpg 209>; 1232 #address-cells = <1>; 1233 #size-cells = <0>; 1234 status = "disabled"; 1235 }; 1236 1237 msiof3: spi@e6c10000 { 1238 compatible = "renesas,msiof-r8a77961", 1239 "renesas,rcar-gen3-msiof"; 1240 reg = <0 0xe6c10000 0 0x0064>; 1241 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1242 clocks = <&cpg CPG_MOD 208>; 1243 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1244 dma-names = "tx", "rx"; 1245 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1246 resets = <&cpg 208>; 1247 #address-cells = <1>; 1248 #size-cells = <0>; 1249 status = "disabled"; 1250 }; 1251 1252 vin0: video@e6ef0000 { 1253 reg = <0 0xe6ef0000 0 0x1000>; 1254 /* placeholder */ 1255 }; 1256 1257 vin1: video@e6ef1000 { 1258 reg = <0 0xe6ef1000 0 0x1000>; 1259 /* placeholder */ 1260 }; 1261 1262 vin2: video@e6ef2000 { 1263 reg = <0 0xe6ef2000 0 0x1000>; 1264 /* placeholder */ 1265 }; 1266 1267 vin3: video@e6ef3000 { 1268 reg = <0 0xe6ef3000 0 0x1000>; 1269 /* placeholder */ 1270 }; 1271 1272 vin4: video@e6ef4000 { 1273 reg = <0 0xe6ef4000 0 0x1000>; 1274 /* placeholder */ 1275 }; 1276 1277 vin5: video@e6ef5000 { 1278 reg = <0 0xe6ef5000 0 0x1000>; 1279 /* placeholder */ 1280 }; 1281 1282 vin6: video@e6ef6000 { 1283 reg = <0 0xe6ef6000 0 0x1000>; 1284 /* placeholder */ 1285 }; 1286 1287 vin7: video@e6ef7000 { 1288 reg = <0 0xe6ef7000 0 0x1000>; 1289 /* placeholder */ 1290 }; 1291 1292 rcar_sound: sound@ec500000 { 1293 /* 1294 * #sound-dai-cells is required 1295 * 1296 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1297 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1298 */ 1299 /* 1300 * #clock-cells is required for audio_clkout0/1/2/3 1301 * 1302 * clkout : #clock-cells = <0>; <&rcar_sound>; 1303 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1304 */ 1305 compatible = "renesas,rcar_sound-r8a77961", "renesas,rcar_sound-gen3"; 1306 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1307 <0 0xec5a0000 0 0x100>, /* ADG */ 1308 <0 0xec540000 0 0x1000>, /* SSIU */ 1309 <0 0xec541000 0 0x280>, /* SSI */ 1310 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1311 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1312 1313 clocks = <&cpg CPG_MOD 1005>, 1314 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1315 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1316 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1317 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1318 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1319 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1320 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1321 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1322 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1323 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1324 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1325 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1326 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1327 <&audio_clk_a>, <&audio_clk_b>, 1328 <&audio_clk_c>, 1329 <&cpg CPG_CORE R8A77961_CLK_S0D4>; 1330 clock-names = "ssi-all", 1331 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1332 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1333 "ssi.1", "ssi.0", 1334 "src.9", "src.8", "src.7", "src.6", 1335 "src.5", "src.4", "src.3", "src.2", 1336 "src.1", "src.0", 1337 "mix.1", "mix.0", 1338 "ctu.1", "ctu.0", 1339 "dvc.0", "dvc.1", 1340 "clk_a", "clk_b", "clk_c", "clk_i"; 1341 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1342 resets = <&cpg 1005>, 1343 <&cpg 1006>, <&cpg 1007>, 1344 <&cpg 1008>, <&cpg 1009>, 1345 <&cpg 1010>, <&cpg 1011>, 1346 <&cpg 1012>, <&cpg 1013>, 1347 <&cpg 1014>, <&cpg 1015>; 1348 reset-names = "ssi-all", 1349 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1350 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1351 "ssi.1", "ssi.0"; 1352 status = "disabled"; 1353 1354 rcar_sound,ctu { 1355 ctu00: ctu-0 { }; 1356 ctu01: ctu-1 { }; 1357 ctu02: ctu-2 { }; 1358 ctu03: ctu-3 { }; 1359 ctu10: ctu-4 { }; 1360 ctu11: ctu-5 { }; 1361 ctu12: ctu-6 { }; 1362 ctu13: ctu-7 { }; 1363 }; 1364 1365 rcar_sound,dvc { 1366 dvc0: dvc-0 { 1367 dmas = <&audma1 0xbc>; 1368 dma-names = "tx"; 1369 }; 1370 dvc1: dvc-1 { 1371 dmas = <&audma1 0xbe>; 1372 dma-names = "tx"; 1373 }; 1374 }; 1375 1376 rcar_sound,mix { 1377 mix0: mix-0 { }; 1378 mix1: mix-1 { }; 1379 }; 1380 1381 rcar_sound,src { 1382 src0: src-0 { 1383 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1384 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1385 dma-names = "rx", "tx"; 1386 }; 1387 src1: src-1 { 1388 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1389 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1390 dma-names = "rx", "tx"; 1391 }; 1392 src2: src-2 { 1393 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1394 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1395 dma-names = "rx", "tx"; 1396 }; 1397 src3: src-3 { 1398 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1399 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1400 dma-names = "rx", "tx"; 1401 }; 1402 src4: src-4 { 1403 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1404 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1405 dma-names = "rx", "tx"; 1406 }; 1407 src5: src-5 { 1408 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1409 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1410 dma-names = "rx", "tx"; 1411 }; 1412 src6: src-6 { 1413 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1414 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1415 dma-names = "rx", "tx"; 1416 }; 1417 src7: src-7 { 1418 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1419 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1420 dma-names = "rx", "tx"; 1421 }; 1422 src8: src-8 { 1423 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1424 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1425 dma-names = "rx", "tx"; 1426 }; 1427 src9: src-9 { 1428 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1429 dmas = <&audma0 0x97>, <&audma1 0xba>; 1430 dma-names = "rx", "tx"; 1431 }; 1432 }; 1433 1434 rcar_sound,ssi { 1435 ssi0: ssi-0 { 1436 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1437 dmas = <&audma0 0x01>, <&audma1 0x02>; 1438 dma-names = "rx", "tx"; 1439 }; 1440 ssi1: ssi-1 { 1441 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1442 dmas = <&audma0 0x03>, <&audma1 0x04>; 1443 dma-names = "rx", "tx"; 1444 }; 1445 ssi2: ssi-2 { 1446 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1447 dmas = <&audma0 0x05>, <&audma1 0x06>; 1448 dma-names = "rx", "tx"; 1449 }; 1450 ssi3: ssi-3 { 1451 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1452 dmas = <&audma0 0x07>, <&audma1 0x08>; 1453 dma-names = "rx", "tx"; 1454 }; 1455 ssi4: ssi-4 { 1456 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1457 dmas = <&audma0 0x09>, <&audma1 0x0a>; 1458 dma-names = "rx", "tx"; 1459 }; 1460 ssi5: ssi-5 { 1461 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1462 dmas = <&audma0 0x0b>, <&audma1 0x0c>; 1463 dma-names = "rx", "tx"; 1464 }; 1465 ssi6: ssi-6 { 1466 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1467 dmas = <&audma0 0x0d>, <&audma1 0x0e>; 1468 dma-names = "rx", "tx"; 1469 }; 1470 ssi7: ssi-7 { 1471 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1472 dmas = <&audma0 0x0f>, <&audma1 0x10>; 1473 dma-names = "rx", "tx"; 1474 }; 1475 ssi8: ssi-8 { 1476 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1477 dmas = <&audma0 0x11>, <&audma1 0x12>; 1478 dma-names = "rx", "tx"; 1479 }; 1480 ssi9: ssi-9 { 1481 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1482 dmas = <&audma0 0x13>, <&audma1 0x14>; 1483 dma-names = "rx", "tx"; 1484 }; 1485 }; 1486 1487 rcar_sound,ssiu { 1488 ssiu00: ssiu-0 { 1489 dmas = <&audma0 0x15>, <&audma1 0x16>; 1490 dma-names = "rx", "tx"; 1491 }; 1492 ssiu01: ssiu-1 { 1493 dmas = <&audma0 0x35>, <&audma1 0x36>; 1494 dma-names = "rx", "tx"; 1495 }; 1496 ssiu02: ssiu-2 { 1497 dmas = <&audma0 0x37>, <&audma1 0x38>; 1498 dma-names = "rx", "tx"; 1499 }; 1500 ssiu03: ssiu-3 { 1501 dmas = <&audma0 0x47>, <&audma1 0x48>; 1502 dma-names = "rx", "tx"; 1503 }; 1504 ssiu04: ssiu-4 { 1505 dmas = <&audma0 0x3F>, <&audma1 0x40>; 1506 dma-names = "rx", "tx"; 1507 }; 1508 ssiu05: ssiu-5 { 1509 dmas = <&audma0 0x43>, <&audma1 0x44>; 1510 dma-names = "rx", "tx"; 1511 }; 1512 ssiu06: ssiu-6 { 1513 dmas = <&audma0 0x4F>, <&audma1 0x50>; 1514 dma-names = "rx", "tx"; 1515 }; 1516 ssiu07: ssiu-7 { 1517 dmas = <&audma0 0x53>, <&audma1 0x54>; 1518 dma-names = "rx", "tx"; 1519 }; 1520 ssiu10: ssiu-8 { 1521 dmas = <&audma0 0x49>, <&audma1 0x4a>; 1522 dma-names = "rx", "tx"; 1523 }; 1524 ssiu11: ssiu-9 { 1525 dmas = <&audma0 0x4B>, <&audma1 0x4C>; 1526 dma-names = "rx", "tx"; 1527 }; 1528 ssiu12: ssiu-10 { 1529 dmas = <&audma0 0x57>, <&audma1 0x58>; 1530 dma-names = "rx", "tx"; 1531 }; 1532 ssiu13: ssiu-11 { 1533 dmas = <&audma0 0x59>, <&audma1 0x5A>; 1534 dma-names = "rx", "tx"; 1535 }; 1536 ssiu14: ssiu-12 { 1537 dmas = <&audma0 0x5F>, <&audma1 0x60>; 1538 dma-names = "rx", "tx"; 1539 }; 1540 ssiu15: ssiu-13 { 1541 dmas = <&audma0 0xC3>, <&audma1 0xC4>; 1542 dma-names = "rx", "tx"; 1543 }; 1544 ssiu16: ssiu-14 { 1545 dmas = <&audma0 0xC7>, <&audma1 0xC8>; 1546 dma-names = "rx", "tx"; 1547 }; 1548 ssiu17: ssiu-15 { 1549 dmas = <&audma0 0xCB>, <&audma1 0xCC>; 1550 dma-names = "rx", "tx"; 1551 }; 1552 ssiu20: ssiu-16 { 1553 dmas = <&audma0 0x63>, <&audma1 0x64>; 1554 dma-names = "rx", "tx"; 1555 }; 1556 ssiu21: ssiu-17 { 1557 dmas = <&audma0 0x67>, <&audma1 0x68>; 1558 dma-names = "rx", "tx"; 1559 }; 1560 ssiu22: ssiu-18 { 1561 dmas = <&audma0 0x6B>, <&audma1 0x6C>; 1562 dma-names = "rx", "tx"; 1563 }; 1564 ssiu23: ssiu-19 { 1565 dmas = <&audma0 0x6D>, <&audma1 0x6E>; 1566 dma-names = "rx", "tx"; 1567 }; 1568 ssiu24: ssiu-20 { 1569 dmas = <&audma0 0xCF>, <&audma1 0xCE>; 1570 dma-names = "rx", "tx"; 1571 }; 1572 ssiu25: ssiu-21 { 1573 dmas = <&audma0 0xEB>, <&audma1 0xEC>; 1574 dma-names = "rx", "tx"; 1575 }; 1576 ssiu26: ssiu-22 { 1577 dmas = <&audma0 0xED>, <&audma1 0xEE>; 1578 dma-names = "rx", "tx"; 1579 }; 1580 ssiu27: ssiu-23 { 1581 dmas = <&audma0 0xEF>, <&audma1 0xF0>; 1582 dma-names = "rx", "tx"; 1583 }; 1584 ssiu30: ssiu-24 { 1585 dmas = <&audma0 0x6f>, <&audma1 0x70>; 1586 dma-names = "rx", "tx"; 1587 }; 1588 ssiu31: ssiu-25 { 1589 dmas = <&audma0 0x21>, <&audma1 0x22>; 1590 dma-names = "rx", "tx"; 1591 }; 1592 ssiu32: ssiu-26 { 1593 dmas = <&audma0 0x23>, <&audma1 0x24>; 1594 dma-names = "rx", "tx"; 1595 }; 1596 ssiu33: ssiu-27 { 1597 dmas = <&audma0 0x25>, <&audma1 0x26>; 1598 dma-names = "rx", "tx"; 1599 }; 1600 ssiu34: ssiu-28 { 1601 dmas = <&audma0 0x27>, <&audma1 0x28>; 1602 dma-names = "rx", "tx"; 1603 }; 1604 ssiu35: ssiu-29 { 1605 dmas = <&audma0 0x29>, <&audma1 0x2A>; 1606 dma-names = "rx", "tx"; 1607 }; 1608 ssiu36: ssiu-30 { 1609 dmas = <&audma0 0x2B>, <&audma1 0x2C>; 1610 dma-names = "rx", "tx"; 1611 }; 1612 ssiu37: ssiu-31 { 1613 dmas = <&audma0 0x2D>, <&audma1 0x2E>; 1614 dma-names = "rx", "tx"; 1615 }; 1616 ssiu40: ssiu-32 { 1617 dmas = <&audma0 0x71>, <&audma1 0x72>; 1618 dma-names = "rx", "tx"; 1619 }; 1620 ssiu41: ssiu-33 { 1621 dmas = <&audma0 0x17>, <&audma1 0x18>; 1622 dma-names = "rx", "tx"; 1623 }; 1624 ssiu42: ssiu-34 { 1625 dmas = <&audma0 0x19>, <&audma1 0x1A>; 1626 dma-names = "rx", "tx"; 1627 }; 1628 ssiu43: ssiu-35 { 1629 dmas = <&audma0 0x1B>, <&audma1 0x1C>; 1630 dma-names = "rx", "tx"; 1631 }; 1632 ssiu44: ssiu-36 { 1633 dmas = <&audma0 0x1D>, <&audma1 0x1E>; 1634 dma-names = "rx", "tx"; 1635 }; 1636 ssiu45: ssiu-37 { 1637 dmas = <&audma0 0x1F>, <&audma1 0x20>; 1638 dma-names = "rx", "tx"; 1639 }; 1640 ssiu46: ssiu-38 { 1641 dmas = <&audma0 0x31>, <&audma1 0x32>; 1642 dma-names = "rx", "tx"; 1643 }; 1644 ssiu47: ssiu-39 { 1645 dmas = <&audma0 0x33>, <&audma1 0x34>; 1646 dma-names = "rx", "tx"; 1647 }; 1648 ssiu50: ssiu-40 { 1649 dmas = <&audma0 0x73>, <&audma1 0x74>; 1650 dma-names = "rx", "tx"; 1651 }; 1652 ssiu60: ssiu-41 { 1653 dmas = <&audma0 0x75>, <&audma1 0x76>; 1654 dma-names = "rx", "tx"; 1655 }; 1656 ssiu70: ssiu-42 { 1657 dmas = <&audma0 0x79>, <&audma1 0x7a>; 1658 dma-names = "rx", "tx"; 1659 }; 1660 ssiu80: ssiu-43 { 1661 dmas = <&audma0 0x7b>, <&audma1 0x7c>; 1662 dma-names = "rx", "tx"; 1663 }; 1664 ssiu90: ssiu-44 { 1665 dmas = <&audma0 0x7d>, <&audma1 0x7e>; 1666 dma-names = "rx", "tx"; 1667 }; 1668 ssiu91: ssiu-45 { 1669 dmas = <&audma0 0x7F>, <&audma1 0x80>; 1670 dma-names = "rx", "tx"; 1671 }; 1672 ssiu92: ssiu-46 { 1673 dmas = <&audma0 0x81>, <&audma1 0x82>; 1674 dma-names = "rx", "tx"; 1675 }; 1676 ssiu93: ssiu-47 { 1677 dmas = <&audma0 0x83>, <&audma1 0x84>; 1678 dma-names = "rx", "tx"; 1679 }; 1680 ssiu94: ssiu-48 { 1681 dmas = <&audma0 0xA3>, <&audma1 0xA4>; 1682 dma-names = "rx", "tx"; 1683 }; 1684 ssiu95: ssiu-49 { 1685 dmas = <&audma0 0xA5>, <&audma1 0xA6>; 1686 dma-names = "rx", "tx"; 1687 }; 1688 ssiu96: ssiu-50 { 1689 dmas = <&audma0 0xA7>, <&audma1 0xA8>; 1690 dma-names = "rx", "tx"; 1691 }; 1692 ssiu97: ssiu-51 { 1693 dmas = <&audma0 0xA9>, <&audma1 0xAA>; 1694 dma-names = "rx", "tx"; 1695 }; 1696 }; 1697 }; 1698 1699 audma0: dma-controller@ec700000 { 1700 compatible = "renesas,dmac-r8a77961", 1701 "renesas,rcar-dmac"; 1702 reg = <0 0xec700000 0 0x10000>; 1703 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1704 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1705 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1706 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1707 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1708 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1709 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1710 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1711 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1712 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1713 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1714 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1715 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1716 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1717 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1718 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1719 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1720 interrupt-names = "error", 1721 "ch0", "ch1", "ch2", "ch3", 1722 "ch4", "ch5", "ch6", "ch7", 1723 "ch8", "ch9", "ch10", "ch11", 1724 "ch12", "ch13", "ch14", "ch15"; 1725 clocks = <&cpg CPG_MOD 502>; 1726 clock-names = "fck"; 1727 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1728 resets = <&cpg 502>; 1729 #dma-cells = <1>; 1730 dma-channels = <16>; 1731 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 1732 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 1733 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 1734 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 1735 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 1736 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 1737 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 1738 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 1739 }; 1740 1741 audma1: dma-controller@ec720000 { 1742 compatible = "renesas,dmac-r8a77961", 1743 "renesas,rcar-dmac"; 1744 reg = <0 0xec720000 0 0x10000>; 1745 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 1746 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1747 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1748 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1749 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1750 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1751 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 1762 interrupt-names = "error", 1763 "ch0", "ch1", "ch2", "ch3", 1764 "ch4", "ch5", "ch6", "ch7", 1765 "ch8", "ch9", "ch10", "ch11", 1766 "ch12", "ch13", "ch14", "ch15"; 1767 clocks = <&cpg CPG_MOD 501>; 1768 clock-names = "fck"; 1769 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1770 resets = <&cpg 501>; 1771 #dma-cells = <1>; 1772 dma-channels = <16>; 1773 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, 1774 <&ipmmu_mp 18>, <&ipmmu_mp 19>, 1775 <&ipmmu_mp 20>, <&ipmmu_mp 21>, 1776 <&ipmmu_mp 22>, <&ipmmu_mp 23>, 1777 <&ipmmu_mp 24>, <&ipmmu_mp 25>, 1778 <&ipmmu_mp 26>, <&ipmmu_mp 27>, 1779 <&ipmmu_mp 28>, <&ipmmu_mp 29>, 1780 <&ipmmu_mp 30>, <&ipmmu_mp 31>; 1781 }; 1782 1783 xhci0: usb@ee000000 { 1784 compatible = "renesas,xhci-r8a77961", 1785 "renesas,rcar-gen3-xhci"; 1786 reg = <0 0xee000000 0 0xc00>; 1787 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1788 clocks = <&cpg CPG_MOD 328>; 1789 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1790 resets = <&cpg 328>; 1791 status = "disabled"; 1792 }; 1793 1794 usb3_peri0: usb@ee020000 { 1795 compatible = "renesas,r8a77961-usb3-peri", 1796 "renesas,rcar-gen3-usb3-peri"; 1797 reg = <0 0xee020000 0 0x400>; 1798 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1799 clocks = <&cpg CPG_MOD 328>; 1800 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1801 resets = <&cpg 328>; 1802 status = "disabled"; 1803 }; 1804 1805 ohci0: usb@ee080000 { 1806 compatible = "generic-ohci"; 1807 reg = <0 0xee080000 0 0x100>; 1808 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1809 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1810 phys = <&usb2_phy0 1>; 1811 phy-names = "usb"; 1812 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1813 resets = <&cpg 703>, <&cpg 704>; 1814 status = "disabled"; 1815 }; 1816 1817 ohci1: usb@ee0a0000 { 1818 compatible = "generic-ohci"; 1819 reg = <0 0xee0a0000 0 0x100>; 1820 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1821 clocks = <&cpg CPG_MOD 702>; 1822 phys = <&usb2_phy1 1>; 1823 phy-names = "usb"; 1824 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1825 resets = <&cpg 702>; 1826 status = "disabled"; 1827 }; 1828 1829 ehci0: usb@ee080100 { 1830 compatible = "generic-ehci"; 1831 reg = <0 0xee080100 0 0x100>; 1832 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1833 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1834 phys = <&usb2_phy0 2>; 1835 phy-names = "usb"; 1836 companion = <&ohci0>; 1837 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1838 resets = <&cpg 703>, <&cpg 704>; 1839 status = "disabled"; 1840 }; 1841 1842 ehci1: usb@ee0a0100 { 1843 compatible = "generic-ehci"; 1844 reg = <0 0xee0a0100 0 0x100>; 1845 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1846 clocks = <&cpg CPG_MOD 702>; 1847 phys = <&usb2_phy1 2>; 1848 phy-names = "usb"; 1849 companion = <&ohci1>; 1850 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1851 resets = <&cpg 702>; 1852 status = "disabled"; 1853 }; 1854 1855 usb2_phy0: usb-phy@ee080200 { 1856 compatible = "renesas,usb2-phy-r8a77961", 1857 "renesas,rcar-gen3-usb2-phy"; 1858 reg = <0 0xee080200 0 0x700>; 1859 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1860 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1861 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1862 resets = <&cpg 703>, <&cpg 704>; 1863 #phy-cells = <1>; 1864 status = "disabled"; 1865 }; 1866 1867 usb2_phy1: usb-phy@ee0a0200 { 1868 compatible = "renesas,usb2-phy-r8a77961", 1869 "renesas,rcar-gen3-usb2-phy"; 1870 reg = <0 0xee0a0200 0 0x700>; 1871 clocks = <&cpg CPG_MOD 702>; 1872 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1873 resets = <&cpg 702>; 1874 #phy-cells = <1>; 1875 status = "disabled"; 1876 }; 1877 1878 sdhi0: mmc@ee100000 { 1879 compatible = "renesas,sdhi-r8a77961", 1880 "renesas,rcar-gen3-sdhi"; 1881 reg = <0 0xee100000 0 0x2000>; 1882 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1883 clocks = <&cpg CPG_MOD 314>; 1884 max-frequency = <200000000>; 1885 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1886 resets = <&cpg 314>; 1887 status = "disabled"; 1888 }; 1889 1890 sdhi1: mmc@ee120000 { 1891 compatible = "renesas,sdhi-r8a77961", 1892 "renesas,rcar-gen3-sdhi"; 1893 reg = <0 0xee120000 0 0x2000>; 1894 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1895 clocks = <&cpg CPG_MOD 313>; 1896 max-frequency = <200000000>; 1897 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1898 resets = <&cpg 313>; 1899 status = "disabled"; 1900 }; 1901 1902 sdhi2: mmc@ee140000 { 1903 compatible = "renesas,sdhi-r8a77961", 1904 "renesas,rcar-gen3-sdhi"; 1905 reg = <0 0xee140000 0 0x2000>; 1906 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1907 clocks = <&cpg CPG_MOD 312>; 1908 max-frequency = <200000000>; 1909 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1910 resets = <&cpg 312>; 1911 status = "disabled"; 1912 }; 1913 1914 sdhi3: mmc@ee160000 { 1915 compatible = "renesas,sdhi-r8a77961", 1916 "renesas,rcar-gen3-sdhi"; 1917 reg = <0 0xee160000 0 0x2000>; 1918 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1919 clocks = <&cpg CPG_MOD 311>; 1920 max-frequency = <200000000>; 1921 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1922 resets = <&cpg 311>; 1923 status = "disabled"; 1924 }; 1925 1926 gic: interrupt-controller@f1010000 { 1927 compatible = "arm,gic-400"; 1928 #interrupt-cells = <3>; 1929 #address-cells = <0>; 1930 interrupt-controller; 1931 reg = <0x0 0xf1010000 0 0x1000>, 1932 <0x0 0xf1020000 0 0x20000>, 1933 <0x0 0xf1040000 0 0x20000>, 1934 <0x0 0xf1060000 0 0x20000>; 1935 interrupts = <GIC_PPI 9 1936 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 1937 clocks = <&cpg CPG_MOD 408>; 1938 clock-names = "clk"; 1939 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1940 resets = <&cpg 408>; 1941 }; 1942 1943 pciec0: pcie@fe000000 { 1944 compatible = "renesas,pcie-r8a77961", 1945 "renesas,pcie-rcar-gen3"; 1946 reg = <0 0xfe000000 0 0x80000>; 1947 #address-cells = <3>; 1948 #size-cells = <2>; 1949 bus-range = <0x00 0xff>; 1950 device_type = "pci"; 1951 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 1952 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 1953 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 1954 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 1955 /* Map all possible DDR as inbound ranges */ 1956 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 1957 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1958 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1959 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1960 #interrupt-cells = <1>; 1961 interrupt-map-mask = <0 0 0 0>; 1962 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1963 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 1964 clock-names = "pcie", "pcie_bus"; 1965 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1966 resets = <&cpg 319>; 1967 status = "disabled"; 1968 }; 1969 1970 pciec1: pcie@ee800000 { 1971 compatible = "renesas,pcie-r8a77961", 1972 "renesas,pcie-rcar-gen3"; 1973 reg = <0 0xee800000 0 0x80000>; 1974 #address-cells = <3>; 1975 #size-cells = <2>; 1976 bus-range = <0x00 0xff>; 1977 device_type = "pci"; 1978 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, 1979 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, 1980 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, 1981 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 1982 /* Map all possible DDR as inbound ranges */ 1983 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 1984 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1985 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1986 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1987 #interrupt-cells = <1>; 1988 interrupt-map-mask = <0 0 0 0>; 1989 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1990 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 1991 clock-names = "pcie", "pcie_bus"; 1992 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1993 resets = <&cpg 318>; 1994 status = "disabled"; 1995 }; 1996 1997 fcpf0: fcp@fe950000 { 1998 compatible = "renesas,fcpf"; 1999 reg = <0 0xfe950000 0 0x200>; 2000 clocks = <&cpg CPG_MOD 615>; 2001 power-domains = <&sysc R8A77961_PD_A3VC>; 2002 resets = <&cpg 615>; 2003 }; 2004 2005 fcpvb0: fcp@fe96f000 { 2006 compatible = "renesas,fcpv"; 2007 reg = <0 0xfe96f000 0 0x200>; 2008 clocks = <&cpg CPG_MOD 607>; 2009 power-domains = <&sysc R8A77961_PD_A3VC>; 2010 resets = <&cpg 607>; 2011 }; 2012 2013 fcpvi0: fcp@fe9af000 { 2014 compatible = "renesas,fcpv"; 2015 reg = <0 0xfe9af000 0 0x200>; 2016 clocks = <&cpg CPG_MOD 611>; 2017 power-domains = <&sysc R8A77961_PD_A3VC>; 2018 resets = <&cpg 611>; 2019 iommus = <&ipmmu_vc0 19>; 2020 }; 2021 2022 fcpvd0: fcp@fea27000 { 2023 compatible = "renesas,fcpv"; 2024 reg = <0 0xfea27000 0 0x200>; 2025 clocks = <&cpg CPG_MOD 603>; 2026 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2027 resets = <&cpg 603>; 2028 iommus = <&ipmmu_vi0 8>; 2029 }; 2030 2031 fcpvd1: fcp@fea2f000 { 2032 compatible = "renesas,fcpv"; 2033 reg = <0 0xfea2f000 0 0x200>; 2034 clocks = <&cpg CPG_MOD 602>; 2035 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2036 resets = <&cpg 602>; 2037 iommus = <&ipmmu_vi0 9>; 2038 }; 2039 2040 fcpvd2: fcp@fea37000 { 2041 compatible = "renesas,fcpv"; 2042 reg = <0 0xfea37000 0 0x200>; 2043 clocks = <&cpg CPG_MOD 601>; 2044 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2045 resets = <&cpg 601>; 2046 iommus = <&ipmmu_vi0 10>; 2047 }; 2048 2049 vspb: vsp@fe960000 { 2050 compatible = "renesas,vsp2"; 2051 reg = <0 0xfe960000 0 0x8000>; 2052 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 2053 clocks = <&cpg CPG_MOD 626>; 2054 power-domains = <&sysc R8A77961_PD_A3VC>; 2055 resets = <&cpg 626>; 2056 2057 renesas,fcp = <&fcpvb0>; 2058 }; 2059 2060 vspd0: vsp@fea20000 { 2061 compatible = "renesas,vsp2"; 2062 reg = <0 0xfea20000 0 0x5000>; 2063 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 2064 clocks = <&cpg CPG_MOD 623>; 2065 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2066 resets = <&cpg 623>; 2067 2068 renesas,fcp = <&fcpvd0>; 2069 }; 2070 2071 vspd1: vsp@fea28000 { 2072 compatible = "renesas,vsp2"; 2073 reg = <0 0xfea28000 0 0x5000>; 2074 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 2075 clocks = <&cpg CPG_MOD 622>; 2076 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2077 resets = <&cpg 622>; 2078 2079 renesas,fcp = <&fcpvd1>; 2080 }; 2081 2082 vspd2: vsp@fea30000 { 2083 compatible = "renesas,vsp2"; 2084 reg = <0 0xfea30000 0 0x5000>; 2085 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 2086 clocks = <&cpg CPG_MOD 621>; 2087 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2088 resets = <&cpg 621>; 2089 2090 renesas,fcp = <&fcpvd2>; 2091 }; 2092 2093 vspi0: vsp@fe9a0000 { 2094 compatible = "renesas,vsp2"; 2095 reg = <0 0xfe9a0000 0 0x8000>; 2096 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 2097 clocks = <&cpg CPG_MOD 631>; 2098 power-domains = <&sysc R8A77961_PD_A3VC>; 2099 resets = <&cpg 631>; 2100 2101 renesas,fcp = <&fcpvi0>; 2102 }; 2103 2104 csi20: csi2@fea80000 { 2105 reg = <0 0xfea80000 0 0x10000>; 2106 /* placeholder */ 2107 2108 ports { 2109 #address-cells = <1>; 2110 #size-cells = <0>; 2111 2112 port@1 { 2113 #address-cells = <1>; 2114 #size-cells = <0>; 2115 reg = <1>; 2116 }; 2117 }; 2118 }; 2119 2120 csi40: csi2@feaa0000 { 2121 reg = <0 0xfeaa0000 0 0x10000>; 2122 /* placeholder */ 2123 2124 ports { 2125 #address-cells = <1>; 2126 #size-cells = <0>; 2127 2128 port@1 { 2129 #address-cells = <1>; 2130 #size-cells = <0>; 2131 2132 reg = <1>; 2133 }; 2134 }; 2135 }; 2136 2137 hdmi0: hdmi@fead0000 { 2138 compatible = "renesas,r8a77961-hdmi", "renesas,rcar-gen3-hdmi"; 2139 reg = <0 0xfead0000 0 0x10000>; 2140 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 2141 clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A77961_CLK_HDMI>; 2142 clock-names = "iahb", "isfr"; 2143 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2144 resets = <&cpg 729>; 2145 status = "disabled"; 2146 2147 ports { 2148 #address-cells = <1>; 2149 #size-cells = <0>; 2150 port@0 { 2151 reg = <0>; 2152 dw_hdmi0_in: endpoint { 2153 remote-endpoint = <&du_out_hdmi0>; 2154 }; 2155 }; 2156 port@1 { 2157 reg = <1>; 2158 }; 2159 port@2 { 2160 /* HDMI sound */ 2161 reg = <2>; 2162 }; 2163 }; 2164 }; 2165 2166 du: display@feb00000 { 2167 compatible = "renesas,du-r8a77961"; 2168 reg = <0 0xfeb00000 0 0x70000>; 2169 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2170 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2171 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2172 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, 2173 <&cpg CPG_MOD 722>; 2174 clock-names = "du.0", "du.1", "du.2"; 2175 resets = <&cpg 724>, <&cpg 722>; 2176 reset-names = "du.0", "du.2"; 2177 2178 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; 2179 status = "disabled"; 2180 2181 ports { 2182 #address-cells = <1>; 2183 #size-cells = <0>; 2184 2185 port@0 { 2186 reg = <0>; 2187 du_out_rgb: endpoint { 2188 }; 2189 }; 2190 port@1 { 2191 reg = <1>; 2192 du_out_hdmi0: endpoint { 2193 remote-endpoint = <&dw_hdmi0_in>; 2194 }; 2195 }; 2196 port@2 { 2197 reg = <2>; 2198 du_out_lvds0: endpoint { 2199 }; 2200 }; 2201 }; 2202 }; 2203 2204 prr: chipid@fff00044 { 2205 compatible = "renesas,prr"; 2206 reg = <0 0xfff00044 0 4>; 2207 }; 2208 }; 2209 2210 thermal-zones { 2211 sensor_thermal1: sensor-thermal1 { 2212 polling-delay-passive = <250>; 2213 polling-delay = <1000>; 2214 thermal-sensors = <&tsc 0>; 2215 sustainable-power = <3874>; 2216 2217 trips { 2218 sensor1_crit: sensor1-crit { 2219 temperature = <120000>; 2220 hysteresis = <1000>; 2221 type = "critical"; 2222 }; 2223 }; 2224 }; 2225 2226 sensor_thermal2: sensor-thermal2 { 2227 polling-delay-passive = <250>; 2228 polling-delay = <1000>; 2229 thermal-sensors = <&tsc 1>; 2230 sustainable-power = <3874>; 2231 2232 trips { 2233 sensor2_crit: sensor2-crit { 2234 temperature = <120000>; 2235 hysteresis = <1000>; 2236 type = "critical"; 2237 }; 2238 }; 2239 }; 2240 2241 sensor_thermal3: sensor-thermal3 { 2242 polling-delay-passive = <250>; 2243 polling-delay = <1000>; 2244 thermal-sensors = <&tsc 2>; 2245 sustainable-power = <3874>; 2246 2247 cooling-maps { 2248 map0 { 2249 trip = <&target>; 2250 cooling-device = <&a57_0 2 4>; 2251 contribution = <1024>; 2252 }; 2253 map1 { 2254 trip = <&target>; 2255 cooling-device = <&a53_0 0 2>; 2256 contribution = <1024>; 2257 }; 2258 }; 2259 trips { 2260 target: trip-point1 { 2261 temperature = <100000>; 2262 hysteresis = <1000>; 2263 type = "passive"; 2264 }; 2265 2266 sensor3_crit: sensor3-crit { 2267 temperature = <120000>; 2268 hysteresis = <1000>; 2269 type = "critical"; 2270 }; 2271 }; 2272 }; 2273 }; 2274 2275 timer { 2276 compatible = "arm,armv8-timer"; 2277 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2278 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2279 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2280 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 2281 }; 2282 2283 /* External USB clocks - can be overridden by the board */ 2284 usb3s0_clk: usb3s0 { 2285 compatible = "fixed-clock"; 2286 #clock-cells = <0>; 2287 clock-frequency = <0>; 2288 }; 2289 2290 usb_extal_clk: usb_extal { 2291 compatible = "fixed-clock"; 2292 #clock-cells = <0>; 2293 clock-frequency = <0>; 2294 }; 2295}; 2296