1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC 4 * 5 * Copyright (C) 2016-2017 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a77961-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a77961-sysc.h> 11 12#define CPG_AUDIO_CLK_I R8A77961_CLK_S0D4 13 14/ { 15 compatible = "renesas,r8a77961"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* 20 * The external audio clocks are configured as 0 Hz fixed frequency 21 * clocks by default. 22 * Boards that provide audio clocks should override them. 23 */ 24 audio_clk_a: audio_clk_a { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <0>; 28 }; 29 30 audio_clk_b: audio_clk_b { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <0>; 34 }; 35 36 audio_clk_c: audio_clk_c { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <0>; 40 }; 41 42 /* External CAN clock - to be overridden by boards that provide it */ 43 can_clk: can { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <0>; 47 }; 48 49 cluster0_opp: opp_table0 { 50 compatible = "operating-points-v2"; 51 opp-shared; 52 53 opp-500000000 { 54 opp-hz = /bits/ 64 <500000000>; 55 opp-microvolt = <820000>; 56 clock-latency-ns = <300000>; 57 }; 58 opp-1000000000 { 59 opp-hz = /bits/ 64 <1000000000>; 60 opp-microvolt = <820000>; 61 clock-latency-ns = <300000>; 62 }; 63 opp-1500000000 { 64 opp-hz = /bits/ 64 <1500000000>; 65 opp-microvolt = <820000>; 66 clock-latency-ns = <300000>; 67 }; 68 opp-1600000000 { 69 opp-hz = /bits/ 64 <1600000000>; 70 opp-microvolt = <900000>; 71 clock-latency-ns = <300000>; 72 turbo-mode; 73 }; 74 opp-1700000000 { 75 opp-hz = /bits/ 64 <1700000000>; 76 opp-microvolt = <900000>; 77 clock-latency-ns = <300000>; 78 turbo-mode; 79 }; 80 opp-1800000000 { 81 opp-hz = /bits/ 64 <1800000000>; 82 opp-microvolt = <960000>; 83 clock-latency-ns = <300000>; 84 turbo-mode; 85 }; 86 }; 87 88 cluster1_opp: opp_table1 { 89 compatible = "operating-points-v2"; 90 opp-shared; 91 92 opp-800000000 { 93 opp-hz = /bits/ 64 <800000000>; 94 opp-microvolt = <820000>; 95 clock-latency-ns = <300000>; 96 }; 97 opp-1000000000 { 98 opp-hz = /bits/ 64 <1000000000>; 99 opp-microvolt = <820000>; 100 clock-latency-ns = <300000>; 101 }; 102 opp-1200000000 { 103 opp-hz = /bits/ 64 <1200000000>; 104 opp-microvolt = <820000>; 105 clock-latency-ns = <300000>; 106 }; 107 opp-1300000000 { 108 opp-hz = /bits/ 64 <1300000000>; 109 opp-microvolt = <820000>; 110 clock-latency-ns = <300000>; 111 turbo-mode; 112 }; 113 }; 114 115 cpus { 116 #address-cells = <1>; 117 #size-cells = <0>; 118 119 cpu-map { 120 cluster0 { 121 core0 { 122 cpu = <&a57_0>; 123 }; 124 core1 { 125 cpu = <&a57_1>; 126 }; 127 }; 128 129 cluster1 { 130 core0 { 131 cpu = <&a53_0>; 132 }; 133 core1 { 134 cpu = <&a53_1>; 135 }; 136 core2 { 137 cpu = <&a53_2>; 138 }; 139 core3 { 140 cpu = <&a53_3>; 141 }; 142 }; 143 }; 144 145 a57_0: cpu@0 { 146 compatible = "arm,cortex-a57"; 147 reg = <0x0>; 148 device_type = "cpu"; 149 power-domains = <&sysc R8A77961_PD_CA57_CPU0>; 150 next-level-cache = <&L2_CA57>; 151 enable-method = "psci"; 152 cpu-idle-states = <&CPU_SLEEP_0>; 153 dynamic-power-coefficient = <854>; 154 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; 155 operating-points-v2 = <&cluster0_opp>; 156 capacity-dmips-mhz = <1024>; 157 #cooling-cells = <2>; 158 }; 159 160 a57_1: cpu@1 { 161 compatible = "arm,cortex-a57"; 162 reg = <0x1>; 163 device_type = "cpu"; 164 power-domains = <&sysc R8A77961_PD_CA57_CPU1>; 165 next-level-cache = <&L2_CA57>; 166 enable-method = "psci"; 167 cpu-idle-states = <&CPU_SLEEP_0>; 168 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; 169 operating-points-v2 = <&cluster0_opp>; 170 capacity-dmips-mhz = <1024>; 171 #cooling-cells = <2>; 172 }; 173 174 a53_0: cpu@100 { 175 compatible = "arm,cortex-a53"; 176 reg = <0x100>; 177 device_type = "cpu"; 178 power-domains = <&sysc R8A77961_PD_CA53_CPU0>; 179 next-level-cache = <&L2_CA53>; 180 enable-method = "psci"; 181 cpu-idle-states = <&CPU_SLEEP_1>; 182 #cooling-cells = <2>; 183 dynamic-power-coefficient = <277>; 184 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 185 operating-points-v2 = <&cluster1_opp>; 186 capacity-dmips-mhz = <535>; 187 }; 188 189 a53_1: cpu@101 { 190 compatible = "arm,cortex-a53"; 191 reg = <0x101>; 192 device_type = "cpu"; 193 power-domains = <&sysc R8A77961_PD_CA53_CPU1>; 194 next-level-cache = <&L2_CA53>; 195 enable-method = "psci"; 196 cpu-idle-states = <&CPU_SLEEP_1>; 197 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 198 operating-points-v2 = <&cluster1_opp>; 199 capacity-dmips-mhz = <535>; 200 }; 201 202 a53_2: cpu@102 { 203 compatible = "arm,cortex-a53"; 204 reg = <0x102>; 205 device_type = "cpu"; 206 power-domains = <&sysc R8A77961_PD_CA53_CPU2>; 207 next-level-cache = <&L2_CA53>; 208 enable-method = "psci"; 209 cpu-idle-states = <&CPU_SLEEP_1>; 210 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 211 operating-points-v2 = <&cluster1_opp>; 212 capacity-dmips-mhz = <535>; 213 }; 214 215 a53_3: cpu@103 { 216 compatible = "arm,cortex-a53"; 217 reg = <0x103>; 218 device_type = "cpu"; 219 power-domains = <&sysc R8A77961_PD_CA53_CPU3>; 220 next-level-cache = <&L2_CA53>; 221 enable-method = "psci"; 222 cpu-idle-states = <&CPU_SLEEP_1>; 223 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 224 operating-points-v2 = <&cluster1_opp>; 225 capacity-dmips-mhz = <535>; 226 }; 227 228 L2_CA57: cache-controller-0 { 229 compatible = "cache"; 230 power-domains = <&sysc R8A77961_PD_CA57_SCU>; 231 cache-unified; 232 cache-level = <2>; 233 }; 234 235 L2_CA53: cache-controller-1 { 236 compatible = "cache"; 237 power-domains = <&sysc R8A77961_PD_CA53_SCU>; 238 cache-unified; 239 cache-level = <2>; 240 }; 241 242 idle-states { 243 entry-method = "psci"; 244 245 CPU_SLEEP_0: cpu-sleep-0 { 246 compatible = "arm,idle-state"; 247 arm,psci-suspend-param = <0x0010000>; 248 local-timer-stop; 249 entry-latency-us = <400>; 250 exit-latency-us = <500>; 251 min-residency-us = <4000>; 252 }; 253 254 CPU_SLEEP_1: cpu-sleep-1 { 255 compatible = "arm,idle-state"; 256 arm,psci-suspend-param = <0x0010000>; 257 local-timer-stop; 258 entry-latency-us = <700>; 259 exit-latency-us = <700>; 260 min-residency-us = <5000>; 261 }; 262 }; 263 }; 264 265 extal_clk: extal { 266 compatible = "fixed-clock"; 267 #clock-cells = <0>; 268 /* This value must be overridden by the board */ 269 clock-frequency = <0>; 270 }; 271 272 extalr_clk: extalr { 273 compatible = "fixed-clock"; 274 #clock-cells = <0>; 275 /* This value must be overridden by the board */ 276 clock-frequency = <0>; 277 }; 278 279 /* External PCIe clock - can be overridden by the board */ 280 pcie_bus_clk: pcie_bus { 281 compatible = "fixed-clock"; 282 #clock-cells = <0>; 283 clock-frequency = <0>; 284 }; 285 286 pmu_a53 { 287 compatible = "arm,cortex-a53-pmu"; 288 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 289 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 290 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 291 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 292 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 293 }; 294 295 pmu_a57 { 296 compatible = "arm,cortex-a57-pmu"; 297 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 298 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 299 interrupt-affinity = <&a57_0>, <&a57_1>; 300 }; 301 302 psci { 303 compatible = "arm,psci-1.0", "arm,psci-0.2"; 304 method = "smc"; 305 }; 306 307 /* External SCIF clock - to be overridden by boards that provide it */ 308 scif_clk: scif { 309 compatible = "fixed-clock"; 310 #clock-cells = <0>; 311 clock-frequency = <0>; 312 }; 313 314 soc { 315 compatible = "simple-bus"; 316 interrupt-parent = <&gic>; 317 #address-cells = <2>; 318 #size-cells = <2>; 319 ranges; 320 321 rwdt: watchdog@e6020000 { 322 compatible = "renesas,r8a77961-wdt", 323 "renesas,rcar-gen3-wdt"; 324 reg = <0 0xe6020000 0 0x0c>; 325 clocks = <&cpg CPG_MOD 402>; 326 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 327 resets = <&cpg 402>; 328 status = "disabled"; 329 }; 330 331 gpio0: gpio@e6050000 { 332 compatible = "renesas,gpio-r8a77961", 333 "renesas,rcar-gen3-gpio"; 334 reg = <0 0xe6050000 0 0x50>; 335 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 336 #gpio-cells = <2>; 337 gpio-controller; 338 gpio-ranges = <&pfc 0 0 16>; 339 #interrupt-cells = <2>; 340 interrupt-controller; 341 clocks = <&cpg CPG_MOD 912>; 342 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 343 resets = <&cpg 912>; 344 }; 345 346 gpio1: gpio@e6051000 { 347 compatible = "renesas,gpio-r8a77961", 348 "renesas,rcar-gen3-gpio"; 349 reg = <0 0xe6051000 0 0x50>; 350 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 351 #gpio-cells = <2>; 352 gpio-controller; 353 gpio-ranges = <&pfc 0 32 29>; 354 #interrupt-cells = <2>; 355 interrupt-controller; 356 clocks = <&cpg CPG_MOD 911>; 357 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 358 resets = <&cpg 911>; 359 }; 360 361 gpio2: gpio@e6052000 { 362 compatible = "renesas,gpio-r8a77961", 363 "renesas,rcar-gen3-gpio"; 364 reg = <0 0xe6052000 0 0x50>; 365 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 366 #gpio-cells = <2>; 367 gpio-controller; 368 gpio-ranges = <&pfc 0 64 15>; 369 #interrupt-cells = <2>; 370 interrupt-controller; 371 clocks = <&cpg CPG_MOD 910>; 372 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 373 resets = <&cpg 910>; 374 }; 375 376 gpio3: gpio@e6053000 { 377 compatible = "renesas,gpio-r8a77961", 378 "renesas,rcar-gen3-gpio"; 379 reg = <0 0xe6053000 0 0x50>; 380 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 381 #gpio-cells = <2>; 382 gpio-controller; 383 gpio-ranges = <&pfc 0 96 16>; 384 #interrupt-cells = <2>; 385 interrupt-controller; 386 clocks = <&cpg CPG_MOD 909>; 387 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 388 resets = <&cpg 909>; 389 }; 390 391 gpio4: gpio@e6054000 { 392 compatible = "renesas,gpio-r8a77961", 393 "renesas,rcar-gen3-gpio"; 394 reg = <0 0xe6054000 0 0x50>; 395 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 396 #gpio-cells = <2>; 397 gpio-controller; 398 gpio-ranges = <&pfc 0 128 18>; 399 #interrupt-cells = <2>; 400 interrupt-controller; 401 clocks = <&cpg CPG_MOD 908>; 402 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 403 resets = <&cpg 908>; 404 }; 405 406 gpio5: gpio@e6055000 { 407 compatible = "renesas,gpio-r8a77961", 408 "renesas,rcar-gen3-gpio"; 409 reg = <0 0xe6055000 0 0x50>; 410 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 411 #gpio-cells = <2>; 412 gpio-controller; 413 gpio-ranges = <&pfc 0 160 26>; 414 #interrupt-cells = <2>; 415 interrupt-controller; 416 clocks = <&cpg CPG_MOD 907>; 417 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 418 resets = <&cpg 907>; 419 }; 420 421 gpio6: gpio@e6055400 { 422 compatible = "renesas,gpio-r8a77961", 423 "renesas,rcar-gen3-gpio"; 424 reg = <0 0xe6055400 0 0x50>; 425 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 426 #gpio-cells = <2>; 427 gpio-controller; 428 gpio-ranges = <&pfc 0 192 32>; 429 #interrupt-cells = <2>; 430 interrupt-controller; 431 clocks = <&cpg CPG_MOD 906>; 432 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 433 resets = <&cpg 906>; 434 }; 435 436 gpio7: gpio@e6055800 { 437 compatible = "renesas,gpio-r8a77961", 438 "renesas,rcar-gen3-gpio"; 439 reg = <0 0xe6055800 0 0x50>; 440 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 441 #gpio-cells = <2>; 442 gpio-controller; 443 gpio-ranges = <&pfc 0 224 4>; 444 #interrupt-cells = <2>; 445 interrupt-controller; 446 clocks = <&cpg CPG_MOD 905>; 447 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 448 resets = <&cpg 905>; 449 }; 450 451 pfc: pin-controller@e6060000 { 452 compatible = "renesas,pfc-r8a77961"; 453 reg = <0 0xe6060000 0 0x50c>; 454 }; 455 456 cpg: clock-controller@e6150000 { 457 compatible = "renesas,r8a77961-cpg-mssr"; 458 reg = <0 0xe6150000 0 0x1000>; 459 clocks = <&extal_clk>, <&extalr_clk>; 460 clock-names = "extal", "extalr"; 461 #clock-cells = <2>; 462 #power-domain-cells = <0>; 463 #reset-cells = <1>; 464 }; 465 466 rst: reset-controller@e6160000 { 467 compatible = "renesas,r8a77961-rst"; 468 reg = <0 0xe6160000 0 0x0200>; 469 }; 470 471 sysc: system-controller@e6180000 { 472 compatible = "renesas,r8a77961-sysc"; 473 reg = <0 0xe6180000 0 0x0400>; 474 #power-domain-cells = <1>; 475 }; 476 477 intc_ex: interrupt-controller@e61c0000 { 478 #interrupt-cells = <2>; 479 interrupt-controller; 480 reg = <0 0xe61c0000 0 0x200>; 481 /* placeholder */ 482 }; 483 484 i2c2: i2c@e6510000 { 485 #address-cells = <1>; 486 #size-cells = <0>; 487 reg = <0 0xe6510000 0 0x40>; 488 /* placeholder */ 489 }; 490 491 i2c4: i2c@e66d8000 { 492 #address-cells = <1>; 493 #size-cells = <0>; 494 reg = <0 0xe66d8000 0 0x40>; 495 /* placeholder */ 496 }; 497 498 i2c_dvfs: i2c@e60b0000 { 499 #address-cells = <1>; 500 #size-cells = <0>; 501 reg = <0 0xe60b0000 0 0x425>; 502 /* placeholder */ 503 }; 504 505 hscif1: serial@e6550000 { 506 reg = <0 0xe6550000 0 0x60>; 507 /* placeholder */ 508 }; 509 510 hsusb: usb@e6590000 { 511 reg = <0 0xe6590000 0 0x200>; 512 /* placeholder */ 513 }; 514 515 usb3_phy0: usb-phy@e65ee000 { 516 reg = <0 0xe65ee000 0 0x90>; 517 #phy-cells = <0>; 518 /* placeholder */ 519 }; 520 521 avb: ethernet@e6800000 { 522 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 /* placeholder */ 526 }; 527 528 pwm1: pwm@e6e31000 { 529 reg = <0 0xe6e31000 0 8>; 530 #pwm-cells = <2>; 531 /* placeholder */ 532 }; 533 534 scif1: serial@e6e68000 { 535 reg = <0 0xe6e68000 0 64>; 536 /* placeholder */ 537 }; 538 539 scif2: serial@e6e88000 { 540 compatible = "renesas,scif-r8a77961", 541 "renesas,rcar-gen3-scif", "renesas,scif"; 542 reg = <0 0xe6e88000 0 64>; 543 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 544 clocks = <&cpg CPG_MOD 310>, 545 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 546 <&scif_clk>; 547 clock-names = "fck", "brg_int", "scif_clk"; 548 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 549 resets = <&cpg 310>; 550 status = "disabled"; 551 }; 552 553 vin0: video@e6ef0000 { 554 reg = <0 0xe6ef0000 0 0x1000>; 555 /* placeholder */ 556 }; 557 558 vin1: video@e6ef1000 { 559 reg = <0 0xe6ef1000 0 0x1000>; 560 /* placeholder */ 561 }; 562 563 vin2: video@e6ef2000 { 564 reg = <0 0xe6ef2000 0 0x1000>; 565 /* placeholder */ 566 }; 567 568 vin3: video@e6ef3000 { 569 reg = <0 0xe6ef3000 0 0x1000>; 570 /* placeholder */ 571 }; 572 573 vin4: video@e6ef4000 { 574 reg = <0 0xe6ef4000 0 0x1000>; 575 /* placeholder */ 576 }; 577 578 vin5: video@e6ef5000 { 579 reg = <0 0xe6ef5000 0 0x1000>; 580 /* placeholder */ 581 }; 582 583 vin6: video@e6ef6000 { 584 reg = <0 0xe6ef6000 0 0x1000>; 585 /* placeholder */ 586 }; 587 588 vin7: video@e6ef7000 { 589 reg = <0 0xe6ef7000 0 0x1000>; 590 /* placeholder */ 591 }; 592 593 rcar_sound: sound@ec500000 { 594 reg = <0 0xec500000 0 0x1000>, /* SCU */ 595 <0 0xec5a0000 0 0x100>, /* ADG */ 596 <0 0xec540000 0 0x1000>, /* SSIU */ 597 <0 0xec541000 0 0x280>, /* SSI */ 598 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 599 /* placeholder */ 600 rcar_sound,dvc { 601 dvc0: dvc-0 { }; 602 dvc1: dvc-1 { }; 603 }; 604 605 rcar_sound,src { 606 src0: src-0 { }; 607 src1: src-1 { }; 608 }; 609 610 rcar_sound,ssi { 611 ssi0: ssi-0 { }; 612 ssi1: ssi-1 { }; 613 }; 614 }; 615 616 xhci0: usb@ee000000 { 617 reg = <0 0xee000000 0 0xc00>; 618 /* placeholder */ 619 }; 620 621 usb3_peri0: usb@ee020000 { 622 reg = <0 0xee020000 0 0x400>; 623 /* placeholder */ 624 }; 625 626 ohci0: usb@ee080000 { 627 reg = <0 0xee080000 0 0x100>; 628 /* placeholder */ 629 }; 630 631 ohci1: usb@ee0a0000 { 632 reg = <0 0xee0a0000 0 0x100>; 633 /* placeholder */ 634 }; 635 636 ehci0: usb@ee080100 { 637 reg = <0 0xee080100 0 0x100>; 638 /* placeholder */ 639 }; 640 641 ehci1: usb@ee0a0100 { 642 reg = <0 0xee0a0100 0 0x100>; 643 /* placeholder */ 644 }; 645 646 usb2_phy0: usb-phy@ee080200 { 647 reg = <0 0xee080200 0 0x700>; 648 /* placeholder */ 649 }; 650 651 usb2_phy1: usb-phy@ee0a0200 { 652 reg = <0 0xee0a0200 0 0x700>; 653 /* placeholder */ 654 }; 655 656 sdhi0: sd@ee100000 { 657 reg = <0 0xee100000 0 0x2000>; 658 /* placeholder */ 659 }; 660 661 sdhi2: sd@ee140000 { 662 reg = <0 0xee140000 0 0x2000>; 663 /* placeholder */ 664 }; 665 666 sdhi3: sd@ee160000 { 667 reg = <0 0xee160000 0 0x2000>; 668 /* placeholder */ 669 }; 670 671 gic: interrupt-controller@f1010000 { 672 compatible = "arm,gic-400"; 673 #interrupt-cells = <3>; 674 #address-cells = <0>; 675 interrupt-controller; 676 reg = <0x0 0xf1010000 0 0x1000>, 677 <0x0 0xf1020000 0 0x20000>, 678 <0x0 0xf1040000 0 0x20000>, 679 <0x0 0xf1060000 0 0x20000>; 680 interrupts = <GIC_PPI 9 681 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 682 clocks = <&cpg CPG_MOD 408>; 683 clock-names = "clk"; 684 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 685 resets = <&cpg 408>; 686 }; 687 688 pciec0: pcie@fe000000 { 689 reg = <0 0xfe000000 0 0x80000>; 690 /* placeholder */ 691 }; 692 693 pciec1: pcie@ee800000 { 694 reg = <0 0xee800000 0 0x80000>; 695 /* placeholder */ 696 }; 697 698 csi20: csi2@fea80000 { 699 reg = <0 0xfea80000 0 0x10000>; 700 /* placeholder */ 701 702 ports { 703 #address-cells = <1>; 704 #size-cells = <0>; 705 706 port@1 { 707 #address-cells = <1>; 708 #size-cells = <0>; 709 reg = <1>; 710 }; 711 }; 712 }; 713 714 csi40: csi2@feaa0000 { 715 reg = <0 0xfeaa0000 0 0x10000>; 716 /* placeholder */ 717 718 ports { 719 #address-cells = <1>; 720 #size-cells = <0>; 721 722 port@1 { 723 #address-cells = <1>; 724 #size-cells = <0>; 725 726 reg = <1>; 727 }; 728 }; 729 }; 730 731 hdmi0: hdmi@fead0000 { 732 reg = <0 0xfead0000 0 0x10000>; 733 /* placeholder */ 734 735 ports { 736 #address-cells = <1>; 737 #size-cells = <0>; 738 port@0 { 739 reg = <0>; 740 }; 741 port@1 { 742 reg = <1>; 743 }; 744 port@2 { 745 /* HDMI sound */ 746 reg = <2>; 747 }; 748 }; 749 }; 750 751 du: display@feb00000 { 752 reg = <0 0xfeb00000 0 0x70000>; 753 /* placeholder */ 754 755 ports { 756 #address-cells = <1>; 757 #size-cells = <0>; 758 759 port@0 { 760 reg = <0>; 761 du_out_rgb: endpoint { 762 }; 763 }; 764 port@1 { 765 reg = <1>; 766 du_out_hdmi0: endpoint { 767 }; 768 }; 769 port@2 { 770 reg = <2>; 771 du_out_lvds0: endpoint { 772 }; 773 }; 774 }; 775 }; 776 777 prr: chipid@fff00044 { 778 compatible = "renesas,prr"; 779 reg = <0 0xfff00044 0 4>; 780 }; 781 }; 782 783 timer { 784 compatible = "arm,armv8-timer"; 785 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 786 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 787 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 788 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 789 }; 790 791 /* External USB clocks - can be overridden by the board */ 792 usb3s0_clk: usb3s0 { 793 compatible = "fixed-clock"; 794 #clock-cells = <0>; 795 clock-frequency = <0>; 796 }; 797 798 usb_extal_clk: usb_extal { 799 compatible = "fixed-clock"; 800 #clock-cells = <0>; 801 clock-frequency = <0>; 802 }; 803}; 804