1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC 4 * 5 * Copyright (C) 2016-2017 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a77961-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a77961-sysc.h> 11 12#define CPG_AUDIO_CLK_I R8A77961_CLK_S0D4 13 14/ { 15 compatible = "renesas,r8a77961"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* 20 * The external audio clocks are configured as 0 Hz fixed frequency 21 * clocks by default. 22 * Boards that provide audio clocks should override them. 23 */ 24 audio_clk_a: audio_clk_a { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <0>; 28 }; 29 30 audio_clk_b: audio_clk_b { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <0>; 34 }; 35 36 audio_clk_c: audio_clk_c { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <0>; 40 }; 41 42 /* External CAN clock - to be overridden by boards that provide it */ 43 can_clk: can { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <0>; 47 }; 48 49 cluster0_opp: opp_table0 { 50 compatible = "operating-points-v2"; 51 opp-shared; 52 53 opp-500000000 { 54 opp-hz = /bits/ 64 <500000000>; 55 opp-microvolt = <820000>; 56 clock-latency-ns = <300000>; 57 }; 58 opp-1000000000 { 59 opp-hz = /bits/ 64 <1000000000>; 60 opp-microvolt = <820000>; 61 clock-latency-ns = <300000>; 62 }; 63 opp-1500000000 { 64 opp-hz = /bits/ 64 <1500000000>; 65 opp-microvolt = <820000>; 66 clock-latency-ns = <300000>; 67 }; 68 opp-1600000000 { 69 opp-hz = /bits/ 64 <1600000000>; 70 opp-microvolt = <900000>; 71 clock-latency-ns = <300000>; 72 turbo-mode; 73 }; 74 opp-1700000000 { 75 opp-hz = /bits/ 64 <1700000000>; 76 opp-microvolt = <900000>; 77 clock-latency-ns = <300000>; 78 turbo-mode; 79 }; 80 opp-1800000000 { 81 opp-hz = /bits/ 64 <1800000000>; 82 opp-microvolt = <960000>; 83 clock-latency-ns = <300000>; 84 turbo-mode; 85 }; 86 }; 87 88 cluster1_opp: opp_table1 { 89 compatible = "operating-points-v2"; 90 opp-shared; 91 92 opp-800000000 { 93 opp-hz = /bits/ 64 <800000000>; 94 opp-microvolt = <820000>; 95 clock-latency-ns = <300000>; 96 }; 97 opp-1000000000 { 98 opp-hz = /bits/ 64 <1000000000>; 99 opp-microvolt = <820000>; 100 clock-latency-ns = <300000>; 101 }; 102 opp-1200000000 { 103 opp-hz = /bits/ 64 <1200000000>; 104 opp-microvolt = <820000>; 105 clock-latency-ns = <300000>; 106 }; 107 opp-1300000000 { 108 opp-hz = /bits/ 64 <1300000000>; 109 opp-microvolt = <820000>; 110 clock-latency-ns = <300000>; 111 turbo-mode; 112 }; 113 }; 114 115 cpus { 116 #address-cells = <1>; 117 #size-cells = <0>; 118 119 cpu-map { 120 cluster0 { 121 core0 { 122 cpu = <&a57_0>; 123 }; 124 core1 { 125 cpu = <&a57_1>; 126 }; 127 }; 128 129 cluster1 { 130 core0 { 131 cpu = <&a53_0>; 132 }; 133 core1 { 134 cpu = <&a53_1>; 135 }; 136 core2 { 137 cpu = <&a53_2>; 138 }; 139 core3 { 140 cpu = <&a53_3>; 141 }; 142 }; 143 }; 144 145 a57_0: cpu@0 { 146 compatible = "arm,cortex-a57"; 147 reg = <0x0>; 148 device_type = "cpu"; 149 power-domains = <&sysc R8A77961_PD_CA57_CPU0>; 150 next-level-cache = <&L2_CA57>; 151 enable-method = "psci"; 152 cpu-idle-states = <&CPU_SLEEP_0>; 153 dynamic-power-coefficient = <854>; 154 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; 155 operating-points-v2 = <&cluster0_opp>; 156 capacity-dmips-mhz = <1024>; 157 #cooling-cells = <2>; 158 }; 159 160 a57_1: cpu@1 { 161 compatible = "arm,cortex-a57"; 162 reg = <0x1>; 163 device_type = "cpu"; 164 power-domains = <&sysc R8A77961_PD_CA57_CPU1>; 165 next-level-cache = <&L2_CA57>; 166 enable-method = "psci"; 167 cpu-idle-states = <&CPU_SLEEP_0>; 168 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; 169 operating-points-v2 = <&cluster0_opp>; 170 capacity-dmips-mhz = <1024>; 171 #cooling-cells = <2>; 172 }; 173 174 a53_0: cpu@100 { 175 compatible = "arm,cortex-a53"; 176 reg = <0x100>; 177 device_type = "cpu"; 178 power-domains = <&sysc R8A77961_PD_CA53_CPU0>; 179 next-level-cache = <&L2_CA53>; 180 enable-method = "psci"; 181 cpu-idle-states = <&CPU_SLEEP_1>; 182 #cooling-cells = <2>; 183 dynamic-power-coefficient = <277>; 184 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 185 operating-points-v2 = <&cluster1_opp>; 186 capacity-dmips-mhz = <535>; 187 }; 188 189 a53_1: cpu@101 { 190 compatible = "arm,cortex-a53"; 191 reg = <0x101>; 192 device_type = "cpu"; 193 power-domains = <&sysc R8A77961_PD_CA53_CPU1>; 194 next-level-cache = <&L2_CA53>; 195 enable-method = "psci"; 196 cpu-idle-states = <&CPU_SLEEP_1>; 197 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 198 operating-points-v2 = <&cluster1_opp>; 199 capacity-dmips-mhz = <535>; 200 }; 201 202 a53_2: cpu@102 { 203 compatible = "arm,cortex-a53"; 204 reg = <0x102>; 205 device_type = "cpu"; 206 power-domains = <&sysc R8A77961_PD_CA53_CPU2>; 207 next-level-cache = <&L2_CA53>; 208 enable-method = "psci"; 209 cpu-idle-states = <&CPU_SLEEP_1>; 210 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 211 operating-points-v2 = <&cluster1_opp>; 212 capacity-dmips-mhz = <535>; 213 }; 214 215 a53_3: cpu@103 { 216 compatible = "arm,cortex-a53"; 217 reg = <0x103>; 218 device_type = "cpu"; 219 power-domains = <&sysc R8A77961_PD_CA53_CPU3>; 220 next-level-cache = <&L2_CA53>; 221 enable-method = "psci"; 222 cpu-idle-states = <&CPU_SLEEP_1>; 223 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 224 operating-points-v2 = <&cluster1_opp>; 225 capacity-dmips-mhz = <535>; 226 }; 227 228 L2_CA57: cache-controller-0 { 229 compatible = "cache"; 230 power-domains = <&sysc R8A77961_PD_CA57_SCU>; 231 cache-unified; 232 cache-level = <2>; 233 }; 234 235 L2_CA53: cache-controller-1 { 236 compatible = "cache"; 237 power-domains = <&sysc R8A77961_PD_CA53_SCU>; 238 cache-unified; 239 cache-level = <2>; 240 }; 241 242 idle-states { 243 entry-method = "psci"; 244 245 CPU_SLEEP_0: cpu-sleep-0 { 246 compatible = "arm,idle-state"; 247 arm,psci-suspend-param = <0x0010000>; 248 local-timer-stop; 249 entry-latency-us = <400>; 250 exit-latency-us = <500>; 251 min-residency-us = <4000>; 252 }; 253 254 CPU_SLEEP_1: cpu-sleep-1 { 255 compatible = "arm,idle-state"; 256 arm,psci-suspend-param = <0x0010000>; 257 local-timer-stop; 258 entry-latency-us = <700>; 259 exit-latency-us = <700>; 260 min-residency-us = <5000>; 261 }; 262 }; 263 }; 264 265 extal_clk: extal { 266 compatible = "fixed-clock"; 267 #clock-cells = <0>; 268 /* This value must be overridden by the board */ 269 clock-frequency = <0>; 270 }; 271 272 extalr_clk: extalr { 273 compatible = "fixed-clock"; 274 #clock-cells = <0>; 275 /* This value must be overridden by the board */ 276 clock-frequency = <0>; 277 }; 278 279 /* External PCIe clock - can be overridden by the board */ 280 pcie_bus_clk: pcie_bus { 281 compatible = "fixed-clock"; 282 #clock-cells = <0>; 283 clock-frequency = <0>; 284 }; 285 286 pmu_a53 { 287 compatible = "arm,cortex-a53-pmu"; 288 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 289 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 290 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 291 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 292 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 293 }; 294 295 pmu_a57 { 296 compatible = "arm,cortex-a57-pmu"; 297 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 298 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 299 interrupt-affinity = <&a57_0>, <&a57_1>; 300 }; 301 302 psci { 303 compatible = "arm,psci-1.0", "arm,psci-0.2"; 304 method = "smc"; 305 }; 306 307 /* External SCIF clock - to be overridden by boards that provide it */ 308 scif_clk: scif { 309 compatible = "fixed-clock"; 310 #clock-cells = <0>; 311 clock-frequency = <0>; 312 }; 313 314 soc { 315 compatible = "simple-bus"; 316 interrupt-parent = <&gic>; 317 #address-cells = <2>; 318 #size-cells = <2>; 319 ranges; 320 321 rwdt: watchdog@e6020000 { 322 compatible = "renesas,r8a77961-wdt", 323 "renesas,rcar-gen3-wdt"; 324 reg = <0 0xe6020000 0 0x0c>; 325 clocks = <&cpg CPG_MOD 402>; 326 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 327 resets = <&cpg 402>; 328 status = "disabled"; 329 }; 330 331 gpio0: gpio@e6050000 { 332 compatible = "renesas,gpio-r8a77961", 333 "renesas,rcar-gen3-gpio"; 334 reg = <0 0xe6050000 0 0x50>; 335 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 336 #gpio-cells = <2>; 337 gpio-controller; 338 gpio-ranges = <&pfc 0 0 16>; 339 #interrupt-cells = <2>; 340 interrupt-controller; 341 clocks = <&cpg CPG_MOD 912>; 342 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 343 resets = <&cpg 912>; 344 }; 345 346 gpio1: gpio@e6051000 { 347 compatible = "renesas,gpio-r8a77961", 348 "renesas,rcar-gen3-gpio"; 349 reg = <0 0xe6051000 0 0x50>; 350 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 351 #gpio-cells = <2>; 352 gpio-controller; 353 gpio-ranges = <&pfc 0 32 29>; 354 #interrupt-cells = <2>; 355 interrupt-controller; 356 clocks = <&cpg CPG_MOD 911>; 357 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 358 resets = <&cpg 911>; 359 }; 360 361 gpio2: gpio@e6052000 { 362 compatible = "renesas,gpio-r8a77961", 363 "renesas,rcar-gen3-gpio"; 364 reg = <0 0xe6052000 0 0x50>; 365 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 366 #gpio-cells = <2>; 367 gpio-controller; 368 gpio-ranges = <&pfc 0 64 15>; 369 #interrupt-cells = <2>; 370 interrupt-controller; 371 clocks = <&cpg CPG_MOD 910>; 372 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 373 resets = <&cpg 910>; 374 }; 375 376 gpio3: gpio@e6053000 { 377 compatible = "renesas,gpio-r8a77961", 378 "renesas,rcar-gen3-gpio"; 379 reg = <0 0xe6053000 0 0x50>; 380 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 381 #gpio-cells = <2>; 382 gpio-controller; 383 gpio-ranges = <&pfc 0 96 16>; 384 #interrupt-cells = <2>; 385 interrupt-controller; 386 clocks = <&cpg CPG_MOD 909>; 387 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 388 resets = <&cpg 909>; 389 }; 390 391 gpio4: gpio@e6054000 { 392 compatible = "renesas,gpio-r8a77961", 393 "renesas,rcar-gen3-gpio"; 394 reg = <0 0xe6054000 0 0x50>; 395 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 396 #gpio-cells = <2>; 397 gpio-controller; 398 gpio-ranges = <&pfc 0 128 18>; 399 #interrupt-cells = <2>; 400 interrupt-controller; 401 clocks = <&cpg CPG_MOD 908>; 402 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 403 resets = <&cpg 908>; 404 }; 405 406 gpio5: gpio@e6055000 { 407 compatible = "renesas,gpio-r8a77961", 408 "renesas,rcar-gen3-gpio"; 409 reg = <0 0xe6055000 0 0x50>; 410 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 411 #gpio-cells = <2>; 412 gpio-controller; 413 gpio-ranges = <&pfc 0 160 26>; 414 #interrupt-cells = <2>; 415 interrupt-controller; 416 clocks = <&cpg CPG_MOD 907>; 417 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 418 resets = <&cpg 907>; 419 }; 420 421 gpio6: gpio@e6055400 { 422 compatible = "renesas,gpio-r8a77961", 423 "renesas,rcar-gen3-gpio"; 424 reg = <0 0xe6055400 0 0x50>; 425 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 426 #gpio-cells = <2>; 427 gpio-controller; 428 gpio-ranges = <&pfc 0 192 32>; 429 #interrupt-cells = <2>; 430 interrupt-controller; 431 clocks = <&cpg CPG_MOD 906>; 432 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 433 resets = <&cpg 906>; 434 }; 435 436 gpio7: gpio@e6055800 { 437 compatible = "renesas,gpio-r8a77961", 438 "renesas,rcar-gen3-gpio"; 439 reg = <0 0xe6055800 0 0x50>; 440 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 441 #gpio-cells = <2>; 442 gpio-controller; 443 gpio-ranges = <&pfc 0 224 4>; 444 #interrupt-cells = <2>; 445 interrupt-controller; 446 clocks = <&cpg CPG_MOD 905>; 447 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 448 resets = <&cpg 905>; 449 }; 450 451 pfc: pinctrl@e6060000 { 452 compatible = "renesas,pfc-r8a77961"; 453 reg = <0 0xe6060000 0 0x50c>; 454 }; 455 456 cpg: clock-controller@e6150000 { 457 compatible = "renesas,r8a77961-cpg-mssr"; 458 reg = <0 0xe6150000 0 0x1000>; 459 clocks = <&extal_clk>, <&extalr_clk>; 460 clock-names = "extal", "extalr"; 461 #clock-cells = <2>; 462 #power-domain-cells = <0>; 463 #reset-cells = <1>; 464 }; 465 466 rst: reset-controller@e6160000 { 467 compatible = "renesas,r8a77961-rst"; 468 reg = <0 0xe6160000 0 0x0200>; 469 }; 470 471 sysc: system-controller@e6180000 { 472 compatible = "renesas,r8a77961-sysc"; 473 reg = <0 0xe6180000 0 0x0400>; 474 #power-domain-cells = <1>; 475 }; 476 477 tsc: thermal@e6198000 { 478 compatible = "renesas,r8a77961-thermal"; 479 reg = <0 0xe6198000 0 0x100>, 480 <0 0xe61a0000 0 0x100>, 481 <0 0xe61a8000 0 0x100>; 482 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 485 clocks = <&cpg CPG_MOD 522>; 486 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 487 resets = <&cpg 522>; 488 #thermal-sensor-cells = <1>; 489 }; 490 491 intc_ex: interrupt-controller@e61c0000 { 492 #interrupt-cells = <2>; 493 interrupt-controller; 494 reg = <0 0xe61c0000 0 0x200>; 495 /* placeholder */ 496 }; 497 498 i2c0: i2c@e6500000 { 499 #address-cells = <1>; 500 #size-cells = <0>; 501 compatible = "renesas,i2c-r8a77961", 502 "renesas,rcar-gen3-i2c"; 503 reg = <0 0xe6500000 0 0x40>; 504 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&cpg CPG_MOD 931>; 506 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 507 resets = <&cpg 931>; 508 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 509 <&dmac2 0x91>, <&dmac2 0x90>; 510 dma-names = "tx", "rx", "tx", "rx"; 511 i2c-scl-internal-delay-ns = <110>; 512 status = "disabled"; 513 }; 514 515 i2c1: i2c@e6508000 { 516 #address-cells = <1>; 517 #size-cells = <0>; 518 compatible = "renesas,i2c-r8a77961", 519 "renesas,rcar-gen3-i2c"; 520 reg = <0 0xe6508000 0 0x40>; 521 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&cpg CPG_MOD 930>; 523 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 524 resets = <&cpg 930>; 525 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 526 <&dmac2 0x93>, <&dmac2 0x92>; 527 dma-names = "tx", "rx", "tx", "rx"; 528 i2c-scl-internal-delay-ns = <6>; 529 status = "disabled"; 530 }; 531 532 i2c2: i2c@e6510000 { 533 #address-cells = <1>; 534 #size-cells = <0>; 535 compatible = "renesas,i2c-r8a77961", 536 "renesas,rcar-gen3-i2c"; 537 reg = <0 0xe6510000 0 0x40>; 538 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&cpg CPG_MOD 929>; 540 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 541 resets = <&cpg 929>; 542 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 543 <&dmac2 0x95>, <&dmac2 0x94>; 544 dma-names = "tx", "rx", "tx", "rx"; 545 i2c-scl-internal-delay-ns = <6>; 546 status = "disabled"; 547 }; 548 549 i2c3: i2c@e66d0000 { 550 #address-cells = <1>; 551 #size-cells = <0>; 552 compatible = "renesas,i2c-r8a77961", 553 "renesas,rcar-gen3-i2c"; 554 reg = <0 0xe66d0000 0 0x40>; 555 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&cpg CPG_MOD 928>; 557 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 558 resets = <&cpg 928>; 559 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 560 dma-names = "tx", "rx"; 561 i2c-scl-internal-delay-ns = <110>; 562 status = "disabled"; 563 }; 564 565 i2c4: i2c@e66d8000 { 566 #address-cells = <1>; 567 #size-cells = <0>; 568 compatible = "renesas,i2c-r8a77961", 569 "renesas,rcar-gen3-i2c"; 570 reg = <0 0xe66d8000 0 0x40>; 571 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&cpg CPG_MOD 927>; 573 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 574 resets = <&cpg 927>; 575 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 576 dma-names = "tx", "rx"; 577 i2c-scl-internal-delay-ns = <110>; 578 status = "disabled"; 579 }; 580 581 i2c5: i2c@e66e0000 { 582 #address-cells = <1>; 583 #size-cells = <0>; 584 compatible = "renesas,i2c-r8a77961", 585 "renesas,rcar-gen3-i2c"; 586 reg = <0 0xe66e0000 0 0x40>; 587 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&cpg CPG_MOD 919>; 589 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 590 resets = <&cpg 919>; 591 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 592 dma-names = "tx", "rx"; 593 i2c-scl-internal-delay-ns = <110>; 594 status = "disabled"; 595 }; 596 597 i2c6: i2c@e66e8000 { 598 #address-cells = <1>; 599 #size-cells = <0>; 600 compatible = "renesas,i2c-r8a77961", 601 "renesas,rcar-gen3-i2c"; 602 reg = <0 0xe66e8000 0 0x40>; 603 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&cpg CPG_MOD 918>; 605 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 606 resets = <&cpg 918>; 607 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 608 dma-names = "tx", "rx"; 609 i2c-scl-internal-delay-ns = <6>; 610 status = "disabled"; 611 }; 612 613 i2c_dvfs: i2c@e60b0000 { 614 #address-cells = <1>; 615 #size-cells = <0>; 616 compatible = "renesas,iic-r8a77961", 617 "renesas,rcar-gen3-iic", 618 "renesas,rmobile-iic"; 619 reg = <0 0xe60b0000 0 0x425>; 620 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&cpg CPG_MOD 926>; 622 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 623 resets = <&cpg 926>; 624 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 625 dma-names = "tx", "rx"; 626 status = "disabled"; 627 }; 628 629 hscif0: serial@e6540000 { 630 compatible = "renesas,hscif-r8a77961", 631 "renesas,rcar-gen3-hscif", 632 "renesas,hscif"; 633 reg = <0 0xe6540000 0 0x60>; 634 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 635 clocks = <&cpg CPG_MOD 520>, 636 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 637 <&scif_clk>; 638 clock-names = "fck", "brg_int", "scif_clk"; 639 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 640 <&dmac2 0x31>, <&dmac2 0x30>; 641 dma-names = "tx", "rx", "tx", "rx"; 642 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 643 resets = <&cpg 520>; 644 status = "disabled"; 645 }; 646 647 hscif1: serial@e6550000 { 648 compatible = "renesas,hscif-r8a77961", 649 "renesas,rcar-gen3-hscif", 650 "renesas,hscif"; 651 reg = <0 0xe6550000 0 0x60>; 652 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 653 clocks = <&cpg CPG_MOD 519>, 654 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 655 <&scif_clk>; 656 clock-names = "fck", "brg_int", "scif_clk"; 657 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 658 <&dmac2 0x33>, <&dmac2 0x32>; 659 dma-names = "tx", "rx", "tx", "rx"; 660 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 661 resets = <&cpg 519>; 662 status = "disabled"; 663 }; 664 665 hscif2: serial@e6560000 { 666 compatible = "renesas,hscif-r8a77961", 667 "renesas,rcar-gen3-hscif", 668 "renesas,hscif"; 669 reg = <0 0xe6560000 0 0x60>; 670 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&cpg CPG_MOD 518>, 672 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 673 <&scif_clk>; 674 clock-names = "fck", "brg_int", "scif_clk"; 675 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 676 <&dmac2 0x35>, <&dmac2 0x34>; 677 dma-names = "tx", "rx", "tx", "rx"; 678 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 679 resets = <&cpg 518>; 680 status = "disabled"; 681 }; 682 683 hscif3: serial@e66a0000 { 684 compatible = "renesas,hscif-r8a77961", 685 "renesas,rcar-gen3-hscif", 686 "renesas,hscif"; 687 reg = <0 0xe66a0000 0 0x60>; 688 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&cpg CPG_MOD 517>, 690 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 691 <&scif_clk>; 692 clock-names = "fck", "brg_int", "scif_clk"; 693 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 694 dma-names = "tx", "rx"; 695 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 696 resets = <&cpg 517>; 697 status = "disabled"; 698 }; 699 700 hscif4: serial@e66b0000 { 701 compatible = "renesas,hscif-r8a77961", 702 "renesas,rcar-gen3-hscif", 703 "renesas,hscif"; 704 reg = <0 0xe66b0000 0 0x60>; 705 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 706 clocks = <&cpg CPG_MOD 516>, 707 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 708 <&scif_clk>; 709 clock-names = "fck", "brg_int", "scif_clk"; 710 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 711 dma-names = "tx", "rx"; 712 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 713 resets = <&cpg 516>; 714 status = "disabled"; 715 }; 716 717 hsusb: usb@e6590000 { 718 compatible = "renesas,usbhs-r8a77961", 719 "renesas,rcar-gen3-usbhs"; 720 reg = <0 0xe6590000 0 0x200>; 721 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 723 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 724 <&usb_dmac1 0>, <&usb_dmac1 1>; 725 dma-names = "ch0", "ch1", "ch2", "ch3"; 726 renesas,buswait = <11>; 727 phys = <&usb2_phy0 3>; 728 phy-names = "usb"; 729 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 730 resets = <&cpg 704>, <&cpg 703>; 731 status = "disabled"; 732 }; 733 734 usb_dmac0: dma-controller@e65a0000 { 735 compatible = "renesas,r8a77961-usb-dmac", 736 "renesas,usb-dmac"; 737 reg = <0 0xe65a0000 0 0x100>; 738 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 740 interrupt-names = "ch0", "ch1"; 741 clocks = <&cpg CPG_MOD 330>; 742 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 743 resets = <&cpg 330>; 744 #dma-cells = <1>; 745 dma-channels = <2>; 746 }; 747 748 usb_dmac1: dma-controller@e65b0000 { 749 compatible = "renesas,r8a77961-usb-dmac", 750 "renesas,usb-dmac"; 751 reg = <0 0xe65b0000 0 0x100>; 752 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 754 interrupt-names = "ch0", "ch1"; 755 clocks = <&cpg CPG_MOD 331>; 756 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 757 resets = <&cpg 331>; 758 #dma-cells = <1>; 759 dma-channels = <2>; 760 }; 761 762 usb3_phy0: usb-phy@e65ee000 { 763 compatible = "renesas,r8a77961-usb3-phy", 764 "renesas,rcar-gen3-usb3-phy"; 765 reg = <0 0xe65ee000 0 0x90>; 766 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 767 <&usb_extal_clk>; 768 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 769 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 770 resets = <&cpg 328>; 771 #phy-cells = <0>; 772 status = "disabled"; 773 }; 774 775 arm_cc630p: crypto@e6601000 { 776 compatible = "arm,cryptocell-630p-ree"; 777 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 778 reg = <0x0 0xe6601000 0 0x1000>; 779 clocks = <&cpg CPG_MOD 229>; 780 resets = <&cpg 229>; 781 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 782 }; 783 784 dmac0: dma-controller@e6700000 { 785 compatible = "renesas,dmac-r8a77961", 786 "renesas,rcar-dmac"; 787 reg = <0 0xe6700000 0 0x10000>; 788 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 800 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 805 interrupt-names = "error", 806 "ch0", "ch1", "ch2", "ch3", 807 "ch4", "ch5", "ch6", "ch7", 808 "ch8", "ch9", "ch10", "ch11", 809 "ch12", "ch13", "ch14", "ch15"; 810 clocks = <&cpg CPG_MOD 219>; 811 clock-names = "fck"; 812 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 813 resets = <&cpg 219>; 814 #dma-cells = <1>; 815 dma-channels = <16>; 816 }; 817 818 dmac1: dma-controller@e7300000 { 819 compatible = "renesas,dmac-r8a77961", 820 "renesas,rcar-dmac"; 821 reg = <0 0xe7300000 0 0x10000>; 822 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 828 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 830 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 839 interrupt-names = "error", 840 "ch0", "ch1", "ch2", "ch3", 841 "ch4", "ch5", "ch6", "ch7", 842 "ch8", "ch9", "ch10", "ch11", 843 "ch12", "ch13", "ch14", "ch15"; 844 clocks = <&cpg CPG_MOD 218>; 845 clock-names = "fck"; 846 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 847 resets = <&cpg 218>; 848 #dma-cells = <1>; 849 dma-channels = <16>; 850 }; 851 852 dmac2: dma-controller@e7310000 { 853 compatible = "renesas,dmac-r8a77961", 854 "renesas,rcar-dmac"; 855 reg = <0 0xe7310000 0 0x10000>; 856 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 873 interrupt-names = "error", 874 "ch0", "ch1", "ch2", "ch3", 875 "ch4", "ch5", "ch6", "ch7", 876 "ch8", "ch9", "ch10", "ch11", 877 "ch12", "ch13", "ch14", "ch15"; 878 clocks = <&cpg CPG_MOD 217>; 879 clock-names = "fck"; 880 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 881 resets = <&cpg 217>; 882 #dma-cells = <1>; 883 dma-channels = <16>; 884 }; 885 886 ipmmu_ds0: iommu@e6740000 { 887 compatible = "renesas,ipmmu-r8a77961"; 888 reg = <0 0xe6740000 0 0x1000>; 889 renesas,ipmmu-main = <&ipmmu_mm 0>; 890 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 891 #iommu-cells = <1>; 892 }; 893 894 ipmmu_ds1: iommu@e7740000 { 895 compatible = "renesas,ipmmu-r8a77961"; 896 reg = <0 0xe7740000 0 0x1000>; 897 renesas,ipmmu-main = <&ipmmu_mm 1>; 898 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 899 #iommu-cells = <1>; 900 }; 901 902 ipmmu_hc: iommu@e6570000 { 903 compatible = "renesas,ipmmu-r8a77961"; 904 reg = <0 0xe6570000 0 0x1000>; 905 renesas,ipmmu-main = <&ipmmu_mm 2>; 906 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 907 #iommu-cells = <1>; 908 }; 909 910 ipmmu_ir: iommu@ff8b0000 { 911 compatible = "renesas,ipmmu-r8a77961"; 912 reg = <0 0xff8b0000 0 0x1000>; 913 renesas,ipmmu-main = <&ipmmu_mm 3>; 914 power-domains = <&sysc R8A77961_PD_A3IR>; 915 #iommu-cells = <1>; 916 }; 917 918 ipmmu_mm: iommu@e67b0000 { 919 compatible = "renesas,ipmmu-r8a77961"; 920 reg = <0 0xe67b0000 0 0x1000>; 921 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 923 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 924 #iommu-cells = <1>; 925 }; 926 927 ipmmu_mp: iommu@ec670000 { 928 compatible = "renesas,ipmmu-r8a77961"; 929 reg = <0 0xec670000 0 0x1000>; 930 renesas,ipmmu-main = <&ipmmu_mm 4>; 931 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 932 #iommu-cells = <1>; 933 }; 934 935 ipmmu_pv0: iommu@fd800000 { 936 compatible = "renesas,ipmmu-r8a77961"; 937 reg = <0 0xfd800000 0 0x1000>; 938 renesas,ipmmu-main = <&ipmmu_mm 5>; 939 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 940 #iommu-cells = <1>; 941 }; 942 943 ipmmu_pv1: iommu@fd950000 { 944 compatible = "renesas,ipmmu-r8a77961"; 945 reg = <0 0xfd950000 0 0x1000>; 946 renesas,ipmmu-main = <&ipmmu_mm 6>; 947 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 948 #iommu-cells = <1>; 949 }; 950 951 ipmmu_rt: iommu@ffc80000 { 952 compatible = "renesas,ipmmu-r8a77961"; 953 reg = <0 0xffc80000 0 0x1000>; 954 renesas,ipmmu-main = <&ipmmu_mm 7>; 955 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 956 #iommu-cells = <1>; 957 }; 958 959 ipmmu_vc0: iommu@fe6b0000 { 960 compatible = "renesas,ipmmu-r8a77961"; 961 reg = <0 0xfe6b0000 0 0x1000>; 962 renesas,ipmmu-main = <&ipmmu_mm 8>; 963 power-domains = <&sysc R8A77961_PD_A3VC>; 964 #iommu-cells = <1>; 965 }; 966 967 ipmmu_vi0: iommu@febd0000 { 968 compatible = "renesas,ipmmu-r8a77961"; 969 reg = <0 0xfebd0000 0 0x1000>; 970 renesas,ipmmu-main = <&ipmmu_mm 9>; 971 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 972 #iommu-cells = <1>; 973 }; 974 975 avb: ethernet@e6800000 { 976 compatible = "renesas,etheravb-r8a77961", 977 "renesas,etheravb-rcar-gen3"; 978 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 979 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 981 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 982 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1001 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1002 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1003 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1004 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1005 "ch4", "ch5", "ch6", "ch7", 1006 "ch8", "ch9", "ch10", "ch11", 1007 "ch12", "ch13", "ch14", "ch15", 1008 "ch16", "ch17", "ch18", "ch19", 1009 "ch20", "ch21", "ch22", "ch23", 1010 "ch24"; 1011 clocks = <&cpg CPG_MOD 812>; 1012 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1013 resets = <&cpg 812>; 1014 phy-mode = "rgmii"; 1015 rx-internal-delay-ps = <0>; 1016 tx-internal-delay-ps = <0>; 1017 #address-cells = <1>; 1018 #size-cells = <0>; 1019 status = "disabled"; 1020 }; 1021 1022 can0: can@e6c30000 { 1023 reg = <0 0xe6c30000 0 0x1000>; 1024 /* placeholder */ 1025 }; 1026 1027 can1: can@e6c38000 { 1028 reg = <0 0xe6c38000 0 0x1000>; 1029 /* placeholder */ 1030 }; 1031 1032 pwm0: pwm@e6e30000 { 1033 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1034 reg = <0 0xe6e30000 0 8>; 1035 #pwm-cells = <2>; 1036 clocks = <&cpg CPG_MOD 523>; 1037 resets = <&cpg 523>; 1038 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1039 status = "disabled"; 1040 }; 1041 1042 pwm1: pwm@e6e31000 { 1043 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1044 reg = <0 0xe6e31000 0 8>; 1045 #pwm-cells = <2>; 1046 clocks = <&cpg CPG_MOD 523>; 1047 resets = <&cpg 523>; 1048 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1049 status = "disabled"; 1050 }; 1051 1052 pwm2: pwm@e6e32000 { 1053 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1054 reg = <0 0xe6e32000 0 8>; 1055 #pwm-cells = <2>; 1056 clocks = <&cpg CPG_MOD 523>; 1057 resets = <&cpg 523>; 1058 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1059 status = "disabled"; 1060 }; 1061 1062 pwm3: pwm@e6e33000 { 1063 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1064 reg = <0 0xe6e33000 0 8>; 1065 #pwm-cells = <2>; 1066 clocks = <&cpg CPG_MOD 523>; 1067 resets = <&cpg 523>; 1068 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1069 status = "disabled"; 1070 }; 1071 1072 pwm4: pwm@e6e34000 { 1073 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1074 reg = <0 0xe6e34000 0 8>; 1075 #pwm-cells = <2>; 1076 clocks = <&cpg CPG_MOD 523>; 1077 resets = <&cpg 523>; 1078 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1079 status = "disabled"; 1080 }; 1081 1082 pwm5: pwm@e6e35000 { 1083 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1084 reg = <0 0xe6e35000 0 8>; 1085 #pwm-cells = <2>; 1086 clocks = <&cpg CPG_MOD 523>; 1087 resets = <&cpg 523>; 1088 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1089 status = "disabled"; 1090 }; 1091 1092 pwm6: pwm@e6e36000 { 1093 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1094 reg = <0 0xe6e36000 0 8>; 1095 #pwm-cells = <2>; 1096 clocks = <&cpg CPG_MOD 523>; 1097 resets = <&cpg 523>; 1098 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1099 status = "disabled"; 1100 }; 1101 1102 scif0: serial@e6e60000 { 1103 compatible = "renesas,scif-r8a77961", 1104 "renesas,rcar-gen3-scif", "renesas,scif"; 1105 reg = <0 0xe6e60000 0 64>; 1106 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1107 clocks = <&cpg CPG_MOD 207>, 1108 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1109 <&scif_clk>; 1110 clock-names = "fck", "brg_int", "scif_clk"; 1111 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1112 <&dmac2 0x51>, <&dmac2 0x50>; 1113 dma-names = "tx", "rx", "tx", "rx"; 1114 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1115 resets = <&cpg 207>; 1116 status = "disabled"; 1117 }; 1118 1119 scif1: serial@e6e68000 { 1120 compatible = "renesas,scif-r8a77961", 1121 "renesas,rcar-gen3-scif", "renesas,scif"; 1122 reg = <0 0xe6e68000 0 64>; 1123 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1124 clocks = <&cpg CPG_MOD 206>, 1125 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1126 <&scif_clk>; 1127 clock-names = "fck", "brg_int", "scif_clk"; 1128 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1129 <&dmac2 0x53>, <&dmac2 0x52>; 1130 dma-names = "tx", "rx", "tx", "rx"; 1131 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1132 resets = <&cpg 206>; 1133 status = "disabled"; 1134 }; 1135 1136 scif2: serial@e6e88000 { 1137 compatible = "renesas,scif-r8a77961", 1138 "renesas,rcar-gen3-scif", "renesas,scif"; 1139 reg = <0 0xe6e88000 0 64>; 1140 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1141 clocks = <&cpg CPG_MOD 310>, 1142 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1143 <&scif_clk>; 1144 clock-names = "fck", "brg_int", "scif_clk"; 1145 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1146 <&dmac2 0x13>, <&dmac2 0x12>; 1147 dma-names = "tx", "rx", "tx", "rx"; 1148 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1149 resets = <&cpg 310>; 1150 status = "disabled"; 1151 }; 1152 1153 scif3: serial@e6c50000 { 1154 compatible = "renesas,scif-r8a77961", 1155 "renesas,rcar-gen3-scif", "renesas,scif"; 1156 reg = <0 0xe6c50000 0 64>; 1157 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1158 clocks = <&cpg CPG_MOD 204>, 1159 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1160 <&scif_clk>; 1161 clock-names = "fck", "brg_int", "scif_clk"; 1162 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1163 dma-names = "tx", "rx"; 1164 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1165 resets = <&cpg 204>; 1166 status = "disabled"; 1167 }; 1168 1169 scif4: serial@e6c40000 { 1170 compatible = "renesas,scif-r8a77961", 1171 "renesas,rcar-gen3-scif", "renesas,scif"; 1172 reg = <0 0xe6c40000 0 64>; 1173 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1174 clocks = <&cpg CPG_MOD 203>, 1175 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1176 <&scif_clk>; 1177 clock-names = "fck", "brg_int", "scif_clk"; 1178 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1179 dma-names = "tx", "rx"; 1180 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1181 resets = <&cpg 203>; 1182 status = "disabled"; 1183 }; 1184 1185 scif5: serial@e6f30000 { 1186 compatible = "renesas,scif-r8a77961", 1187 "renesas,rcar-gen3-scif", "renesas,scif"; 1188 reg = <0 0xe6f30000 0 64>; 1189 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1190 clocks = <&cpg CPG_MOD 202>, 1191 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1192 <&scif_clk>; 1193 clock-names = "fck", "brg_int", "scif_clk"; 1194 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1195 <&dmac2 0x5b>, <&dmac2 0x5a>; 1196 dma-names = "tx", "rx", "tx", "rx"; 1197 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1198 resets = <&cpg 202>; 1199 status = "disabled"; 1200 }; 1201 1202 msiof0: spi@e6e90000 { 1203 compatible = "renesas,msiof-r8a77961", 1204 "renesas,rcar-gen3-msiof"; 1205 reg = <0 0xe6e90000 0 0x0064>; 1206 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1207 clocks = <&cpg CPG_MOD 211>; 1208 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1209 <&dmac2 0x41>, <&dmac2 0x40>; 1210 dma-names = "tx", "rx", "tx", "rx"; 1211 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1212 resets = <&cpg 211>; 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 status = "disabled"; 1216 }; 1217 1218 msiof1: spi@e6ea0000 { 1219 compatible = "renesas,msiof-r8a77961", 1220 "renesas,rcar-gen3-msiof"; 1221 reg = <0 0xe6ea0000 0 0x0064>; 1222 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1223 clocks = <&cpg CPG_MOD 210>; 1224 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1225 <&dmac2 0x43>, <&dmac2 0x42>; 1226 dma-names = "tx", "rx", "tx", "rx"; 1227 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1228 resets = <&cpg 210>; 1229 #address-cells = <1>; 1230 #size-cells = <0>; 1231 status = "disabled"; 1232 }; 1233 1234 msiof2: spi@e6c00000 { 1235 compatible = "renesas,msiof-r8a77961", 1236 "renesas,rcar-gen3-msiof"; 1237 reg = <0 0xe6c00000 0 0x0064>; 1238 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1239 clocks = <&cpg CPG_MOD 209>; 1240 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1241 dma-names = "tx", "rx"; 1242 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1243 resets = <&cpg 209>; 1244 #address-cells = <1>; 1245 #size-cells = <0>; 1246 status = "disabled"; 1247 }; 1248 1249 msiof3: spi@e6c10000 { 1250 compatible = "renesas,msiof-r8a77961", 1251 "renesas,rcar-gen3-msiof"; 1252 reg = <0 0xe6c10000 0 0x0064>; 1253 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1254 clocks = <&cpg CPG_MOD 208>; 1255 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1256 dma-names = "tx", "rx"; 1257 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1258 resets = <&cpg 208>; 1259 #address-cells = <1>; 1260 #size-cells = <0>; 1261 status = "disabled"; 1262 }; 1263 1264 vin0: video@e6ef0000 { 1265 reg = <0 0xe6ef0000 0 0x1000>; 1266 /* placeholder */ 1267 }; 1268 1269 vin1: video@e6ef1000 { 1270 reg = <0 0xe6ef1000 0 0x1000>; 1271 /* placeholder */ 1272 }; 1273 1274 vin2: video@e6ef2000 { 1275 reg = <0 0xe6ef2000 0 0x1000>; 1276 /* placeholder */ 1277 }; 1278 1279 vin3: video@e6ef3000 { 1280 reg = <0 0xe6ef3000 0 0x1000>; 1281 /* placeholder */ 1282 }; 1283 1284 vin4: video@e6ef4000 { 1285 reg = <0 0xe6ef4000 0 0x1000>; 1286 /* placeholder */ 1287 }; 1288 1289 vin5: video@e6ef5000 { 1290 reg = <0 0xe6ef5000 0 0x1000>; 1291 /* placeholder */ 1292 }; 1293 1294 vin6: video@e6ef6000 { 1295 reg = <0 0xe6ef6000 0 0x1000>; 1296 /* placeholder */ 1297 }; 1298 1299 vin7: video@e6ef7000 { 1300 reg = <0 0xe6ef7000 0 0x1000>; 1301 /* placeholder */ 1302 }; 1303 1304 rcar_sound: sound@ec500000 { 1305 /* 1306 * #sound-dai-cells is required 1307 * 1308 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1309 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1310 */ 1311 /* 1312 * #clock-cells is required for audio_clkout0/1/2/3 1313 * 1314 * clkout : #clock-cells = <0>; <&rcar_sound>; 1315 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1316 */ 1317 compatible = "renesas,rcar_sound-r8a77961", "renesas,rcar_sound-gen3"; 1318 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1319 <0 0xec5a0000 0 0x100>, /* ADG */ 1320 <0 0xec540000 0 0x1000>, /* SSIU */ 1321 <0 0xec541000 0 0x280>, /* SSI */ 1322 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1323 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1324 1325 clocks = <&cpg CPG_MOD 1005>, 1326 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1327 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1328 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1329 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1330 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1331 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1332 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1333 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1334 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1335 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1336 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1337 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1338 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1339 <&audio_clk_a>, <&audio_clk_b>, 1340 <&audio_clk_c>, 1341 <&cpg CPG_CORE R8A77961_CLK_S0D4>; 1342 clock-names = "ssi-all", 1343 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1344 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1345 "ssi.1", "ssi.0", 1346 "src.9", "src.8", "src.7", "src.6", 1347 "src.5", "src.4", "src.3", "src.2", 1348 "src.1", "src.0", 1349 "mix.1", "mix.0", 1350 "ctu.1", "ctu.0", 1351 "dvc.0", "dvc.1", 1352 "clk_a", "clk_b", "clk_c", "clk_i"; 1353 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1354 resets = <&cpg 1005>, 1355 <&cpg 1006>, <&cpg 1007>, 1356 <&cpg 1008>, <&cpg 1009>, 1357 <&cpg 1010>, <&cpg 1011>, 1358 <&cpg 1012>, <&cpg 1013>, 1359 <&cpg 1014>, <&cpg 1015>; 1360 reset-names = "ssi-all", 1361 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1362 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1363 "ssi.1", "ssi.0"; 1364 status = "disabled"; 1365 1366 rcar_sound,ctu { 1367 ctu00: ctu-0 { }; 1368 ctu01: ctu-1 { }; 1369 ctu02: ctu-2 { }; 1370 ctu03: ctu-3 { }; 1371 ctu10: ctu-4 { }; 1372 ctu11: ctu-5 { }; 1373 ctu12: ctu-6 { }; 1374 ctu13: ctu-7 { }; 1375 }; 1376 1377 rcar_sound,dvc { 1378 dvc0: dvc-0 { 1379 dmas = <&audma1 0xbc>; 1380 dma-names = "tx"; 1381 }; 1382 dvc1: dvc-1 { 1383 dmas = <&audma1 0xbe>; 1384 dma-names = "tx"; 1385 }; 1386 }; 1387 1388 rcar_sound,mix { 1389 mix0: mix-0 { }; 1390 mix1: mix-1 { }; 1391 }; 1392 1393 rcar_sound,src { 1394 src0: src-0 { 1395 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1396 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1397 dma-names = "rx", "tx"; 1398 }; 1399 src1: src-1 { 1400 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1401 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1402 dma-names = "rx", "tx"; 1403 }; 1404 src2: src-2 { 1405 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1406 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1407 dma-names = "rx", "tx"; 1408 }; 1409 src3: src-3 { 1410 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1411 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1412 dma-names = "rx", "tx"; 1413 }; 1414 src4: src-4 { 1415 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1416 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1417 dma-names = "rx", "tx"; 1418 }; 1419 src5: src-5 { 1420 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1421 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1422 dma-names = "rx", "tx"; 1423 }; 1424 src6: src-6 { 1425 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1426 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1427 dma-names = "rx", "tx"; 1428 }; 1429 src7: src-7 { 1430 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1431 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1432 dma-names = "rx", "tx"; 1433 }; 1434 src8: src-8 { 1435 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1436 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1437 dma-names = "rx", "tx"; 1438 }; 1439 src9: src-9 { 1440 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1441 dmas = <&audma0 0x97>, <&audma1 0xba>; 1442 dma-names = "rx", "tx"; 1443 }; 1444 }; 1445 1446 rcar_sound,ssi { 1447 ssi0: ssi-0 { 1448 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1449 dmas = <&audma0 0x01>, <&audma1 0x02>; 1450 dma-names = "rx", "tx"; 1451 }; 1452 ssi1: ssi-1 { 1453 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1454 dmas = <&audma0 0x03>, <&audma1 0x04>; 1455 dma-names = "rx", "tx"; 1456 }; 1457 ssi2: ssi-2 { 1458 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1459 dmas = <&audma0 0x05>, <&audma1 0x06>; 1460 dma-names = "rx", "tx"; 1461 }; 1462 ssi3: ssi-3 { 1463 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1464 dmas = <&audma0 0x07>, <&audma1 0x08>; 1465 dma-names = "rx", "tx"; 1466 }; 1467 ssi4: ssi-4 { 1468 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1469 dmas = <&audma0 0x09>, <&audma1 0x0a>; 1470 dma-names = "rx", "tx"; 1471 }; 1472 ssi5: ssi-5 { 1473 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1474 dmas = <&audma0 0x0b>, <&audma1 0x0c>; 1475 dma-names = "rx", "tx"; 1476 }; 1477 ssi6: ssi-6 { 1478 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1479 dmas = <&audma0 0x0d>, <&audma1 0x0e>; 1480 dma-names = "rx", "tx"; 1481 }; 1482 ssi7: ssi-7 { 1483 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1484 dmas = <&audma0 0x0f>, <&audma1 0x10>; 1485 dma-names = "rx", "tx"; 1486 }; 1487 ssi8: ssi-8 { 1488 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1489 dmas = <&audma0 0x11>, <&audma1 0x12>; 1490 dma-names = "rx", "tx"; 1491 }; 1492 ssi9: ssi-9 { 1493 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1494 dmas = <&audma0 0x13>, <&audma1 0x14>; 1495 dma-names = "rx", "tx"; 1496 }; 1497 }; 1498 1499 rcar_sound,ssiu { 1500 ssiu00: ssiu-0 { 1501 dmas = <&audma0 0x15>, <&audma1 0x16>; 1502 dma-names = "rx", "tx"; 1503 }; 1504 ssiu01: ssiu-1 { 1505 dmas = <&audma0 0x35>, <&audma1 0x36>; 1506 dma-names = "rx", "tx"; 1507 }; 1508 ssiu02: ssiu-2 { 1509 dmas = <&audma0 0x37>, <&audma1 0x38>; 1510 dma-names = "rx", "tx"; 1511 }; 1512 ssiu03: ssiu-3 { 1513 dmas = <&audma0 0x47>, <&audma1 0x48>; 1514 dma-names = "rx", "tx"; 1515 }; 1516 ssiu04: ssiu-4 { 1517 dmas = <&audma0 0x3F>, <&audma1 0x40>; 1518 dma-names = "rx", "tx"; 1519 }; 1520 ssiu05: ssiu-5 { 1521 dmas = <&audma0 0x43>, <&audma1 0x44>; 1522 dma-names = "rx", "tx"; 1523 }; 1524 ssiu06: ssiu-6 { 1525 dmas = <&audma0 0x4F>, <&audma1 0x50>; 1526 dma-names = "rx", "tx"; 1527 }; 1528 ssiu07: ssiu-7 { 1529 dmas = <&audma0 0x53>, <&audma1 0x54>; 1530 dma-names = "rx", "tx"; 1531 }; 1532 ssiu10: ssiu-8 { 1533 dmas = <&audma0 0x49>, <&audma1 0x4a>; 1534 dma-names = "rx", "tx"; 1535 }; 1536 ssiu11: ssiu-9 { 1537 dmas = <&audma0 0x4B>, <&audma1 0x4C>; 1538 dma-names = "rx", "tx"; 1539 }; 1540 ssiu12: ssiu-10 { 1541 dmas = <&audma0 0x57>, <&audma1 0x58>; 1542 dma-names = "rx", "tx"; 1543 }; 1544 ssiu13: ssiu-11 { 1545 dmas = <&audma0 0x59>, <&audma1 0x5A>; 1546 dma-names = "rx", "tx"; 1547 }; 1548 ssiu14: ssiu-12 { 1549 dmas = <&audma0 0x5F>, <&audma1 0x60>; 1550 dma-names = "rx", "tx"; 1551 }; 1552 ssiu15: ssiu-13 { 1553 dmas = <&audma0 0xC3>, <&audma1 0xC4>; 1554 dma-names = "rx", "tx"; 1555 }; 1556 ssiu16: ssiu-14 { 1557 dmas = <&audma0 0xC7>, <&audma1 0xC8>; 1558 dma-names = "rx", "tx"; 1559 }; 1560 ssiu17: ssiu-15 { 1561 dmas = <&audma0 0xCB>, <&audma1 0xCC>; 1562 dma-names = "rx", "tx"; 1563 }; 1564 ssiu20: ssiu-16 { 1565 dmas = <&audma0 0x63>, <&audma1 0x64>; 1566 dma-names = "rx", "tx"; 1567 }; 1568 ssiu21: ssiu-17 { 1569 dmas = <&audma0 0x67>, <&audma1 0x68>; 1570 dma-names = "rx", "tx"; 1571 }; 1572 ssiu22: ssiu-18 { 1573 dmas = <&audma0 0x6B>, <&audma1 0x6C>; 1574 dma-names = "rx", "tx"; 1575 }; 1576 ssiu23: ssiu-19 { 1577 dmas = <&audma0 0x6D>, <&audma1 0x6E>; 1578 dma-names = "rx", "tx"; 1579 }; 1580 ssiu24: ssiu-20 { 1581 dmas = <&audma0 0xCF>, <&audma1 0xCE>; 1582 dma-names = "rx", "tx"; 1583 }; 1584 ssiu25: ssiu-21 { 1585 dmas = <&audma0 0xEB>, <&audma1 0xEC>; 1586 dma-names = "rx", "tx"; 1587 }; 1588 ssiu26: ssiu-22 { 1589 dmas = <&audma0 0xED>, <&audma1 0xEE>; 1590 dma-names = "rx", "tx"; 1591 }; 1592 ssiu27: ssiu-23 { 1593 dmas = <&audma0 0xEF>, <&audma1 0xF0>; 1594 dma-names = "rx", "tx"; 1595 }; 1596 ssiu30: ssiu-24 { 1597 dmas = <&audma0 0x6f>, <&audma1 0x70>; 1598 dma-names = "rx", "tx"; 1599 }; 1600 ssiu31: ssiu-25 { 1601 dmas = <&audma0 0x21>, <&audma1 0x22>; 1602 dma-names = "rx", "tx"; 1603 }; 1604 ssiu32: ssiu-26 { 1605 dmas = <&audma0 0x23>, <&audma1 0x24>; 1606 dma-names = "rx", "tx"; 1607 }; 1608 ssiu33: ssiu-27 { 1609 dmas = <&audma0 0x25>, <&audma1 0x26>; 1610 dma-names = "rx", "tx"; 1611 }; 1612 ssiu34: ssiu-28 { 1613 dmas = <&audma0 0x27>, <&audma1 0x28>; 1614 dma-names = "rx", "tx"; 1615 }; 1616 ssiu35: ssiu-29 { 1617 dmas = <&audma0 0x29>, <&audma1 0x2A>; 1618 dma-names = "rx", "tx"; 1619 }; 1620 ssiu36: ssiu-30 { 1621 dmas = <&audma0 0x2B>, <&audma1 0x2C>; 1622 dma-names = "rx", "tx"; 1623 }; 1624 ssiu37: ssiu-31 { 1625 dmas = <&audma0 0x2D>, <&audma1 0x2E>; 1626 dma-names = "rx", "tx"; 1627 }; 1628 ssiu40: ssiu-32 { 1629 dmas = <&audma0 0x71>, <&audma1 0x72>; 1630 dma-names = "rx", "tx"; 1631 }; 1632 ssiu41: ssiu-33 { 1633 dmas = <&audma0 0x17>, <&audma1 0x18>; 1634 dma-names = "rx", "tx"; 1635 }; 1636 ssiu42: ssiu-34 { 1637 dmas = <&audma0 0x19>, <&audma1 0x1A>; 1638 dma-names = "rx", "tx"; 1639 }; 1640 ssiu43: ssiu-35 { 1641 dmas = <&audma0 0x1B>, <&audma1 0x1C>; 1642 dma-names = "rx", "tx"; 1643 }; 1644 ssiu44: ssiu-36 { 1645 dmas = <&audma0 0x1D>, <&audma1 0x1E>; 1646 dma-names = "rx", "tx"; 1647 }; 1648 ssiu45: ssiu-37 { 1649 dmas = <&audma0 0x1F>, <&audma1 0x20>; 1650 dma-names = "rx", "tx"; 1651 }; 1652 ssiu46: ssiu-38 { 1653 dmas = <&audma0 0x31>, <&audma1 0x32>; 1654 dma-names = "rx", "tx"; 1655 }; 1656 ssiu47: ssiu-39 { 1657 dmas = <&audma0 0x33>, <&audma1 0x34>; 1658 dma-names = "rx", "tx"; 1659 }; 1660 ssiu50: ssiu-40 { 1661 dmas = <&audma0 0x73>, <&audma1 0x74>; 1662 dma-names = "rx", "tx"; 1663 }; 1664 ssiu60: ssiu-41 { 1665 dmas = <&audma0 0x75>, <&audma1 0x76>; 1666 dma-names = "rx", "tx"; 1667 }; 1668 ssiu70: ssiu-42 { 1669 dmas = <&audma0 0x79>, <&audma1 0x7a>; 1670 dma-names = "rx", "tx"; 1671 }; 1672 ssiu80: ssiu-43 { 1673 dmas = <&audma0 0x7b>, <&audma1 0x7c>; 1674 dma-names = "rx", "tx"; 1675 }; 1676 ssiu90: ssiu-44 { 1677 dmas = <&audma0 0x7d>, <&audma1 0x7e>; 1678 dma-names = "rx", "tx"; 1679 }; 1680 ssiu91: ssiu-45 { 1681 dmas = <&audma0 0x7F>, <&audma1 0x80>; 1682 dma-names = "rx", "tx"; 1683 }; 1684 ssiu92: ssiu-46 { 1685 dmas = <&audma0 0x81>, <&audma1 0x82>; 1686 dma-names = "rx", "tx"; 1687 }; 1688 ssiu93: ssiu-47 { 1689 dmas = <&audma0 0x83>, <&audma1 0x84>; 1690 dma-names = "rx", "tx"; 1691 }; 1692 ssiu94: ssiu-48 { 1693 dmas = <&audma0 0xA3>, <&audma1 0xA4>; 1694 dma-names = "rx", "tx"; 1695 }; 1696 ssiu95: ssiu-49 { 1697 dmas = <&audma0 0xA5>, <&audma1 0xA6>; 1698 dma-names = "rx", "tx"; 1699 }; 1700 ssiu96: ssiu-50 { 1701 dmas = <&audma0 0xA7>, <&audma1 0xA8>; 1702 dma-names = "rx", "tx"; 1703 }; 1704 ssiu97: ssiu-51 { 1705 dmas = <&audma0 0xA9>, <&audma1 0xAA>; 1706 dma-names = "rx", "tx"; 1707 }; 1708 }; 1709 }; 1710 1711 audma0: dma-controller@ec700000 { 1712 compatible = "renesas,dmac-r8a77961", 1713 "renesas,rcar-dmac"; 1714 reg = <0 0xec700000 0 0x10000>; 1715 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1716 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1717 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1718 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1719 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1720 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1721 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1722 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1723 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1724 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1727 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1728 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1732 interrupt-names = "error", 1733 "ch0", "ch1", "ch2", "ch3", 1734 "ch4", "ch5", "ch6", "ch7", 1735 "ch8", "ch9", "ch10", "ch11", 1736 "ch12", "ch13", "ch14", "ch15"; 1737 clocks = <&cpg CPG_MOD 502>; 1738 clock-names = "fck"; 1739 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1740 resets = <&cpg 502>; 1741 #dma-cells = <1>; 1742 dma-channels = <16>; 1743 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 1744 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 1745 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 1746 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 1747 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 1748 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 1749 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 1750 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 1751 }; 1752 1753 audma1: dma-controller@ec720000 { 1754 compatible = "renesas,dmac-r8a77961", 1755 "renesas,rcar-dmac"; 1756 reg = <0 0xec720000 0 0x10000>; 1757 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 1774 interrupt-names = "error", 1775 "ch0", "ch1", "ch2", "ch3", 1776 "ch4", "ch5", "ch6", "ch7", 1777 "ch8", "ch9", "ch10", "ch11", 1778 "ch12", "ch13", "ch14", "ch15"; 1779 clocks = <&cpg CPG_MOD 501>; 1780 clock-names = "fck"; 1781 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1782 resets = <&cpg 501>; 1783 #dma-cells = <1>; 1784 dma-channels = <16>; 1785 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, 1786 <&ipmmu_mp 18>, <&ipmmu_mp 19>, 1787 <&ipmmu_mp 20>, <&ipmmu_mp 21>, 1788 <&ipmmu_mp 22>, <&ipmmu_mp 23>, 1789 <&ipmmu_mp 24>, <&ipmmu_mp 25>, 1790 <&ipmmu_mp 26>, <&ipmmu_mp 27>, 1791 <&ipmmu_mp 28>, <&ipmmu_mp 29>, 1792 <&ipmmu_mp 30>, <&ipmmu_mp 31>; 1793 }; 1794 1795 xhci0: usb@ee000000 { 1796 compatible = "renesas,xhci-r8a77961", 1797 "renesas,rcar-gen3-xhci"; 1798 reg = <0 0xee000000 0 0xc00>; 1799 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1800 clocks = <&cpg CPG_MOD 328>; 1801 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1802 resets = <&cpg 328>; 1803 status = "disabled"; 1804 }; 1805 1806 usb3_peri0: usb@ee020000 { 1807 compatible = "renesas,r8a77961-usb3-peri", 1808 "renesas,rcar-gen3-usb3-peri"; 1809 reg = <0 0xee020000 0 0x400>; 1810 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1811 clocks = <&cpg CPG_MOD 328>; 1812 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1813 resets = <&cpg 328>; 1814 status = "disabled"; 1815 }; 1816 1817 ohci0: usb@ee080000 { 1818 compatible = "generic-ohci"; 1819 reg = <0 0xee080000 0 0x100>; 1820 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1821 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1822 phys = <&usb2_phy0 1>; 1823 phy-names = "usb"; 1824 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1825 resets = <&cpg 703>, <&cpg 704>; 1826 status = "disabled"; 1827 }; 1828 1829 ohci1: usb@ee0a0000 { 1830 compatible = "generic-ohci"; 1831 reg = <0 0xee0a0000 0 0x100>; 1832 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1833 clocks = <&cpg CPG_MOD 702>; 1834 phys = <&usb2_phy1 1>; 1835 phy-names = "usb"; 1836 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1837 resets = <&cpg 702>; 1838 status = "disabled"; 1839 }; 1840 1841 ehci0: usb@ee080100 { 1842 compatible = "generic-ehci"; 1843 reg = <0 0xee080100 0 0x100>; 1844 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1845 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1846 phys = <&usb2_phy0 2>; 1847 phy-names = "usb"; 1848 companion = <&ohci0>; 1849 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1850 resets = <&cpg 703>, <&cpg 704>; 1851 status = "disabled"; 1852 }; 1853 1854 ehci1: usb@ee0a0100 { 1855 compatible = "generic-ehci"; 1856 reg = <0 0xee0a0100 0 0x100>; 1857 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1858 clocks = <&cpg CPG_MOD 702>; 1859 phys = <&usb2_phy1 2>; 1860 phy-names = "usb"; 1861 companion = <&ohci1>; 1862 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1863 resets = <&cpg 702>; 1864 status = "disabled"; 1865 }; 1866 1867 usb2_phy0: usb-phy@ee080200 { 1868 compatible = "renesas,usb2-phy-r8a77961", 1869 "renesas,rcar-gen3-usb2-phy"; 1870 reg = <0 0xee080200 0 0x700>; 1871 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1872 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1873 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1874 resets = <&cpg 703>, <&cpg 704>; 1875 #phy-cells = <1>; 1876 status = "disabled"; 1877 }; 1878 1879 usb2_phy1: usb-phy@ee0a0200 { 1880 compatible = "renesas,usb2-phy-r8a77961", 1881 "renesas,rcar-gen3-usb2-phy"; 1882 reg = <0 0xee0a0200 0 0x700>; 1883 clocks = <&cpg CPG_MOD 702>; 1884 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1885 resets = <&cpg 702>; 1886 #phy-cells = <1>; 1887 status = "disabled"; 1888 }; 1889 1890 sdhi0: mmc@ee100000 { 1891 compatible = "renesas,sdhi-r8a77961", 1892 "renesas,rcar-gen3-sdhi"; 1893 reg = <0 0xee100000 0 0x2000>; 1894 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1895 clocks = <&cpg CPG_MOD 314>; 1896 max-frequency = <200000000>; 1897 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1898 resets = <&cpg 314>; 1899 status = "disabled"; 1900 }; 1901 1902 sdhi1: mmc@ee120000 { 1903 compatible = "renesas,sdhi-r8a77961", 1904 "renesas,rcar-gen3-sdhi"; 1905 reg = <0 0xee120000 0 0x2000>; 1906 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1907 clocks = <&cpg CPG_MOD 313>; 1908 max-frequency = <200000000>; 1909 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1910 resets = <&cpg 313>; 1911 status = "disabled"; 1912 }; 1913 1914 sdhi2: mmc@ee140000 { 1915 compatible = "renesas,sdhi-r8a77961", 1916 "renesas,rcar-gen3-sdhi"; 1917 reg = <0 0xee140000 0 0x2000>; 1918 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1919 clocks = <&cpg CPG_MOD 312>; 1920 max-frequency = <200000000>; 1921 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1922 resets = <&cpg 312>; 1923 status = "disabled"; 1924 }; 1925 1926 sdhi3: mmc@ee160000 { 1927 compatible = "renesas,sdhi-r8a77961", 1928 "renesas,rcar-gen3-sdhi"; 1929 reg = <0 0xee160000 0 0x2000>; 1930 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1931 clocks = <&cpg CPG_MOD 311>; 1932 max-frequency = <200000000>; 1933 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1934 resets = <&cpg 311>; 1935 status = "disabled"; 1936 }; 1937 1938 gic: interrupt-controller@f1010000 { 1939 compatible = "arm,gic-400"; 1940 #interrupt-cells = <3>; 1941 #address-cells = <0>; 1942 interrupt-controller; 1943 reg = <0x0 0xf1010000 0 0x1000>, 1944 <0x0 0xf1020000 0 0x20000>, 1945 <0x0 0xf1040000 0 0x20000>, 1946 <0x0 0xf1060000 0 0x20000>; 1947 interrupts = <GIC_PPI 9 1948 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 1949 clocks = <&cpg CPG_MOD 408>; 1950 clock-names = "clk"; 1951 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1952 resets = <&cpg 408>; 1953 }; 1954 1955 pciec0: pcie@fe000000 { 1956 compatible = "renesas,pcie-r8a77961", 1957 "renesas,pcie-rcar-gen3"; 1958 reg = <0 0xfe000000 0 0x80000>; 1959 #address-cells = <3>; 1960 #size-cells = <2>; 1961 bus-range = <0x00 0xff>; 1962 device_type = "pci"; 1963 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 1964 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 1965 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 1966 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 1967 /* Map all possible DDR as inbound ranges */ 1968 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 1969 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1971 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1972 #interrupt-cells = <1>; 1973 interrupt-map-mask = <0 0 0 0>; 1974 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1975 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 1976 clock-names = "pcie", "pcie_bus"; 1977 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1978 resets = <&cpg 319>; 1979 status = "disabled"; 1980 }; 1981 1982 pciec1: pcie@ee800000 { 1983 compatible = "renesas,pcie-r8a77961", 1984 "renesas,pcie-rcar-gen3"; 1985 reg = <0 0xee800000 0 0x80000>; 1986 #address-cells = <3>; 1987 #size-cells = <2>; 1988 bus-range = <0x00 0xff>; 1989 device_type = "pci"; 1990 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, 1991 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, 1992 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, 1993 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 1994 /* Map all possible DDR as inbound ranges */ 1995 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 1996 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1997 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1998 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1999 #interrupt-cells = <1>; 2000 interrupt-map-mask = <0 0 0 0>; 2001 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2002 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 2003 clock-names = "pcie", "pcie_bus"; 2004 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2005 resets = <&cpg 318>; 2006 status = "disabled"; 2007 }; 2008 2009 fcpf0: fcp@fe950000 { 2010 compatible = "renesas,fcpf"; 2011 reg = <0 0xfe950000 0 0x200>; 2012 clocks = <&cpg CPG_MOD 615>; 2013 power-domains = <&sysc R8A77961_PD_A3VC>; 2014 resets = <&cpg 615>; 2015 }; 2016 2017 fcpvb0: fcp@fe96f000 { 2018 compatible = "renesas,fcpv"; 2019 reg = <0 0xfe96f000 0 0x200>; 2020 clocks = <&cpg CPG_MOD 607>; 2021 power-domains = <&sysc R8A77961_PD_A3VC>; 2022 resets = <&cpg 607>; 2023 }; 2024 2025 fcpvi0: fcp@fe9af000 { 2026 compatible = "renesas,fcpv"; 2027 reg = <0 0xfe9af000 0 0x200>; 2028 clocks = <&cpg CPG_MOD 611>; 2029 power-domains = <&sysc R8A77961_PD_A3VC>; 2030 resets = <&cpg 611>; 2031 iommus = <&ipmmu_vc0 19>; 2032 }; 2033 2034 fcpvd0: fcp@fea27000 { 2035 compatible = "renesas,fcpv"; 2036 reg = <0 0xfea27000 0 0x200>; 2037 clocks = <&cpg CPG_MOD 603>; 2038 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2039 resets = <&cpg 603>; 2040 iommus = <&ipmmu_vi0 8>; 2041 }; 2042 2043 fcpvd1: fcp@fea2f000 { 2044 compatible = "renesas,fcpv"; 2045 reg = <0 0xfea2f000 0 0x200>; 2046 clocks = <&cpg CPG_MOD 602>; 2047 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2048 resets = <&cpg 602>; 2049 iommus = <&ipmmu_vi0 9>; 2050 }; 2051 2052 fcpvd2: fcp@fea37000 { 2053 compatible = "renesas,fcpv"; 2054 reg = <0 0xfea37000 0 0x200>; 2055 clocks = <&cpg CPG_MOD 601>; 2056 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2057 resets = <&cpg 601>; 2058 iommus = <&ipmmu_vi0 10>; 2059 }; 2060 2061 vspb: vsp@fe960000 { 2062 compatible = "renesas,vsp2"; 2063 reg = <0 0xfe960000 0 0x8000>; 2064 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 2065 clocks = <&cpg CPG_MOD 626>; 2066 power-domains = <&sysc R8A77961_PD_A3VC>; 2067 resets = <&cpg 626>; 2068 2069 renesas,fcp = <&fcpvb0>; 2070 }; 2071 2072 vspd0: vsp@fea20000 { 2073 compatible = "renesas,vsp2"; 2074 reg = <0 0xfea20000 0 0x5000>; 2075 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 2076 clocks = <&cpg CPG_MOD 623>; 2077 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2078 resets = <&cpg 623>; 2079 2080 renesas,fcp = <&fcpvd0>; 2081 }; 2082 2083 vspd1: vsp@fea28000 { 2084 compatible = "renesas,vsp2"; 2085 reg = <0 0xfea28000 0 0x5000>; 2086 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 2087 clocks = <&cpg CPG_MOD 622>; 2088 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2089 resets = <&cpg 622>; 2090 2091 renesas,fcp = <&fcpvd1>; 2092 }; 2093 2094 vspd2: vsp@fea30000 { 2095 compatible = "renesas,vsp2"; 2096 reg = <0 0xfea30000 0 0x5000>; 2097 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 2098 clocks = <&cpg CPG_MOD 621>; 2099 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2100 resets = <&cpg 621>; 2101 2102 renesas,fcp = <&fcpvd2>; 2103 }; 2104 2105 vspi0: vsp@fe9a0000 { 2106 compatible = "renesas,vsp2"; 2107 reg = <0 0xfe9a0000 0 0x8000>; 2108 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 2109 clocks = <&cpg CPG_MOD 631>; 2110 power-domains = <&sysc R8A77961_PD_A3VC>; 2111 resets = <&cpg 631>; 2112 2113 renesas,fcp = <&fcpvi0>; 2114 }; 2115 2116 csi20: csi2@fea80000 { 2117 reg = <0 0xfea80000 0 0x10000>; 2118 /* placeholder */ 2119 2120 ports { 2121 #address-cells = <1>; 2122 #size-cells = <0>; 2123 2124 port@1 { 2125 #address-cells = <1>; 2126 #size-cells = <0>; 2127 reg = <1>; 2128 }; 2129 }; 2130 }; 2131 2132 csi40: csi2@feaa0000 { 2133 reg = <0 0xfeaa0000 0 0x10000>; 2134 /* placeholder */ 2135 2136 ports { 2137 #address-cells = <1>; 2138 #size-cells = <0>; 2139 2140 port@1 { 2141 #address-cells = <1>; 2142 #size-cells = <0>; 2143 2144 reg = <1>; 2145 }; 2146 }; 2147 }; 2148 2149 hdmi0: hdmi@fead0000 { 2150 compatible = "renesas,r8a77961-hdmi", "renesas,rcar-gen3-hdmi"; 2151 reg = <0 0xfead0000 0 0x10000>; 2152 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 2153 clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A77961_CLK_HDMI>; 2154 clock-names = "iahb", "isfr"; 2155 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2156 resets = <&cpg 729>; 2157 status = "disabled"; 2158 2159 ports { 2160 #address-cells = <1>; 2161 #size-cells = <0>; 2162 port@0 { 2163 reg = <0>; 2164 dw_hdmi0_in: endpoint { 2165 remote-endpoint = <&du_out_hdmi0>; 2166 }; 2167 }; 2168 port@1 { 2169 reg = <1>; 2170 }; 2171 port@2 { 2172 /* HDMI sound */ 2173 reg = <2>; 2174 }; 2175 }; 2176 }; 2177 2178 du: display@feb00000 { 2179 compatible = "renesas,du-r8a77961"; 2180 reg = <0 0xfeb00000 0 0x70000>; 2181 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2182 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2183 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2184 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, 2185 <&cpg CPG_MOD 722>; 2186 clock-names = "du.0", "du.1", "du.2"; 2187 resets = <&cpg 724>, <&cpg 722>; 2188 reset-names = "du.0", "du.2"; 2189 2190 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; 2191 status = "disabled"; 2192 2193 ports { 2194 #address-cells = <1>; 2195 #size-cells = <0>; 2196 2197 port@0 { 2198 reg = <0>; 2199 du_out_rgb: endpoint { 2200 }; 2201 }; 2202 port@1 { 2203 reg = <1>; 2204 du_out_hdmi0: endpoint { 2205 remote-endpoint = <&dw_hdmi0_in>; 2206 }; 2207 }; 2208 port@2 { 2209 reg = <2>; 2210 du_out_lvds0: endpoint { 2211 }; 2212 }; 2213 }; 2214 }; 2215 2216 prr: chipid@fff00044 { 2217 compatible = "renesas,prr"; 2218 reg = <0 0xfff00044 0 4>; 2219 }; 2220 }; 2221 2222 thermal-zones { 2223 sensor_thermal1: sensor-thermal1 { 2224 polling-delay-passive = <250>; 2225 polling-delay = <1000>; 2226 thermal-sensors = <&tsc 0>; 2227 sustainable-power = <3874>; 2228 2229 trips { 2230 sensor1_crit: sensor1-crit { 2231 temperature = <120000>; 2232 hysteresis = <1000>; 2233 type = "critical"; 2234 }; 2235 }; 2236 }; 2237 2238 sensor_thermal2: sensor-thermal2 { 2239 polling-delay-passive = <250>; 2240 polling-delay = <1000>; 2241 thermal-sensors = <&tsc 1>; 2242 sustainable-power = <3874>; 2243 2244 trips { 2245 sensor2_crit: sensor2-crit { 2246 temperature = <120000>; 2247 hysteresis = <1000>; 2248 type = "critical"; 2249 }; 2250 }; 2251 }; 2252 2253 sensor_thermal3: sensor-thermal3 { 2254 polling-delay-passive = <250>; 2255 polling-delay = <1000>; 2256 thermal-sensors = <&tsc 2>; 2257 sustainable-power = <3874>; 2258 2259 cooling-maps { 2260 map0 { 2261 trip = <&target>; 2262 cooling-device = <&a57_0 2 4>; 2263 contribution = <1024>; 2264 }; 2265 map1 { 2266 trip = <&target>; 2267 cooling-device = <&a53_0 0 2>; 2268 contribution = <1024>; 2269 }; 2270 }; 2271 trips { 2272 target: trip-point1 { 2273 temperature = <100000>; 2274 hysteresis = <1000>; 2275 type = "passive"; 2276 }; 2277 2278 sensor3_crit: sensor3-crit { 2279 temperature = <120000>; 2280 hysteresis = <1000>; 2281 type = "critical"; 2282 }; 2283 }; 2284 }; 2285 }; 2286 2287 timer { 2288 compatible = "arm,armv8-timer"; 2289 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2290 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2291 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2292 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 2293 }; 2294 2295 /* External USB clocks - can be overridden by the board */ 2296 usb3s0_clk: usb3s0 { 2297 compatible = "fixed-clock"; 2298 #clock-cells = <0>; 2299 clock-frequency = <0>; 2300 }; 2301 2302 usb_extal_clk: usb_extal { 2303 compatible = "fixed-clock"; 2304 #clock-cells = <0>; 2305 clock-frequency = <0>; 2306 }; 2307}; 2308