1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC 4 * 5 * Copyright (C) 2016-2017 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a77961-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a77961-sysc.h> 11 12#define CPG_AUDIO_CLK_I R8A77961_CLK_S0D4 13 14/ { 15 compatible = "renesas,r8a77961"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* 20 * The external audio clocks are configured as 0 Hz fixed frequency 21 * clocks by default. 22 * Boards that provide audio clocks should override them. 23 */ 24 audio_clk_a: audio_clk_a { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <0>; 28 }; 29 30 audio_clk_b: audio_clk_b { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <0>; 34 }; 35 36 audio_clk_c: audio_clk_c { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <0>; 40 }; 41 42 /* External CAN clock - to be overridden by boards that provide it */ 43 can_clk: can { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <0>; 47 }; 48 49 cluster0_opp: opp-table-0 { 50 compatible = "operating-points-v2"; 51 opp-shared; 52 53 opp-500000000 { 54 opp-hz = /bits/ 64 <500000000>; 55 opp-microvolt = <830000>; 56 clock-latency-ns = <300000>; 57 }; 58 opp-1000000000 { 59 opp-hz = /bits/ 64 <1000000000>; 60 opp-microvolt = <830000>; 61 clock-latency-ns = <300000>; 62 }; 63 opp-1500000000 { 64 opp-hz = /bits/ 64 <1500000000>; 65 opp-microvolt = <830000>; 66 clock-latency-ns = <300000>; 67 opp-suspend; 68 }; 69 opp-1600000000 { 70 opp-hz = /bits/ 64 <1600000000>; 71 opp-microvolt = <900000>; 72 clock-latency-ns = <300000>; 73 turbo-mode; 74 }; 75 opp-1700000000 { 76 opp-hz = /bits/ 64 <1700000000>; 77 opp-microvolt = <900000>; 78 clock-latency-ns = <300000>; 79 turbo-mode; 80 }; 81 opp-1800000000 { 82 opp-hz = /bits/ 64 <1800000000>; 83 opp-microvolt = <960000>; 84 clock-latency-ns = <300000>; 85 turbo-mode; 86 }; 87 }; 88 89 cluster1_opp: opp-table-1 { 90 compatible = "operating-points-v2"; 91 opp-shared; 92 93 opp-800000000 { 94 opp-hz = /bits/ 64 <800000000>; 95 opp-microvolt = <820000>; 96 clock-latency-ns = <300000>; 97 }; 98 opp-1000000000 { 99 opp-hz = /bits/ 64 <1000000000>; 100 opp-microvolt = <820000>; 101 clock-latency-ns = <300000>; 102 }; 103 opp-1200000000 { 104 opp-hz = /bits/ 64 <1200000000>; 105 opp-microvolt = <820000>; 106 clock-latency-ns = <300000>; 107 }; 108 opp-1300000000 { 109 opp-hz = /bits/ 64 <1300000000>; 110 opp-microvolt = <820000>; 111 clock-latency-ns = <300000>; 112 turbo-mode; 113 }; 114 }; 115 116 cpus { 117 #address-cells = <1>; 118 #size-cells = <0>; 119 120 cpu-map { 121 cluster0 { 122 core0 { 123 cpu = <&a57_0>; 124 }; 125 core1 { 126 cpu = <&a57_1>; 127 }; 128 }; 129 130 cluster1 { 131 core0 { 132 cpu = <&a53_0>; 133 }; 134 core1 { 135 cpu = <&a53_1>; 136 }; 137 core2 { 138 cpu = <&a53_2>; 139 }; 140 core3 { 141 cpu = <&a53_3>; 142 }; 143 }; 144 }; 145 146 a57_0: cpu@0 { 147 compatible = "arm,cortex-a57"; 148 reg = <0x0>; 149 device_type = "cpu"; 150 power-domains = <&sysc R8A77961_PD_CA57_CPU0>; 151 next-level-cache = <&L2_CA57>; 152 enable-method = "psci"; 153 cpu-idle-states = <&CPU_SLEEP_0>; 154 dynamic-power-coefficient = <854>; 155 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; 156 operating-points-v2 = <&cluster0_opp>; 157 capacity-dmips-mhz = <1024>; 158 #cooling-cells = <2>; 159 }; 160 161 a57_1: cpu@1 { 162 compatible = "arm,cortex-a57"; 163 reg = <0x1>; 164 device_type = "cpu"; 165 power-domains = <&sysc R8A77961_PD_CA57_CPU1>; 166 next-level-cache = <&L2_CA57>; 167 enable-method = "psci"; 168 cpu-idle-states = <&CPU_SLEEP_0>; 169 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; 170 operating-points-v2 = <&cluster0_opp>; 171 capacity-dmips-mhz = <1024>; 172 #cooling-cells = <2>; 173 }; 174 175 a53_0: cpu@100 { 176 compatible = "arm,cortex-a53"; 177 reg = <0x100>; 178 device_type = "cpu"; 179 power-domains = <&sysc R8A77961_PD_CA53_CPU0>; 180 next-level-cache = <&L2_CA53>; 181 enable-method = "psci"; 182 cpu-idle-states = <&CPU_SLEEP_1>; 183 #cooling-cells = <2>; 184 dynamic-power-coefficient = <277>; 185 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 186 operating-points-v2 = <&cluster1_opp>; 187 capacity-dmips-mhz = <535>; 188 }; 189 190 a53_1: cpu@101 { 191 compatible = "arm,cortex-a53"; 192 reg = <0x101>; 193 device_type = "cpu"; 194 power-domains = <&sysc R8A77961_PD_CA53_CPU1>; 195 next-level-cache = <&L2_CA53>; 196 enable-method = "psci"; 197 cpu-idle-states = <&CPU_SLEEP_1>; 198 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 199 operating-points-v2 = <&cluster1_opp>; 200 capacity-dmips-mhz = <535>; 201 }; 202 203 a53_2: cpu@102 { 204 compatible = "arm,cortex-a53"; 205 reg = <0x102>; 206 device_type = "cpu"; 207 power-domains = <&sysc R8A77961_PD_CA53_CPU2>; 208 next-level-cache = <&L2_CA53>; 209 enable-method = "psci"; 210 cpu-idle-states = <&CPU_SLEEP_1>; 211 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 212 operating-points-v2 = <&cluster1_opp>; 213 capacity-dmips-mhz = <535>; 214 }; 215 216 a53_3: cpu@103 { 217 compatible = "arm,cortex-a53"; 218 reg = <0x103>; 219 device_type = "cpu"; 220 power-domains = <&sysc R8A77961_PD_CA53_CPU3>; 221 next-level-cache = <&L2_CA53>; 222 enable-method = "psci"; 223 cpu-idle-states = <&CPU_SLEEP_1>; 224 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 225 operating-points-v2 = <&cluster1_opp>; 226 capacity-dmips-mhz = <535>; 227 }; 228 229 L2_CA57: cache-controller-0 { 230 compatible = "cache"; 231 power-domains = <&sysc R8A77961_PD_CA57_SCU>; 232 cache-unified; 233 cache-level = <2>; 234 }; 235 236 L2_CA53: cache-controller-1 { 237 compatible = "cache"; 238 power-domains = <&sysc R8A77961_PD_CA53_SCU>; 239 cache-unified; 240 cache-level = <2>; 241 }; 242 243 idle-states { 244 entry-method = "psci"; 245 246 CPU_SLEEP_0: cpu-sleep-0 { 247 compatible = "arm,idle-state"; 248 arm,psci-suspend-param = <0x0010000>; 249 local-timer-stop; 250 entry-latency-us = <400>; 251 exit-latency-us = <500>; 252 min-residency-us = <4000>; 253 }; 254 255 CPU_SLEEP_1: cpu-sleep-1 { 256 compatible = "arm,idle-state"; 257 arm,psci-suspend-param = <0x0010000>; 258 local-timer-stop; 259 entry-latency-us = <700>; 260 exit-latency-us = <700>; 261 min-residency-us = <5000>; 262 }; 263 }; 264 }; 265 266 extal_clk: extal { 267 compatible = "fixed-clock"; 268 #clock-cells = <0>; 269 /* This value must be overridden by the board */ 270 clock-frequency = <0>; 271 }; 272 273 extalr_clk: extalr { 274 compatible = "fixed-clock"; 275 #clock-cells = <0>; 276 /* This value must be overridden by the board */ 277 clock-frequency = <0>; 278 }; 279 280 /* External PCIe clock - can be overridden by the board */ 281 pcie_bus_clk: pcie_bus { 282 compatible = "fixed-clock"; 283 #clock-cells = <0>; 284 clock-frequency = <0>; 285 }; 286 287 pmu_a53 { 288 compatible = "arm,cortex-a53-pmu"; 289 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 290 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 291 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 292 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 293 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 294 }; 295 296 pmu_a57 { 297 compatible = "arm,cortex-a57-pmu"; 298 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 299 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 300 interrupt-affinity = <&a57_0>, <&a57_1>; 301 }; 302 303 psci { 304 compatible = "arm,psci-1.0", "arm,psci-0.2"; 305 method = "smc"; 306 }; 307 308 /* External SCIF clock - to be overridden by boards that provide it */ 309 scif_clk: scif { 310 compatible = "fixed-clock"; 311 #clock-cells = <0>; 312 clock-frequency = <0>; 313 }; 314 315 soc { 316 compatible = "simple-bus"; 317 interrupt-parent = <&gic>; 318 #address-cells = <2>; 319 #size-cells = <2>; 320 ranges; 321 322 rwdt: watchdog@e6020000 { 323 compatible = "renesas,r8a77961-wdt", 324 "renesas,rcar-gen3-wdt"; 325 reg = <0 0xe6020000 0 0x0c>; 326 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&cpg CPG_MOD 402>; 328 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 329 resets = <&cpg 402>; 330 status = "disabled"; 331 }; 332 333 gpio0: gpio@e6050000 { 334 compatible = "renesas,gpio-r8a77961", 335 "renesas,rcar-gen3-gpio"; 336 reg = <0 0xe6050000 0 0x50>; 337 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 338 #gpio-cells = <2>; 339 gpio-controller; 340 gpio-ranges = <&pfc 0 0 16>; 341 #interrupt-cells = <2>; 342 interrupt-controller; 343 clocks = <&cpg CPG_MOD 912>; 344 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 345 resets = <&cpg 912>; 346 }; 347 348 gpio1: gpio@e6051000 { 349 compatible = "renesas,gpio-r8a77961", 350 "renesas,rcar-gen3-gpio"; 351 reg = <0 0xe6051000 0 0x50>; 352 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 353 #gpio-cells = <2>; 354 gpio-controller; 355 gpio-ranges = <&pfc 0 32 29>; 356 #interrupt-cells = <2>; 357 interrupt-controller; 358 clocks = <&cpg CPG_MOD 911>; 359 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 360 resets = <&cpg 911>; 361 }; 362 363 gpio2: gpio@e6052000 { 364 compatible = "renesas,gpio-r8a77961", 365 "renesas,rcar-gen3-gpio"; 366 reg = <0 0xe6052000 0 0x50>; 367 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 368 #gpio-cells = <2>; 369 gpio-controller; 370 gpio-ranges = <&pfc 0 64 15>; 371 #interrupt-cells = <2>; 372 interrupt-controller; 373 clocks = <&cpg CPG_MOD 910>; 374 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 375 resets = <&cpg 910>; 376 }; 377 378 gpio3: gpio@e6053000 { 379 compatible = "renesas,gpio-r8a77961", 380 "renesas,rcar-gen3-gpio"; 381 reg = <0 0xe6053000 0 0x50>; 382 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 383 #gpio-cells = <2>; 384 gpio-controller; 385 gpio-ranges = <&pfc 0 96 16>; 386 #interrupt-cells = <2>; 387 interrupt-controller; 388 clocks = <&cpg CPG_MOD 909>; 389 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 390 resets = <&cpg 909>; 391 }; 392 393 gpio4: gpio@e6054000 { 394 compatible = "renesas,gpio-r8a77961", 395 "renesas,rcar-gen3-gpio"; 396 reg = <0 0xe6054000 0 0x50>; 397 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 398 #gpio-cells = <2>; 399 gpio-controller; 400 gpio-ranges = <&pfc 0 128 18>; 401 #interrupt-cells = <2>; 402 interrupt-controller; 403 clocks = <&cpg CPG_MOD 908>; 404 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 405 resets = <&cpg 908>; 406 }; 407 408 gpio5: gpio@e6055000 { 409 compatible = "renesas,gpio-r8a77961", 410 "renesas,rcar-gen3-gpio"; 411 reg = <0 0xe6055000 0 0x50>; 412 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 413 #gpio-cells = <2>; 414 gpio-controller; 415 gpio-ranges = <&pfc 0 160 26>; 416 #interrupt-cells = <2>; 417 interrupt-controller; 418 clocks = <&cpg CPG_MOD 907>; 419 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 420 resets = <&cpg 907>; 421 }; 422 423 gpio6: gpio@e6055400 { 424 compatible = "renesas,gpio-r8a77961", 425 "renesas,rcar-gen3-gpio"; 426 reg = <0 0xe6055400 0 0x50>; 427 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 428 #gpio-cells = <2>; 429 gpio-controller; 430 gpio-ranges = <&pfc 0 192 32>; 431 #interrupt-cells = <2>; 432 interrupt-controller; 433 clocks = <&cpg CPG_MOD 906>; 434 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 435 resets = <&cpg 906>; 436 }; 437 438 gpio7: gpio@e6055800 { 439 compatible = "renesas,gpio-r8a77961", 440 "renesas,rcar-gen3-gpio"; 441 reg = <0 0xe6055800 0 0x50>; 442 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 443 #gpio-cells = <2>; 444 gpio-controller; 445 gpio-ranges = <&pfc 0 224 4>; 446 #interrupt-cells = <2>; 447 interrupt-controller; 448 clocks = <&cpg CPG_MOD 905>; 449 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 450 resets = <&cpg 905>; 451 }; 452 453 pfc: pinctrl@e6060000 { 454 compatible = "renesas,pfc-r8a77961"; 455 reg = <0 0xe6060000 0 0x50c>; 456 }; 457 458 cmt0: timer@e60f0000 { 459 compatible = "renesas,r8a77961-cmt0", 460 "renesas,rcar-gen3-cmt0"; 461 reg = <0 0xe60f0000 0 0x1004>; 462 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&cpg CPG_MOD 303>; 465 clock-names = "fck"; 466 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 467 resets = <&cpg 303>; 468 status = "disabled"; 469 }; 470 471 cmt1: timer@e6130000 { 472 compatible = "renesas,r8a77961-cmt1", 473 "renesas,rcar-gen3-cmt1"; 474 reg = <0 0xe6130000 0 0x1004>; 475 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 483 clocks = <&cpg CPG_MOD 302>; 484 clock-names = "fck"; 485 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 486 resets = <&cpg 302>; 487 status = "disabled"; 488 }; 489 490 cmt2: timer@e6140000 { 491 compatible = "renesas,r8a77961-cmt1", 492 "renesas,rcar-gen3-cmt1"; 493 reg = <0 0xe6140000 0 0x1004>; 494 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&cpg CPG_MOD 301>; 503 clock-names = "fck"; 504 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 505 resets = <&cpg 301>; 506 status = "disabled"; 507 }; 508 509 cmt3: timer@e6148000 { 510 compatible = "renesas,r8a77961-cmt1", 511 "renesas,rcar-gen3-cmt1"; 512 reg = <0 0xe6148000 0 0x1004>; 513 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&cpg CPG_MOD 300>; 522 clock-names = "fck"; 523 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 524 resets = <&cpg 300>; 525 status = "disabled"; 526 }; 527 528 cpg: clock-controller@e6150000 { 529 compatible = "renesas,r8a77961-cpg-mssr"; 530 reg = <0 0xe6150000 0 0x1000>; 531 clocks = <&extal_clk>, <&extalr_clk>; 532 clock-names = "extal", "extalr"; 533 #clock-cells = <2>; 534 #power-domain-cells = <0>; 535 #reset-cells = <1>; 536 }; 537 538 rst: reset-controller@e6160000 { 539 compatible = "renesas,r8a77961-rst"; 540 reg = <0 0xe6160000 0 0x0200>; 541 }; 542 543 sysc: system-controller@e6180000 { 544 compatible = "renesas,r8a77961-sysc"; 545 reg = <0 0xe6180000 0 0x0400>; 546 #power-domain-cells = <1>; 547 }; 548 549 tsc: thermal@e6198000 { 550 compatible = "renesas,r8a77961-thermal"; 551 reg = <0 0xe6198000 0 0x100>, 552 <0 0xe61a0000 0 0x100>, 553 <0 0xe61a8000 0 0x100>; 554 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&cpg CPG_MOD 522>; 558 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 559 resets = <&cpg 522>; 560 #thermal-sensor-cells = <1>; 561 }; 562 563 intc_ex: interrupt-controller@e61c0000 { 564 compatible = "renesas,intc-ex-r8a77961", "renesas,irqc"; 565 #interrupt-cells = <2>; 566 interrupt-controller; 567 reg = <0 0xe61c0000 0 0x200>; 568 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&cpg CPG_MOD 407>; 575 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 576 resets = <&cpg 407>; 577 }; 578 579 tmu0: timer@e61e0000 { 580 compatible = "renesas,tmu-r8a77961", "renesas,tmu"; 581 reg = <0 0xe61e0000 0 0x30>; 582 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&cpg CPG_MOD 125>; 586 clock-names = "fck"; 587 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 588 resets = <&cpg 125>; 589 status = "disabled"; 590 }; 591 592 tmu1: timer@e6fc0000 { 593 compatible = "renesas,tmu-r8a77961", "renesas,tmu"; 594 reg = <0 0xe6fc0000 0 0x30>; 595 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&cpg CPG_MOD 124>; 599 clock-names = "fck"; 600 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 601 resets = <&cpg 124>; 602 status = "disabled"; 603 }; 604 605 tmu2: timer@e6fd0000 { 606 compatible = "renesas,tmu-r8a77961", "renesas,tmu"; 607 reg = <0 0xe6fd0000 0 0x30>; 608 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&cpg CPG_MOD 123>; 612 clock-names = "fck"; 613 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 614 resets = <&cpg 123>; 615 status = "disabled"; 616 }; 617 618 tmu3: timer@e6fe0000 { 619 compatible = "renesas,tmu-r8a77961", "renesas,tmu"; 620 reg = <0 0xe6fe0000 0 0x30>; 621 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&cpg CPG_MOD 122>; 625 clock-names = "fck"; 626 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 627 resets = <&cpg 122>; 628 status = "disabled"; 629 }; 630 631 tmu4: timer@ffc00000 { 632 compatible = "renesas,tmu-r8a77961", "renesas,tmu"; 633 reg = <0 0xffc00000 0 0x30>; 634 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 637 clocks = <&cpg CPG_MOD 121>; 638 clock-names = "fck"; 639 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 640 resets = <&cpg 121>; 641 status = "disabled"; 642 }; 643 644 i2c0: i2c@e6500000 { 645 #address-cells = <1>; 646 #size-cells = <0>; 647 compatible = "renesas,i2c-r8a77961", 648 "renesas,rcar-gen3-i2c"; 649 reg = <0 0xe6500000 0 0x40>; 650 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&cpg CPG_MOD 931>; 652 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 653 resets = <&cpg 931>; 654 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 655 <&dmac2 0x91>, <&dmac2 0x90>; 656 dma-names = "tx", "rx", "tx", "rx"; 657 i2c-scl-internal-delay-ns = <110>; 658 status = "disabled"; 659 }; 660 661 i2c1: i2c@e6508000 { 662 #address-cells = <1>; 663 #size-cells = <0>; 664 compatible = "renesas,i2c-r8a77961", 665 "renesas,rcar-gen3-i2c"; 666 reg = <0 0xe6508000 0 0x40>; 667 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 668 clocks = <&cpg CPG_MOD 930>; 669 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 670 resets = <&cpg 930>; 671 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 672 <&dmac2 0x93>, <&dmac2 0x92>; 673 dma-names = "tx", "rx", "tx", "rx"; 674 i2c-scl-internal-delay-ns = <6>; 675 status = "disabled"; 676 }; 677 678 i2c2: i2c@e6510000 { 679 #address-cells = <1>; 680 #size-cells = <0>; 681 compatible = "renesas,i2c-r8a77961", 682 "renesas,rcar-gen3-i2c"; 683 reg = <0 0xe6510000 0 0x40>; 684 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&cpg CPG_MOD 929>; 686 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 687 resets = <&cpg 929>; 688 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 689 <&dmac2 0x95>, <&dmac2 0x94>; 690 dma-names = "tx", "rx", "tx", "rx"; 691 i2c-scl-internal-delay-ns = <6>; 692 status = "disabled"; 693 }; 694 695 i2c3: i2c@e66d0000 { 696 #address-cells = <1>; 697 #size-cells = <0>; 698 compatible = "renesas,i2c-r8a77961", 699 "renesas,rcar-gen3-i2c"; 700 reg = <0 0xe66d0000 0 0x40>; 701 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&cpg CPG_MOD 928>; 703 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 704 resets = <&cpg 928>; 705 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 706 dma-names = "tx", "rx"; 707 i2c-scl-internal-delay-ns = <110>; 708 status = "disabled"; 709 }; 710 711 i2c4: i2c@e66d8000 { 712 #address-cells = <1>; 713 #size-cells = <0>; 714 compatible = "renesas,i2c-r8a77961", 715 "renesas,rcar-gen3-i2c"; 716 reg = <0 0xe66d8000 0 0x40>; 717 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 718 clocks = <&cpg CPG_MOD 927>; 719 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 720 resets = <&cpg 927>; 721 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 722 dma-names = "tx", "rx"; 723 i2c-scl-internal-delay-ns = <110>; 724 status = "disabled"; 725 }; 726 727 i2c5: i2c@e66e0000 { 728 #address-cells = <1>; 729 #size-cells = <0>; 730 compatible = "renesas,i2c-r8a77961", 731 "renesas,rcar-gen3-i2c"; 732 reg = <0 0xe66e0000 0 0x40>; 733 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 734 clocks = <&cpg CPG_MOD 919>; 735 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 736 resets = <&cpg 919>; 737 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 738 dma-names = "tx", "rx"; 739 i2c-scl-internal-delay-ns = <110>; 740 status = "disabled"; 741 }; 742 743 i2c6: i2c@e66e8000 { 744 #address-cells = <1>; 745 #size-cells = <0>; 746 compatible = "renesas,i2c-r8a77961", 747 "renesas,rcar-gen3-i2c"; 748 reg = <0 0xe66e8000 0 0x40>; 749 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 750 clocks = <&cpg CPG_MOD 918>; 751 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 752 resets = <&cpg 918>; 753 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 754 dma-names = "tx", "rx"; 755 i2c-scl-internal-delay-ns = <6>; 756 status = "disabled"; 757 }; 758 759 i2c_dvfs: i2c@e60b0000 { 760 #address-cells = <1>; 761 #size-cells = <0>; 762 compatible = "renesas,iic-r8a77961", 763 "renesas,rcar-gen3-iic", 764 "renesas,rmobile-iic"; 765 reg = <0 0xe60b0000 0 0x425>; 766 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 767 clocks = <&cpg CPG_MOD 926>; 768 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 769 resets = <&cpg 926>; 770 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 771 dma-names = "tx", "rx"; 772 status = "disabled"; 773 }; 774 775 hscif0: serial@e6540000 { 776 compatible = "renesas,hscif-r8a77961", 777 "renesas,rcar-gen3-hscif", 778 "renesas,hscif"; 779 reg = <0 0xe6540000 0 0x60>; 780 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&cpg CPG_MOD 520>, 782 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 783 <&scif_clk>; 784 clock-names = "fck", "brg_int", "scif_clk"; 785 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 786 <&dmac2 0x31>, <&dmac2 0x30>; 787 dma-names = "tx", "rx", "tx", "rx"; 788 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 789 resets = <&cpg 520>; 790 status = "disabled"; 791 }; 792 793 hscif1: serial@e6550000 { 794 compatible = "renesas,hscif-r8a77961", 795 "renesas,rcar-gen3-hscif", 796 "renesas,hscif"; 797 reg = <0 0xe6550000 0 0x60>; 798 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 799 clocks = <&cpg CPG_MOD 519>, 800 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 801 <&scif_clk>; 802 clock-names = "fck", "brg_int", "scif_clk"; 803 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 804 <&dmac2 0x33>, <&dmac2 0x32>; 805 dma-names = "tx", "rx", "tx", "rx"; 806 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 807 resets = <&cpg 519>; 808 status = "disabled"; 809 }; 810 811 hscif2: serial@e6560000 { 812 compatible = "renesas,hscif-r8a77961", 813 "renesas,rcar-gen3-hscif", 814 "renesas,hscif"; 815 reg = <0 0xe6560000 0 0x60>; 816 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 817 clocks = <&cpg CPG_MOD 518>, 818 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 819 <&scif_clk>; 820 clock-names = "fck", "brg_int", "scif_clk"; 821 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 822 <&dmac2 0x35>, <&dmac2 0x34>; 823 dma-names = "tx", "rx", "tx", "rx"; 824 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 825 resets = <&cpg 518>; 826 status = "disabled"; 827 }; 828 829 hscif3: serial@e66a0000 { 830 compatible = "renesas,hscif-r8a77961", 831 "renesas,rcar-gen3-hscif", 832 "renesas,hscif"; 833 reg = <0 0xe66a0000 0 0x60>; 834 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&cpg CPG_MOD 517>, 836 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 837 <&scif_clk>; 838 clock-names = "fck", "brg_int", "scif_clk"; 839 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 840 dma-names = "tx", "rx"; 841 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 842 resets = <&cpg 517>; 843 status = "disabled"; 844 }; 845 846 hscif4: serial@e66b0000 { 847 compatible = "renesas,hscif-r8a77961", 848 "renesas,rcar-gen3-hscif", 849 "renesas,hscif"; 850 reg = <0 0xe66b0000 0 0x60>; 851 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 852 clocks = <&cpg CPG_MOD 516>, 853 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 854 <&scif_clk>; 855 clock-names = "fck", "brg_int", "scif_clk"; 856 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 857 dma-names = "tx", "rx"; 858 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 859 resets = <&cpg 516>; 860 status = "disabled"; 861 }; 862 863 hsusb: usb@e6590000 { 864 compatible = "renesas,usbhs-r8a77961", 865 "renesas,rcar-gen3-usbhs"; 866 reg = <0 0xe6590000 0 0x200>; 867 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 869 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 870 <&usb_dmac1 0>, <&usb_dmac1 1>; 871 dma-names = "ch0", "ch1", "ch2", "ch3"; 872 renesas,buswait = <11>; 873 phys = <&usb2_phy0 3>; 874 phy-names = "usb"; 875 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 876 resets = <&cpg 704>, <&cpg 703>; 877 status = "disabled"; 878 }; 879 880 usb_dmac0: dma-controller@e65a0000 { 881 compatible = "renesas,r8a77961-usb-dmac", 882 "renesas,usb-dmac"; 883 reg = <0 0xe65a0000 0 0x100>; 884 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 886 interrupt-names = "ch0", "ch1"; 887 clocks = <&cpg CPG_MOD 330>; 888 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 889 resets = <&cpg 330>; 890 #dma-cells = <1>; 891 dma-channels = <2>; 892 }; 893 894 usb_dmac1: dma-controller@e65b0000 { 895 compatible = "renesas,r8a77961-usb-dmac", 896 "renesas,usb-dmac"; 897 reg = <0 0xe65b0000 0 0x100>; 898 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 900 interrupt-names = "ch0", "ch1"; 901 clocks = <&cpg CPG_MOD 331>; 902 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 903 resets = <&cpg 331>; 904 #dma-cells = <1>; 905 dma-channels = <2>; 906 }; 907 908 usb3_phy0: usb-phy@e65ee000 { 909 compatible = "renesas,r8a77961-usb3-phy", 910 "renesas,rcar-gen3-usb3-phy"; 911 reg = <0 0xe65ee000 0 0x90>; 912 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 913 <&usb_extal_clk>; 914 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 915 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 916 resets = <&cpg 328>; 917 #phy-cells = <0>; 918 status = "disabled"; 919 }; 920 921 arm_cc630p: crypto@e6601000 { 922 compatible = "arm,cryptocell-630p-ree"; 923 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 924 reg = <0x0 0xe6601000 0 0x1000>; 925 clocks = <&cpg CPG_MOD 229>; 926 resets = <&cpg 229>; 927 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 928 }; 929 930 dmac0: dma-controller@e6700000 { 931 compatible = "renesas,dmac-r8a77961", 932 "renesas,rcar-dmac"; 933 reg = <0 0xe6700000 0 0x10000>; 934 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 951 interrupt-names = "error", 952 "ch0", "ch1", "ch2", "ch3", 953 "ch4", "ch5", "ch6", "ch7", 954 "ch8", "ch9", "ch10", "ch11", 955 "ch12", "ch13", "ch14", "ch15"; 956 clocks = <&cpg CPG_MOD 219>; 957 clock-names = "fck"; 958 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 959 resets = <&cpg 219>; 960 #dma-cells = <1>; 961 dma-channels = <16>; 962 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 963 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 964 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 965 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 966 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 967 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 968 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 969 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 970 }; 971 972 dmac1: dma-controller@e7300000 { 973 compatible = "renesas,dmac-r8a77961", 974 "renesas,rcar-dmac"; 975 reg = <0 0xe7300000 0 0x10000>; 976 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 978 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 979 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 981 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 982 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 993 interrupt-names = "error", 994 "ch0", "ch1", "ch2", "ch3", 995 "ch4", "ch5", "ch6", "ch7", 996 "ch8", "ch9", "ch10", "ch11", 997 "ch12", "ch13", "ch14", "ch15"; 998 clocks = <&cpg CPG_MOD 218>; 999 clock-names = "fck"; 1000 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1001 resets = <&cpg 218>; 1002 #dma-cells = <1>; 1003 dma-channels = <16>; 1004 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 1005 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 1006 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 1007 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 1008 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 1009 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 1010 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 1011 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 1012 }; 1013 1014 dmac2: dma-controller@e7310000 { 1015 compatible = "renesas,dmac-r8a77961", 1016 "renesas,rcar-dmac"; 1017 reg = <0 0xe7310000 0 0x10000>; 1018 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 1019 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 1020 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 1021 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 1022 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 1023 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 1024 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 1026 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 1033 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 1034 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 1035 interrupt-names = "error", 1036 "ch0", "ch1", "ch2", "ch3", 1037 "ch4", "ch5", "ch6", "ch7", 1038 "ch8", "ch9", "ch10", "ch11", 1039 "ch12", "ch13", "ch14", "ch15"; 1040 clocks = <&cpg CPG_MOD 217>; 1041 clock-names = "fck"; 1042 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1043 resets = <&cpg 217>; 1044 #dma-cells = <1>; 1045 dma-channels = <16>; 1046 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 1047 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 1048 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 1049 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 1050 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 1051 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 1052 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 1053 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 1054 }; 1055 1056 ipmmu_ds0: iommu@e6740000 { 1057 compatible = "renesas,ipmmu-r8a77961"; 1058 reg = <0 0xe6740000 0 0x1000>; 1059 renesas,ipmmu-main = <&ipmmu_mm 0>; 1060 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1061 #iommu-cells = <1>; 1062 }; 1063 1064 ipmmu_ds1: iommu@e7740000 { 1065 compatible = "renesas,ipmmu-r8a77961"; 1066 reg = <0 0xe7740000 0 0x1000>; 1067 renesas,ipmmu-main = <&ipmmu_mm 1>; 1068 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1069 #iommu-cells = <1>; 1070 }; 1071 1072 ipmmu_hc: iommu@e6570000 { 1073 compatible = "renesas,ipmmu-r8a77961"; 1074 reg = <0 0xe6570000 0 0x1000>; 1075 renesas,ipmmu-main = <&ipmmu_mm 2>; 1076 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1077 #iommu-cells = <1>; 1078 }; 1079 1080 ipmmu_ir: iommu@ff8b0000 { 1081 compatible = "renesas,ipmmu-r8a77961"; 1082 reg = <0 0xff8b0000 0 0x1000>; 1083 renesas,ipmmu-main = <&ipmmu_mm 3>; 1084 power-domains = <&sysc R8A77961_PD_A3IR>; 1085 #iommu-cells = <1>; 1086 }; 1087 1088 ipmmu_mm: iommu@e67b0000 { 1089 compatible = "renesas,ipmmu-r8a77961"; 1090 reg = <0 0xe67b0000 0 0x1000>; 1091 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1093 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1094 #iommu-cells = <1>; 1095 }; 1096 1097 ipmmu_mp: iommu@ec670000 { 1098 compatible = "renesas,ipmmu-r8a77961"; 1099 reg = <0 0xec670000 0 0x1000>; 1100 renesas,ipmmu-main = <&ipmmu_mm 4>; 1101 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1102 #iommu-cells = <1>; 1103 }; 1104 1105 ipmmu_pv0: iommu@fd800000 { 1106 compatible = "renesas,ipmmu-r8a77961"; 1107 reg = <0 0xfd800000 0 0x1000>; 1108 renesas,ipmmu-main = <&ipmmu_mm 5>; 1109 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1110 #iommu-cells = <1>; 1111 }; 1112 1113 ipmmu_pv1: iommu@fd950000 { 1114 compatible = "renesas,ipmmu-r8a77961"; 1115 reg = <0 0xfd950000 0 0x1000>; 1116 renesas,ipmmu-main = <&ipmmu_mm 6>; 1117 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1118 #iommu-cells = <1>; 1119 }; 1120 1121 ipmmu_rt: iommu@ffc80000 { 1122 compatible = "renesas,ipmmu-r8a77961"; 1123 reg = <0 0xffc80000 0 0x1000>; 1124 renesas,ipmmu-main = <&ipmmu_mm 7>; 1125 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1126 #iommu-cells = <1>; 1127 }; 1128 1129 ipmmu_vc0: iommu@fe6b0000 { 1130 compatible = "renesas,ipmmu-r8a77961"; 1131 reg = <0 0xfe6b0000 0 0x1000>; 1132 renesas,ipmmu-main = <&ipmmu_mm 8>; 1133 power-domains = <&sysc R8A77961_PD_A3VC>; 1134 #iommu-cells = <1>; 1135 }; 1136 1137 ipmmu_vi0: iommu@febd0000 { 1138 compatible = "renesas,ipmmu-r8a77961"; 1139 reg = <0 0xfebd0000 0 0x1000>; 1140 renesas,ipmmu-main = <&ipmmu_mm 9>; 1141 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1142 #iommu-cells = <1>; 1143 }; 1144 1145 avb: ethernet@e6800000 { 1146 compatible = "renesas,etheravb-r8a77961", 1147 "renesas,etheravb-rcar-gen3"; 1148 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 1149 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1174 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1175 "ch4", "ch5", "ch6", "ch7", 1176 "ch8", "ch9", "ch10", "ch11", 1177 "ch12", "ch13", "ch14", "ch15", 1178 "ch16", "ch17", "ch18", "ch19", 1179 "ch20", "ch21", "ch22", "ch23", 1180 "ch24"; 1181 clocks = <&cpg CPG_MOD 812>; 1182 clock-names = "fck"; 1183 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1184 resets = <&cpg 812>; 1185 phy-mode = "rgmii"; 1186 rx-internal-delay-ps = <0>; 1187 tx-internal-delay-ps = <0>; 1188 iommus = <&ipmmu_ds0 16>; 1189 #address-cells = <1>; 1190 #size-cells = <0>; 1191 status = "disabled"; 1192 }; 1193 1194 can0: can@e6c30000 { 1195 compatible = "renesas,can-r8a77961", 1196 "renesas,rcar-gen3-can"; 1197 reg = <0 0xe6c30000 0 0x1000>; 1198 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1199 clocks = <&cpg CPG_MOD 916>, 1200 <&cpg CPG_CORE R8A77961_CLK_CANFD>, 1201 <&can_clk>; 1202 clock-names = "clkp1", "clkp2", "can_clk"; 1203 assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>; 1204 assigned-clock-rates = <40000000>; 1205 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1206 resets = <&cpg 916>; 1207 status = "disabled"; 1208 }; 1209 1210 can1: can@e6c38000 { 1211 compatible = "renesas,can-r8a77961", 1212 "renesas,rcar-gen3-can"; 1213 reg = <0 0xe6c38000 0 0x1000>; 1214 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1215 clocks = <&cpg CPG_MOD 915>, 1216 <&cpg CPG_CORE R8A77961_CLK_CANFD>, 1217 <&can_clk>; 1218 clock-names = "clkp1", "clkp2", "can_clk"; 1219 assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>; 1220 assigned-clock-rates = <40000000>; 1221 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1222 resets = <&cpg 915>; 1223 status = "disabled"; 1224 }; 1225 1226 canfd: can@e66c0000 { 1227 compatible = "renesas,r8a77961-canfd", 1228 "renesas,rcar-gen3-canfd"; 1229 reg = <0 0xe66c0000 0 0x8000>; 1230 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1232 clocks = <&cpg CPG_MOD 914>, 1233 <&cpg CPG_CORE R8A77961_CLK_CANFD>, 1234 <&can_clk>; 1235 clock-names = "fck", "canfd", "can_clk"; 1236 assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>; 1237 assigned-clock-rates = <40000000>; 1238 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1239 resets = <&cpg 914>; 1240 status = "disabled"; 1241 1242 channel0 { 1243 status = "disabled"; 1244 }; 1245 1246 channel1 { 1247 status = "disabled"; 1248 }; 1249 }; 1250 1251 pwm0: pwm@e6e30000 { 1252 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1253 reg = <0 0xe6e30000 0 8>; 1254 #pwm-cells = <2>; 1255 clocks = <&cpg CPG_MOD 523>; 1256 resets = <&cpg 523>; 1257 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1258 status = "disabled"; 1259 }; 1260 1261 pwm1: pwm@e6e31000 { 1262 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1263 reg = <0 0xe6e31000 0 8>; 1264 #pwm-cells = <2>; 1265 clocks = <&cpg CPG_MOD 523>; 1266 resets = <&cpg 523>; 1267 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1268 status = "disabled"; 1269 }; 1270 1271 pwm2: pwm@e6e32000 { 1272 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1273 reg = <0 0xe6e32000 0 8>; 1274 #pwm-cells = <2>; 1275 clocks = <&cpg CPG_MOD 523>; 1276 resets = <&cpg 523>; 1277 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1278 status = "disabled"; 1279 }; 1280 1281 pwm3: pwm@e6e33000 { 1282 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1283 reg = <0 0xe6e33000 0 8>; 1284 #pwm-cells = <2>; 1285 clocks = <&cpg CPG_MOD 523>; 1286 resets = <&cpg 523>; 1287 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1288 status = "disabled"; 1289 }; 1290 1291 pwm4: pwm@e6e34000 { 1292 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1293 reg = <0 0xe6e34000 0 8>; 1294 #pwm-cells = <2>; 1295 clocks = <&cpg CPG_MOD 523>; 1296 resets = <&cpg 523>; 1297 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1298 status = "disabled"; 1299 }; 1300 1301 pwm5: pwm@e6e35000 { 1302 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1303 reg = <0 0xe6e35000 0 8>; 1304 #pwm-cells = <2>; 1305 clocks = <&cpg CPG_MOD 523>; 1306 resets = <&cpg 523>; 1307 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1308 status = "disabled"; 1309 }; 1310 1311 pwm6: pwm@e6e36000 { 1312 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1313 reg = <0 0xe6e36000 0 8>; 1314 #pwm-cells = <2>; 1315 clocks = <&cpg CPG_MOD 523>; 1316 resets = <&cpg 523>; 1317 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1318 status = "disabled"; 1319 }; 1320 1321 scif0: serial@e6e60000 { 1322 compatible = "renesas,scif-r8a77961", 1323 "renesas,rcar-gen3-scif", "renesas,scif"; 1324 reg = <0 0xe6e60000 0 64>; 1325 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1326 clocks = <&cpg CPG_MOD 207>, 1327 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1328 <&scif_clk>; 1329 clock-names = "fck", "brg_int", "scif_clk"; 1330 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1331 <&dmac2 0x51>, <&dmac2 0x50>; 1332 dma-names = "tx", "rx", "tx", "rx"; 1333 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1334 resets = <&cpg 207>; 1335 status = "disabled"; 1336 }; 1337 1338 scif1: serial@e6e68000 { 1339 compatible = "renesas,scif-r8a77961", 1340 "renesas,rcar-gen3-scif", "renesas,scif"; 1341 reg = <0 0xe6e68000 0 64>; 1342 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1343 clocks = <&cpg CPG_MOD 206>, 1344 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1345 <&scif_clk>; 1346 clock-names = "fck", "brg_int", "scif_clk"; 1347 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1348 <&dmac2 0x53>, <&dmac2 0x52>; 1349 dma-names = "tx", "rx", "tx", "rx"; 1350 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1351 resets = <&cpg 206>; 1352 status = "disabled"; 1353 }; 1354 1355 scif2: serial@e6e88000 { 1356 compatible = "renesas,scif-r8a77961", 1357 "renesas,rcar-gen3-scif", "renesas,scif"; 1358 reg = <0 0xe6e88000 0 64>; 1359 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1360 clocks = <&cpg CPG_MOD 310>, 1361 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1362 <&scif_clk>; 1363 clock-names = "fck", "brg_int", "scif_clk"; 1364 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1365 <&dmac2 0x13>, <&dmac2 0x12>; 1366 dma-names = "tx", "rx", "tx", "rx"; 1367 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1368 resets = <&cpg 310>; 1369 status = "disabled"; 1370 }; 1371 1372 scif3: serial@e6c50000 { 1373 compatible = "renesas,scif-r8a77961", 1374 "renesas,rcar-gen3-scif", "renesas,scif"; 1375 reg = <0 0xe6c50000 0 64>; 1376 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1377 clocks = <&cpg CPG_MOD 204>, 1378 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1379 <&scif_clk>; 1380 clock-names = "fck", "brg_int", "scif_clk"; 1381 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1382 dma-names = "tx", "rx"; 1383 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1384 resets = <&cpg 204>; 1385 status = "disabled"; 1386 }; 1387 1388 scif4: serial@e6c40000 { 1389 compatible = "renesas,scif-r8a77961", 1390 "renesas,rcar-gen3-scif", "renesas,scif"; 1391 reg = <0 0xe6c40000 0 64>; 1392 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1393 clocks = <&cpg CPG_MOD 203>, 1394 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1395 <&scif_clk>; 1396 clock-names = "fck", "brg_int", "scif_clk"; 1397 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1398 dma-names = "tx", "rx"; 1399 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1400 resets = <&cpg 203>; 1401 status = "disabled"; 1402 }; 1403 1404 scif5: serial@e6f30000 { 1405 compatible = "renesas,scif-r8a77961", 1406 "renesas,rcar-gen3-scif", "renesas,scif"; 1407 reg = <0 0xe6f30000 0 64>; 1408 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1409 clocks = <&cpg CPG_MOD 202>, 1410 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1411 <&scif_clk>; 1412 clock-names = "fck", "brg_int", "scif_clk"; 1413 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1414 <&dmac2 0x5b>, <&dmac2 0x5a>; 1415 dma-names = "tx", "rx", "tx", "rx"; 1416 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1417 resets = <&cpg 202>; 1418 status = "disabled"; 1419 }; 1420 1421 tpu: pwm@e6e80000 { 1422 compatible = "renesas,tpu-r8a77961", "renesas,tpu"; 1423 reg = <0 0xe6e80000 0 0x148>; 1424 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 1425 clocks = <&cpg CPG_MOD 304>; 1426 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1427 resets = <&cpg 304>; 1428 #pwm-cells = <3>; 1429 status = "disabled"; 1430 }; 1431 1432 msiof0: spi@e6e90000 { 1433 compatible = "renesas,msiof-r8a77961", 1434 "renesas,rcar-gen3-msiof"; 1435 reg = <0 0xe6e90000 0 0x0064>; 1436 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1437 clocks = <&cpg CPG_MOD 211>; 1438 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1439 <&dmac2 0x41>, <&dmac2 0x40>; 1440 dma-names = "tx", "rx", "tx", "rx"; 1441 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1442 resets = <&cpg 211>; 1443 #address-cells = <1>; 1444 #size-cells = <0>; 1445 status = "disabled"; 1446 }; 1447 1448 msiof1: spi@e6ea0000 { 1449 compatible = "renesas,msiof-r8a77961", 1450 "renesas,rcar-gen3-msiof"; 1451 reg = <0 0xe6ea0000 0 0x0064>; 1452 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1453 clocks = <&cpg CPG_MOD 210>; 1454 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1455 <&dmac2 0x43>, <&dmac2 0x42>; 1456 dma-names = "tx", "rx", "tx", "rx"; 1457 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1458 resets = <&cpg 210>; 1459 #address-cells = <1>; 1460 #size-cells = <0>; 1461 status = "disabled"; 1462 }; 1463 1464 msiof2: spi@e6c00000 { 1465 compatible = "renesas,msiof-r8a77961", 1466 "renesas,rcar-gen3-msiof"; 1467 reg = <0 0xe6c00000 0 0x0064>; 1468 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1469 clocks = <&cpg CPG_MOD 209>; 1470 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1471 dma-names = "tx", "rx"; 1472 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1473 resets = <&cpg 209>; 1474 #address-cells = <1>; 1475 #size-cells = <0>; 1476 status = "disabled"; 1477 }; 1478 1479 msiof3: spi@e6c10000 { 1480 compatible = "renesas,msiof-r8a77961", 1481 "renesas,rcar-gen3-msiof"; 1482 reg = <0 0xe6c10000 0 0x0064>; 1483 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1484 clocks = <&cpg CPG_MOD 208>; 1485 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1486 dma-names = "tx", "rx"; 1487 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1488 resets = <&cpg 208>; 1489 #address-cells = <1>; 1490 #size-cells = <0>; 1491 status = "disabled"; 1492 }; 1493 1494 vin0: video@e6ef0000 { 1495 compatible = "renesas,vin-r8a77961"; 1496 reg = <0 0xe6ef0000 0 0x1000>; 1497 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1498 clocks = <&cpg CPG_MOD 811>; 1499 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1500 resets = <&cpg 811>; 1501 renesas,id = <0>; 1502 status = "disabled"; 1503 1504 ports { 1505 #address-cells = <1>; 1506 #size-cells = <0>; 1507 1508 port@1 { 1509 #address-cells = <1>; 1510 #size-cells = <0>; 1511 1512 reg = <1>; 1513 1514 vin0csi20: endpoint@0 { 1515 reg = <0>; 1516 remote-endpoint = <&csi20vin0>; 1517 }; 1518 vin0csi40: endpoint@2 { 1519 reg = <2>; 1520 remote-endpoint = <&csi40vin0>; 1521 }; 1522 }; 1523 }; 1524 }; 1525 1526 vin1: video@e6ef1000 { 1527 compatible = "renesas,vin-r8a77961"; 1528 reg = <0 0xe6ef1000 0 0x1000>; 1529 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1530 clocks = <&cpg CPG_MOD 810>; 1531 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1532 resets = <&cpg 810>; 1533 renesas,id = <1>; 1534 status = "disabled"; 1535 1536 ports { 1537 #address-cells = <1>; 1538 #size-cells = <0>; 1539 1540 port@1 { 1541 #address-cells = <1>; 1542 #size-cells = <0>; 1543 1544 reg = <1>; 1545 1546 vin1csi20: endpoint@0 { 1547 reg = <0>; 1548 remote-endpoint = <&csi20vin1>; 1549 }; 1550 vin1csi40: endpoint@2 { 1551 reg = <2>; 1552 remote-endpoint = <&csi40vin1>; 1553 }; 1554 }; 1555 }; 1556 }; 1557 1558 vin2: video@e6ef2000 { 1559 compatible = "renesas,vin-r8a77961"; 1560 reg = <0 0xe6ef2000 0 0x1000>; 1561 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1562 clocks = <&cpg CPG_MOD 809>; 1563 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1564 resets = <&cpg 809>; 1565 renesas,id = <2>; 1566 status = "disabled"; 1567 1568 ports { 1569 #address-cells = <1>; 1570 #size-cells = <0>; 1571 1572 port@1 { 1573 #address-cells = <1>; 1574 #size-cells = <0>; 1575 1576 reg = <1>; 1577 1578 vin2csi20: endpoint@0 { 1579 reg = <0>; 1580 remote-endpoint = <&csi20vin2>; 1581 }; 1582 vin2csi40: endpoint@2 { 1583 reg = <2>; 1584 remote-endpoint = <&csi40vin2>; 1585 }; 1586 }; 1587 }; 1588 }; 1589 1590 vin3: video@e6ef3000 { 1591 compatible = "renesas,vin-r8a77961"; 1592 reg = <0 0xe6ef3000 0 0x1000>; 1593 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1594 clocks = <&cpg CPG_MOD 808>; 1595 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1596 resets = <&cpg 808>; 1597 renesas,id = <3>; 1598 status = "disabled"; 1599 1600 ports { 1601 #address-cells = <1>; 1602 #size-cells = <0>; 1603 1604 port@1 { 1605 #address-cells = <1>; 1606 #size-cells = <0>; 1607 1608 reg = <1>; 1609 1610 vin3csi20: endpoint@0 { 1611 reg = <0>; 1612 remote-endpoint = <&csi20vin3>; 1613 }; 1614 vin3csi40: endpoint@2 { 1615 reg = <2>; 1616 remote-endpoint = <&csi40vin3>; 1617 }; 1618 }; 1619 }; 1620 }; 1621 1622 vin4: video@e6ef4000 { 1623 compatible = "renesas,vin-r8a77961"; 1624 reg = <0 0xe6ef4000 0 0x1000>; 1625 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1626 clocks = <&cpg CPG_MOD 807>; 1627 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1628 resets = <&cpg 807>; 1629 renesas,id = <4>; 1630 status = "disabled"; 1631 1632 ports { 1633 #address-cells = <1>; 1634 #size-cells = <0>; 1635 1636 port@1 { 1637 #address-cells = <1>; 1638 #size-cells = <0>; 1639 1640 reg = <1>; 1641 1642 vin4csi20: endpoint@0 { 1643 reg = <0>; 1644 remote-endpoint = <&csi20vin4>; 1645 }; 1646 vin4csi40: endpoint@2 { 1647 reg = <2>; 1648 remote-endpoint = <&csi40vin4>; 1649 }; 1650 }; 1651 }; 1652 }; 1653 1654 vin5: video@e6ef5000 { 1655 compatible = "renesas,vin-r8a77961"; 1656 reg = <0 0xe6ef5000 0 0x1000>; 1657 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1658 clocks = <&cpg CPG_MOD 806>; 1659 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1660 resets = <&cpg 806>; 1661 renesas,id = <5>; 1662 status = "disabled"; 1663 1664 ports { 1665 #address-cells = <1>; 1666 #size-cells = <0>; 1667 1668 port@1 { 1669 #address-cells = <1>; 1670 #size-cells = <0>; 1671 1672 reg = <1>; 1673 1674 vin5csi20: endpoint@0 { 1675 reg = <0>; 1676 remote-endpoint = <&csi20vin5>; 1677 }; 1678 vin5csi40: endpoint@2 { 1679 reg = <2>; 1680 remote-endpoint = <&csi40vin5>; 1681 }; 1682 }; 1683 }; 1684 }; 1685 1686 vin6: video@e6ef6000 { 1687 compatible = "renesas,vin-r8a77961"; 1688 reg = <0 0xe6ef6000 0 0x1000>; 1689 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1690 clocks = <&cpg CPG_MOD 805>; 1691 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1692 resets = <&cpg 805>; 1693 renesas,id = <6>; 1694 status = "disabled"; 1695 1696 ports { 1697 #address-cells = <1>; 1698 #size-cells = <0>; 1699 1700 port@1 { 1701 #address-cells = <1>; 1702 #size-cells = <0>; 1703 1704 reg = <1>; 1705 1706 vin6csi20: endpoint@0 { 1707 reg = <0>; 1708 remote-endpoint = <&csi20vin6>; 1709 }; 1710 vin6csi40: endpoint@2 { 1711 reg = <2>; 1712 remote-endpoint = <&csi40vin6>; 1713 }; 1714 }; 1715 }; 1716 }; 1717 1718 vin7: video@e6ef7000 { 1719 compatible = "renesas,vin-r8a77961"; 1720 reg = <0 0xe6ef7000 0 0x1000>; 1721 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 1722 clocks = <&cpg CPG_MOD 804>; 1723 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1724 resets = <&cpg 804>; 1725 renesas,id = <7>; 1726 status = "disabled"; 1727 1728 ports { 1729 #address-cells = <1>; 1730 #size-cells = <0>; 1731 1732 port@1 { 1733 #address-cells = <1>; 1734 #size-cells = <0>; 1735 1736 reg = <1>; 1737 1738 vin7csi20: endpoint@0 { 1739 reg = <0>; 1740 remote-endpoint = <&csi20vin7>; 1741 }; 1742 vin7csi40: endpoint@2 { 1743 reg = <2>; 1744 remote-endpoint = <&csi40vin7>; 1745 }; 1746 }; 1747 }; 1748 }; 1749 1750 rcar_sound: sound@ec500000 { 1751 /* 1752 * #sound-dai-cells is required 1753 * 1754 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1755 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1756 */ 1757 /* 1758 * #clock-cells is required for audio_clkout0/1/2/3 1759 * 1760 * clkout : #clock-cells = <0>; <&rcar_sound>; 1761 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1762 */ 1763 compatible = "renesas,rcar_sound-r8a77961", "renesas,rcar_sound-gen3"; 1764 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1765 <0 0xec5a0000 0 0x100>, /* ADG */ 1766 <0 0xec540000 0 0x1000>, /* SSIU */ 1767 <0 0xec541000 0 0x280>, /* SSI */ 1768 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1769 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1770 1771 clocks = <&cpg CPG_MOD 1005>, 1772 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1773 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1774 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1775 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1776 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1777 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1778 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1779 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1780 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1781 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1782 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1783 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1784 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1785 <&audio_clk_a>, <&audio_clk_b>, 1786 <&audio_clk_c>, 1787 <&cpg CPG_CORE R8A77961_CLK_S0D4>; 1788 clock-names = "ssi-all", 1789 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1790 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1791 "ssi.1", "ssi.0", 1792 "src.9", "src.8", "src.7", "src.6", 1793 "src.5", "src.4", "src.3", "src.2", 1794 "src.1", "src.0", 1795 "mix.1", "mix.0", 1796 "ctu.1", "ctu.0", 1797 "dvc.0", "dvc.1", 1798 "clk_a", "clk_b", "clk_c", "clk_i"; 1799 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1800 resets = <&cpg 1005>, 1801 <&cpg 1006>, <&cpg 1007>, 1802 <&cpg 1008>, <&cpg 1009>, 1803 <&cpg 1010>, <&cpg 1011>, 1804 <&cpg 1012>, <&cpg 1013>, 1805 <&cpg 1014>, <&cpg 1015>; 1806 reset-names = "ssi-all", 1807 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1808 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1809 "ssi.1", "ssi.0"; 1810 status = "disabled"; 1811 1812 rcar_sound,ctu { 1813 ctu00: ctu-0 { }; 1814 ctu01: ctu-1 { }; 1815 ctu02: ctu-2 { }; 1816 ctu03: ctu-3 { }; 1817 ctu10: ctu-4 { }; 1818 ctu11: ctu-5 { }; 1819 ctu12: ctu-6 { }; 1820 ctu13: ctu-7 { }; 1821 }; 1822 1823 rcar_sound,dvc { 1824 dvc0: dvc-0 { 1825 dmas = <&audma1 0xbc>; 1826 dma-names = "tx"; 1827 }; 1828 dvc1: dvc-1 { 1829 dmas = <&audma1 0xbe>; 1830 dma-names = "tx"; 1831 }; 1832 }; 1833 1834 rcar_sound,mix { 1835 mix0: mix-0 { }; 1836 mix1: mix-1 { }; 1837 }; 1838 1839 rcar_sound,src { 1840 src0: src-0 { 1841 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1842 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1843 dma-names = "rx", "tx"; 1844 }; 1845 src1: src-1 { 1846 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1847 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1848 dma-names = "rx", "tx"; 1849 }; 1850 src2: src-2 { 1851 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1852 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1853 dma-names = "rx", "tx"; 1854 }; 1855 src3: src-3 { 1856 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1857 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1858 dma-names = "rx", "tx"; 1859 }; 1860 src4: src-4 { 1861 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1862 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1863 dma-names = "rx", "tx"; 1864 }; 1865 src5: src-5 { 1866 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1867 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1868 dma-names = "rx", "tx"; 1869 }; 1870 src6: src-6 { 1871 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1872 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1873 dma-names = "rx", "tx"; 1874 }; 1875 src7: src-7 { 1876 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1877 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1878 dma-names = "rx", "tx"; 1879 }; 1880 src8: src-8 { 1881 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1882 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1883 dma-names = "rx", "tx"; 1884 }; 1885 src9: src-9 { 1886 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1887 dmas = <&audma0 0x97>, <&audma1 0xba>; 1888 dma-names = "rx", "tx"; 1889 }; 1890 }; 1891 1892 rcar_sound,ssi { 1893 ssi0: ssi-0 { 1894 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1895 dmas = <&audma0 0x01>, <&audma1 0x02>; 1896 dma-names = "rx", "tx"; 1897 }; 1898 ssi1: ssi-1 { 1899 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1900 dmas = <&audma0 0x03>, <&audma1 0x04>; 1901 dma-names = "rx", "tx"; 1902 }; 1903 ssi2: ssi-2 { 1904 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1905 dmas = <&audma0 0x05>, <&audma1 0x06>; 1906 dma-names = "rx", "tx"; 1907 }; 1908 ssi3: ssi-3 { 1909 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1910 dmas = <&audma0 0x07>, <&audma1 0x08>; 1911 dma-names = "rx", "tx"; 1912 }; 1913 ssi4: ssi-4 { 1914 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1915 dmas = <&audma0 0x09>, <&audma1 0x0a>; 1916 dma-names = "rx", "tx"; 1917 }; 1918 ssi5: ssi-5 { 1919 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1920 dmas = <&audma0 0x0b>, <&audma1 0x0c>; 1921 dma-names = "rx", "tx"; 1922 }; 1923 ssi6: ssi-6 { 1924 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1925 dmas = <&audma0 0x0d>, <&audma1 0x0e>; 1926 dma-names = "rx", "tx"; 1927 }; 1928 ssi7: ssi-7 { 1929 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1930 dmas = <&audma0 0x0f>, <&audma1 0x10>; 1931 dma-names = "rx", "tx"; 1932 }; 1933 ssi8: ssi-8 { 1934 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1935 dmas = <&audma0 0x11>, <&audma1 0x12>; 1936 dma-names = "rx", "tx"; 1937 }; 1938 ssi9: ssi-9 { 1939 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1940 dmas = <&audma0 0x13>, <&audma1 0x14>; 1941 dma-names = "rx", "tx"; 1942 }; 1943 }; 1944 1945 rcar_sound,ssiu { 1946 ssiu00: ssiu-0 { 1947 dmas = <&audma0 0x15>, <&audma1 0x16>; 1948 dma-names = "rx", "tx"; 1949 }; 1950 ssiu01: ssiu-1 { 1951 dmas = <&audma0 0x35>, <&audma1 0x36>; 1952 dma-names = "rx", "tx"; 1953 }; 1954 ssiu02: ssiu-2 { 1955 dmas = <&audma0 0x37>, <&audma1 0x38>; 1956 dma-names = "rx", "tx"; 1957 }; 1958 ssiu03: ssiu-3 { 1959 dmas = <&audma0 0x47>, <&audma1 0x48>; 1960 dma-names = "rx", "tx"; 1961 }; 1962 ssiu04: ssiu-4 { 1963 dmas = <&audma0 0x3F>, <&audma1 0x40>; 1964 dma-names = "rx", "tx"; 1965 }; 1966 ssiu05: ssiu-5 { 1967 dmas = <&audma0 0x43>, <&audma1 0x44>; 1968 dma-names = "rx", "tx"; 1969 }; 1970 ssiu06: ssiu-6 { 1971 dmas = <&audma0 0x4F>, <&audma1 0x50>; 1972 dma-names = "rx", "tx"; 1973 }; 1974 ssiu07: ssiu-7 { 1975 dmas = <&audma0 0x53>, <&audma1 0x54>; 1976 dma-names = "rx", "tx"; 1977 }; 1978 ssiu10: ssiu-8 { 1979 dmas = <&audma0 0x49>, <&audma1 0x4a>; 1980 dma-names = "rx", "tx"; 1981 }; 1982 ssiu11: ssiu-9 { 1983 dmas = <&audma0 0x4B>, <&audma1 0x4C>; 1984 dma-names = "rx", "tx"; 1985 }; 1986 ssiu12: ssiu-10 { 1987 dmas = <&audma0 0x57>, <&audma1 0x58>; 1988 dma-names = "rx", "tx"; 1989 }; 1990 ssiu13: ssiu-11 { 1991 dmas = <&audma0 0x59>, <&audma1 0x5A>; 1992 dma-names = "rx", "tx"; 1993 }; 1994 ssiu14: ssiu-12 { 1995 dmas = <&audma0 0x5F>, <&audma1 0x60>; 1996 dma-names = "rx", "tx"; 1997 }; 1998 ssiu15: ssiu-13 { 1999 dmas = <&audma0 0xC3>, <&audma1 0xC4>; 2000 dma-names = "rx", "tx"; 2001 }; 2002 ssiu16: ssiu-14 { 2003 dmas = <&audma0 0xC7>, <&audma1 0xC8>; 2004 dma-names = "rx", "tx"; 2005 }; 2006 ssiu17: ssiu-15 { 2007 dmas = <&audma0 0xCB>, <&audma1 0xCC>; 2008 dma-names = "rx", "tx"; 2009 }; 2010 ssiu20: ssiu-16 { 2011 dmas = <&audma0 0x63>, <&audma1 0x64>; 2012 dma-names = "rx", "tx"; 2013 }; 2014 ssiu21: ssiu-17 { 2015 dmas = <&audma0 0x67>, <&audma1 0x68>; 2016 dma-names = "rx", "tx"; 2017 }; 2018 ssiu22: ssiu-18 { 2019 dmas = <&audma0 0x6B>, <&audma1 0x6C>; 2020 dma-names = "rx", "tx"; 2021 }; 2022 ssiu23: ssiu-19 { 2023 dmas = <&audma0 0x6D>, <&audma1 0x6E>; 2024 dma-names = "rx", "tx"; 2025 }; 2026 ssiu24: ssiu-20 { 2027 dmas = <&audma0 0xCF>, <&audma1 0xCE>; 2028 dma-names = "rx", "tx"; 2029 }; 2030 ssiu25: ssiu-21 { 2031 dmas = <&audma0 0xEB>, <&audma1 0xEC>; 2032 dma-names = "rx", "tx"; 2033 }; 2034 ssiu26: ssiu-22 { 2035 dmas = <&audma0 0xED>, <&audma1 0xEE>; 2036 dma-names = "rx", "tx"; 2037 }; 2038 ssiu27: ssiu-23 { 2039 dmas = <&audma0 0xEF>, <&audma1 0xF0>; 2040 dma-names = "rx", "tx"; 2041 }; 2042 ssiu30: ssiu-24 { 2043 dmas = <&audma0 0x6f>, <&audma1 0x70>; 2044 dma-names = "rx", "tx"; 2045 }; 2046 ssiu31: ssiu-25 { 2047 dmas = <&audma0 0x21>, <&audma1 0x22>; 2048 dma-names = "rx", "tx"; 2049 }; 2050 ssiu32: ssiu-26 { 2051 dmas = <&audma0 0x23>, <&audma1 0x24>; 2052 dma-names = "rx", "tx"; 2053 }; 2054 ssiu33: ssiu-27 { 2055 dmas = <&audma0 0x25>, <&audma1 0x26>; 2056 dma-names = "rx", "tx"; 2057 }; 2058 ssiu34: ssiu-28 { 2059 dmas = <&audma0 0x27>, <&audma1 0x28>; 2060 dma-names = "rx", "tx"; 2061 }; 2062 ssiu35: ssiu-29 { 2063 dmas = <&audma0 0x29>, <&audma1 0x2A>; 2064 dma-names = "rx", "tx"; 2065 }; 2066 ssiu36: ssiu-30 { 2067 dmas = <&audma0 0x2B>, <&audma1 0x2C>; 2068 dma-names = "rx", "tx"; 2069 }; 2070 ssiu37: ssiu-31 { 2071 dmas = <&audma0 0x2D>, <&audma1 0x2E>; 2072 dma-names = "rx", "tx"; 2073 }; 2074 ssiu40: ssiu-32 { 2075 dmas = <&audma0 0x71>, <&audma1 0x72>; 2076 dma-names = "rx", "tx"; 2077 }; 2078 ssiu41: ssiu-33 { 2079 dmas = <&audma0 0x17>, <&audma1 0x18>; 2080 dma-names = "rx", "tx"; 2081 }; 2082 ssiu42: ssiu-34 { 2083 dmas = <&audma0 0x19>, <&audma1 0x1A>; 2084 dma-names = "rx", "tx"; 2085 }; 2086 ssiu43: ssiu-35 { 2087 dmas = <&audma0 0x1B>, <&audma1 0x1C>; 2088 dma-names = "rx", "tx"; 2089 }; 2090 ssiu44: ssiu-36 { 2091 dmas = <&audma0 0x1D>, <&audma1 0x1E>; 2092 dma-names = "rx", "tx"; 2093 }; 2094 ssiu45: ssiu-37 { 2095 dmas = <&audma0 0x1F>, <&audma1 0x20>; 2096 dma-names = "rx", "tx"; 2097 }; 2098 ssiu46: ssiu-38 { 2099 dmas = <&audma0 0x31>, <&audma1 0x32>; 2100 dma-names = "rx", "tx"; 2101 }; 2102 ssiu47: ssiu-39 { 2103 dmas = <&audma0 0x33>, <&audma1 0x34>; 2104 dma-names = "rx", "tx"; 2105 }; 2106 ssiu50: ssiu-40 { 2107 dmas = <&audma0 0x73>, <&audma1 0x74>; 2108 dma-names = "rx", "tx"; 2109 }; 2110 ssiu60: ssiu-41 { 2111 dmas = <&audma0 0x75>, <&audma1 0x76>; 2112 dma-names = "rx", "tx"; 2113 }; 2114 ssiu70: ssiu-42 { 2115 dmas = <&audma0 0x79>, <&audma1 0x7a>; 2116 dma-names = "rx", "tx"; 2117 }; 2118 ssiu80: ssiu-43 { 2119 dmas = <&audma0 0x7b>, <&audma1 0x7c>; 2120 dma-names = "rx", "tx"; 2121 }; 2122 ssiu90: ssiu-44 { 2123 dmas = <&audma0 0x7d>, <&audma1 0x7e>; 2124 dma-names = "rx", "tx"; 2125 }; 2126 ssiu91: ssiu-45 { 2127 dmas = <&audma0 0x7F>, <&audma1 0x80>; 2128 dma-names = "rx", "tx"; 2129 }; 2130 ssiu92: ssiu-46 { 2131 dmas = <&audma0 0x81>, <&audma1 0x82>; 2132 dma-names = "rx", "tx"; 2133 }; 2134 ssiu93: ssiu-47 { 2135 dmas = <&audma0 0x83>, <&audma1 0x84>; 2136 dma-names = "rx", "tx"; 2137 }; 2138 ssiu94: ssiu-48 { 2139 dmas = <&audma0 0xA3>, <&audma1 0xA4>; 2140 dma-names = "rx", "tx"; 2141 }; 2142 ssiu95: ssiu-49 { 2143 dmas = <&audma0 0xA5>, <&audma1 0xA6>; 2144 dma-names = "rx", "tx"; 2145 }; 2146 ssiu96: ssiu-50 { 2147 dmas = <&audma0 0xA7>, <&audma1 0xA8>; 2148 dma-names = "rx", "tx"; 2149 }; 2150 ssiu97: ssiu-51 { 2151 dmas = <&audma0 0xA9>, <&audma1 0xAA>; 2152 dma-names = "rx", "tx"; 2153 }; 2154 }; 2155 }; 2156 2157 mlp: mlp@ec520000 { 2158 compatible = "renesas,r8a77961-mlp", 2159 "renesas,rcar-gen3-mlp"; 2160 reg = <0 0xec520000 0 0x800>; 2161 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 2162 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>; 2163 clocks = <&cpg CPG_MOD 802>; 2164 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2165 resets = <&cpg 802>; 2166 status = "disabled"; 2167 }; 2168 2169 audma0: dma-controller@ec700000 { 2170 compatible = "renesas,dmac-r8a77961", 2171 "renesas,rcar-dmac"; 2172 reg = <0 0xec700000 0 0x10000>; 2173 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 2174 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2175 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2176 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2177 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2178 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2179 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2180 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2181 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2182 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2183 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2184 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2185 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2186 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2187 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2188 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2189 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 2190 interrupt-names = "error", 2191 "ch0", "ch1", "ch2", "ch3", 2192 "ch4", "ch5", "ch6", "ch7", 2193 "ch8", "ch9", "ch10", "ch11", 2194 "ch12", "ch13", "ch14", "ch15"; 2195 clocks = <&cpg CPG_MOD 502>; 2196 clock-names = "fck"; 2197 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2198 resets = <&cpg 502>; 2199 #dma-cells = <1>; 2200 dma-channels = <16>; 2201 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 2202 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 2203 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 2204 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 2205 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 2206 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 2207 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 2208 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 2209 }; 2210 2211 audma1: dma-controller@ec720000 { 2212 compatible = "renesas,dmac-r8a77961", 2213 "renesas,rcar-dmac"; 2214 reg = <0 0xec720000 0 0x10000>; 2215 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 2216 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2217 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2218 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2219 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2220 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2221 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2222 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2223 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2224 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2225 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2226 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 2227 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2228 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 2229 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 2230 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 2231 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 2232 interrupt-names = "error", 2233 "ch0", "ch1", "ch2", "ch3", 2234 "ch4", "ch5", "ch6", "ch7", 2235 "ch8", "ch9", "ch10", "ch11", 2236 "ch12", "ch13", "ch14", "ch15"; 2237 clocks = <&cpg CPG_MOD 501>; 2238 clock-names = "fck"; 2239 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2240 resets = <&cpg 501>; 2241 #dma-cells = <1>; 2242 dma-channels = <16>; 2243 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, 2244 <&ipmmu_mp 18>, <&ipmmu_mp 19>, 2245 <&ipmmu_mp 20>, <&ipmmu_mp 21>, 2246 <&ipmmu_mp 22>, <&ipmmu_mp 23>, 2247 <&ipmmu_mp 24>, <&ipmmu_mp 25>, 2248 <&ipmmu_mp 26>, <&ipmmu_mp 27>, 2249 <&ipmmu_mp 28>, <&ipmmu_mp 29>, 2250 <&ipmmu_mp 30>, <&ipmmu_mp 31>; 2251 }; 2252 2253 xhci0: usb@ee000000 { 2254 compatible = "renesas,xhci-r8a77961", 2255 "renesas,rcar-gen3-xhci"; 2256 reg = <0 0xee000000 0 0xc00>; 2257 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2258 clocks = <&cpg CPG_MOD 328>; 2259 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2260 resets = <&cpg 328>; 2261 status = "disabled"; 2262 }; 2263 2264 usb3_peri0: usb@ee020000 { 2265 compatible = "renesas,r8a77961-usb3-peri", 2266 "renesas,rcar-gen3-usb3-peri"; 2267 reg = <0 0xee020000 0 0x400>; 2268 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2269 clocks = <&cpg CPG_MOD 328>; 2270 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2271 resets = <&cpg 328>; 2272 status = "disabled"; 2273 }; 2274 2275 ohci0: usb@ee080000 { 2276 compatible = "generic-ohci"; 2277 reg = <0 0xee080000 0 0x100>; 2278 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2279 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2280 phys = <&usb2_phy0 1>; 2281 phy-names = "usb"; 2282 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2283 resets = <&cpg 703>, <&cpg 704>; 2284 status = "disabled"; 2285 }; 2286 2287 ohci1: usb@ee0a0000 { 2288 compatible = "generic-ohci"; 2289 reg = <0 0xee0a0000 0 0x100>; 2290 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2291 clocks = <&cpg CPG_MOD 702>; 2292 phys = <&usb2_phy1 1>; 2293 phy-names = "usb"; 2294 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2295 resets = <&cpg 702>; 2296 status = "disabled"; 2297 }; 2298 2299 ehci0: usb@ee080100 { 2300 compatible = "generic-ehci"; 2301 reg = <0 0xee080100 0 0x100>; 2302 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2303 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2304 phys = <&usb2_phy0 2>; 2305 phy-names = "usb"; 2306 companion = <&ohci0>; 2307 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2308 resets = <&cpg 703>, <&cpg 704>; 2309 status = "disabled"; 2310 }; 2311 2312 ehci1: usb@ee0a0100 { 2313 compatible = "generic-ehci"; 2314 reg = <0 0xee0a0100 0 0x100>; 2315 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2316 clocks = <&cpg CPG_MOD 702>; 2317 phys = <&usb2_phy1 2>; 2318 phy-names = "usb"; 2319 companion = <&ohci1>; 2320 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2321 resets = <&cpg 702>; 2322 status = "disabled"; 2323 }; 2324 2325 usb2_phy0: usb-phy@ee080200 { 2326 compatible = "renesas,usb2-phy-r8a77961", 2327 "renesas,rcar-gen3-usb2-phy"; 2328 reg = <0 0xee080200 0 0x700>; 2329 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2330 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2331 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2332 resets = <&cpg 703>, <&cpg 704>; 2333 #phy-cells = <1>; 2334 status = "disabled"; 2335 }; 2336 2337 usb2_phy1: usb-phy@ee0a0200 { 2338 compatible = "renesas,usb2-phy-r8a77961", 2339 "renesas,rcar-gen3-usb2-phy"; 2340 reg = <0 0xee0a0200 0 0x700>; 2341 clocks = <&cpg CPG_MOD 702>; 2342 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2343 resets = <&cpg 702>; 2344 #phy-cells = <1>; 2345 status = "disabled"; 2346 }; 2347 2348 sdhi0: mmc@ee100000 { 2349 compatible = "renesas,sdhi-r8a77961", 2350 "renesas,rcar-gen3-sdhi"; 2351 reg = <0 0xee100000 0 0x2000>; 2352 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 2353 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77961_CLK_SD0H>; 2354 clock-names = "core", "clkh"; 2355 max-frequency = <200000000>; 2356 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2357 resets = <&cpg 314>; 2358 iommus = <&ipmmu_ds1 32>; 2359 status = "disabled"; 2360 }; 2361 2362 sdhi1: mmc@ee120000 { 2363 compatible = "renesas,sdhi-r8a77961", 2364 "renesas,rcar-gen3-sdhi"; 2365 reg = <0 0xee120000 0 0x2000>; 2366 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 2367 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77961_CLK_SD1H>; 2368 clock-names = "core", "clkh"; 2369 max-frequency = <200000000>; 2370 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2371 resets = <&cpg 313>; 2372 iommus = <&ipmmu_ds1 33>; 2373 status = "disabled"; 2374 }; 2375 2376 sdhi2: mmc@ee140000 { 2377 compatible = "renesas,sdhi-r8a77961", 2378 "renesas,rcar-gen3-sdhi"; 2379 reg = <0 0xee140000 0 0x2000>; 2380 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 2381 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77961_CLK_SD2H>; 2382 clock-names = "core", "clkh"; 2383 max-frequency = <200000000>; 2384 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2385 resets = <&cpg 312>; 2386 iommus = <&ipmmu_ds1 34>; 2387 status = "disabled"; 2388 }; 2389 2390 sdhi3: mmc@ee160000 { 2391 compatible = "renesas,sdhi-r8a77961", 2392 "renesas,rcar-gen3-sdhi"; 2393 reg = <0 0xee160000 0 0x2000>; 2394 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 2395 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77961_CLK_SD3H>; 2396 clock-names = "core", "clkh"; 2397 max-frequency = <200000000>; 2398 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2399 resets = <&cpg 311>; 2400 iommus = <&ipmmu_ds1 35>; 2401 status = "disabled"; 2402 }; 2403 2404 rpc: spi@ee200000 { 2405 compatible = "renesas,r8a77961-rpc-if", 2406 "renesas,rcar-gen3-rpc-if"; 2407 reg = <0 0xee200000 0 0x200>, 2408 <0 0x08000000 0 0x04000000>, 2409 <0 0xee208000 0 0x100>; 2410 reg-names = "regs", "dirmap", "wbuf"; 2411 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 2412 clocks = <&cpg CPG_MOD 917>; 2413 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2414 resets = <&cpg 917>; 2415 #address-cells = <1>; 2416 #size-cells = <0>; 2417 status = "disabled"; 2418 }; 2419 2420 gic: interrupt-controller@f1010000 { 2421 compatible = "arm,gic-400"; 2422 #interrupt-cells = <3>; 2423 #address-cells = <0>; 2424 interrupt-controller; 2425 reg = <0x0 0xf1010000 0 0x1000>, 2426 <0x0 0xf1020000 0 0x20000>, 2427 <0x0 0xf1040000 0 0x20000>, 2428 <0x0 0xf1060000 0 0x20000>; 2429 interrupts = <GIC_PPI 9 2430 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 2431 clocks = <&cpg CPG_MOD 408>; 2432 clock-names = "clk"; 2433 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2434 resets = <&cpg 408>; 2435 }; 2436 2437 pciec0: pcie@fe000000 { 2438 compatible = "renesas,pcie-r8a77961", 2439 "renesas,pcie-rcar-gen3"; 2440 reg = <0 0xfe000000 0 0x80000>; 2441 #address-cells = <3>; 2442 #size-cells = <2>; 2443 bus-range = <0x00 0xff>; 2444 device_type = "pci"; 2445 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 2446 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 2447 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 2448 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 2449 /* Map all possible DDR as inbound ranges */ 2450 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2451 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2452 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2453 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2454 #interrupt-cells = <1>; 2455 interrupt-map-mask = <0 0 0 0>; 2456 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2457 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 2458 clock-names = "pcie", "pcie_bus"; 2459 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2460 resets = <&cpg 319>; 2461 status = "disabled"; 2462 }; 2463 2464 pciec1: pcie@ee800000 { 2465 compatible = "renesas,pcie-r8a77961", 2466 "renesas,pcie-rcar-gen3"; 2467 reg = <0 0xee800000 0 0x80000>; 2468 #address-cells = <3>; 2469 #size-cells = <2>; 2470 bus-range = <0x00 0xff>; 2471 device_type = "pci"; 2472 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, 2473 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, 2474 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, 2475 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 2476 /* Map all possible DDR as inbound ranges */ 2477 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2478 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2479 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2480 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2481 #interrupt-cells = <1>; 2482 interrupt-map-mask = <0 0 0 0>; 2483 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2484 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 2485 clock-names = "pcie", "pcie_bus"; 2486 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2487 resets = <&cpg 318>; 2488 status = "disabled"; 2489 }; 2490 2491 fcpf0: fcp@fe950000 { 2492 compatible = "renesas,fcpf"; 2493 reg = <0 0xfe950000 0 0x200>; 2494 clocks = <&cpg CPG_MOD 615>; 2495 power-domains = <&sysc R8A77961_PD_A3VC>; 2496 resets = <&cpg 615>; 2497 }; 2498 2499 fcpvb0: fcp@fe96f000 { 2500 compatible = "renesas,fcpv"; 2501 reg = <0 0xfe96f000 0 0x200>; 2502 clocks = <&cpg CPG_MOD 607>; 2503 power-domains = <&sysc R8A77961_PD_A3VC>; 2504 resets = <&cpg 607>; 2505 }; 2506 2507 fcpvi0: fcp@fe9af000 { 2508 compatible = "renesas,fcpv"; 2509 reg = <0 0xfe9af000 0 0x200>; 2510 clocks = <&cpg CPG_MOD 611>; 2511 power-domains = <&sysc R8A77961_PD_A3VC>; 2512 resets = <&cpg 611>; 2513 iommus = <&ipmmu_vc0 19>; 2514 }; 2515 2516 fcpvd0: fcp@fea27000 { 2517 compatible = "renesas,fcpv"; 2518 reg = <0 0xfea27000 0 0x200>; 2519 clocks = <&cpg CPG_MOD 603>; 2520 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2521 resets = <&cpg 603>; 2522 iommus = <&ipmmu_vi0 8>; 2523 }; 2524 2525 fcpvd1: fcp@fea2f000 { 2526 compatible = "renesas,fcpv"; 2527 reg = <0 0xfea2f000 0 0x200>; 2528 clocks = <&cpg CPG_MOD 602>; 2529 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2530 resets = <&cpg 602>; 2531 iommus = <&ipmmu_vi0 9>; 2532 }; 2533 2534 fcpvd2: fcp@fea37000 { 2535 compatible = "renesas,fcpv"; 2536 reg = <0 0xfea37000 0 0x200>; 2537 clocks = <&cpg CPG_MOD 601>; 2538 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2539 resets = <&cpg 601>; 2540 iommus = <&ipmmu_vi0 10>; 2541 }; 2542 2543 vspb: vsp@fe960000 { 2544 compatible = "renesas,vsp2"; 2545 reg = <0 0xfe960000 0 0x8000>; 2546 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 2547 clocks = <&cpg CPG_MOD 626>; 2548 power-domains = <&sysc R8A77961_PD_A3VC>; 2549 resets = <&cpg 626>; 2550 2551 renesas,fcp = <&fcpvb0>; 2552 }; 2553 2554 vspd0: vsp@fea20000 { 2555 compatible = "renesas,vsp2"; 2556 reg = <0 0xfea20000 0 0x5000>; 2557 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 2558 clocks = <&cpg CPG_MOD 623>; 2559 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2560 resets = <&cpg 623>; 2561 2562 renesas,fcp = <&fcpvd0>; 2563 }; 2564 2565 vspd1: vsp@fea28000 { 2566 compatible = "renesas,vsp2"; 2567 reg = <0 0xfea28000 0 0x5000>; 2568 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 2569 clocks = <&cpg CPG_MOD 622>; 2570 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2571 resets = <&cpg 622>; 2572 2573 renesas,fcp = <&fcpvd1>; 2574 }; 2575 2576 vspd2: vsp@fea30000 { 2577 compatible = "renesas,vsp2"; 2578 reg = <0 0xfea30000 0 0x5000>; 2579 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 2580 clocks = <&cpg CPG_MOD 621>; 2581 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2582 resets = <&cpg 621>; 2583 2584 renesas,fcp = <&fcpvd2>; 2585 }; 2586 2587 vspi0: vsp@fe9a0000 { 2588 compatible = "renesas,vsp2"; 2589 reg = <0 0xfe9a0000 0 0x8000>; 2590 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 2591 clocks = <&cpg CPG_MOD 631>; 2592 power-domains = <&sysc R8A77961_PD_A3VC>; 2593 resets = <&cpg 631>; 2594 2595 renesas,fcp = <&fcpvi0>; 2596 }; 2597 2598 csi20: csi2@fea80000 { 2599 compatible = "renesas,r8a77961-csi2"; 2600 reg = <0 0xfea80000 0 0x10000>; 2601 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2602 clocks = <&cpg CPG_MOD 714>; 2603 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2604 resets = <&cpg 714>; 2605 status = "disabled"; 2606 2607 ports { 2608 #address-cells = <1>; 2609 #size-cells = <0>; 2610 2611 port@0 { 2612 reg = <0>; 2613 }; 2614 2615 port@1 { 2616 #address-cells = <1>; 2617 #size-cells = <0>; 2618 2619 reg = <1>; 2620 2621 csi20vin0: endpoint@0 { 2622 reg = <0>; 2623 remote-endpoint = <&vin0csi20>; 2624 }; 2625 csi20vin1: endpoint@1 { 2626 reg = <1>; 2627 remote-endpoint = <&vin1csi20>; 2628 }; 2629 csi20vin2: endpoint@2 { 2630 reg = <2>; 2631 remote-endpoint = <&vin2csi20>; 2632 }; 2633 csi20vin3: endpoint@3 { 2634 reg = <3>; 2635 remote-endpoint = <&vin3csi20>; 2636 }; 2637 csi20vin4: endpoint@4 { 2638 reg = <4>; 2639 remote-endpoint = <&vin4csi20>; 2640 }; 2641 csi20vin5: endpoint@5 { 2642 reg = <5>; 2643 remote-endpoint = <&vin5csi20>; 2644 }; 2645 csi20vin6: endpoint@6 { 2646 reg = <6>; 2647 remote-endpoint = <&vin6csi20>; 2648 }; 2649 csi20vin7: endpoint@7 { 2650 reg = <7>; 2651 remote-endpoint = <&vin7csi20>; 2652 }; 2653 }; 2654 }; 2655 }; 2656 2657 csi40: csi2@feaa0000 { 2658 compatible = "renesas,r8a77961-csi2"; 2659 reg = <0 0xfeaa0000 0 0x10000>; 2660 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2661 clocks = <&cpg CPG_MOD 716>; 2662 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2663 resets = <&cpg 716>; 2664 status = "disabled"; 2665 2666 ports { 2667 #address-cells = <1>; 2668 #size-cells = <0>; 2669 2670 port@0 { 2671 reg = <0>; 2672 }; 2673 2674 port@1 { 2675 #address-cells = <1>; 2676 #size-cells = <0>; 2677 2678 reg = <1>; 2679 2680 csi40vin0: endpoint@0 { 2681 reg = <0>; 2682 remote-endpoint = <&vin0csi40>; 2683 }; 2684 csi40vin1: endpoint@1 { 2685 reg = <1>; 2686 remote-endpoint = <&vin1csi40>; 2687 }; 2688 csi40vin2: endpoint@2 { 2689 reg = <2>; 2690 remote-endpoint = <&vin2csi40>; 2691 }; 2692 csi40vin3: endpoint@3 { 2693 reg = <3>; 2694 remote-endpoint = <&vin3csi40>; 2695 }; 2696 csi40vin4: endpoint@4 { 2697 reg = <4>; 2698 remote-endpoint = <&vin4csi40>; 2699 }; 2700 csi40vin5: endpoint@5 { 2701 reg = <5>; 2702 remote-endpoint = <&vin5csi40>; 2703 }; 2704 csi40vin6: endpoint@6 { 2705 reg = <6>; 2706 remote-endpoint = <&vin6csi40>; 2707 }; 2708 csi40vin7: endpoint@7 { 2709 reg = <7>; 2710 remote-endpoint = <&vin7csi40>; 2711 }; 2712 }; 2713 2714 }; 2715 }; 2716 2717 hdmi0: hdmi@fead0000 { 2718 compatible = "renesas,r8a77961-hdmi", "renesas,rcar-gen3-hdmi"; 2719 reg = <0 0xfead0000 0 0x10000>; 2720 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 2721 clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A77961_CLK_HDMI>; 2722 clock-names = "iahb", "isfr"; 2723 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2724 resets = <&cpg 729>; 2725 status = "disabled"; 2726 2727 ports { 2728 #address-cells = <1>; 2729 #size-cells = <0>; 2730 port@0 { 2731 reg = <0>; 2732 dw_hdmi0_in: endpoint { 2733 remote-endpoint = <&du_out_hdmi0>; 2734 }; 2735 }; 2736 port@1 { 2737 reg = <1>; 2738 }; 2739 port@2 { 2740 /* HDMI sound */ 2741 reg = <2>; 2742 }; 2743 }; 2744 }; 2745 2746 du: display@feb00000 { 2747 compatible = "renesas,du-r8a77961"; 2748 reg = <0 0xfeb00000 0 0x70000>; 2749 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2750 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2751 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2752 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, 2753 <&cpg CPG_MOD 722>; 2754 clock-names = "du.0", "du.1", "du.2"; 2755 resets = <&cpg 724>, <&cpg 722>; 2756 reset-names = "du.0", "du.2"; 2757 2758 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; 2759 status = "disabled"; 2760 2761 ports { 2762 #address-cells = <1>; 2763 #size-cells = <0>; 2764 2765 port@0 { 2766 reg = <0>; 2767 du_out_rgb: endpoint { 2768 }; 2769 }; 2770 port@1 { 2771 reg = <1>; 2772 du_out_hdmi0: endpoint { 2773 remote-endpoint = <&dw_hdmi0_in>; 2774 }; 2775 }; 2776 port@2 { 2777 reg = <2>; 2778 du_out_lvds0: endpoint { 2779 remote-endpoint = <&lvds0_in>; 2780 }; 2781 }; 2782 }; 2783 }; 2784 2785 lvds0: lvds@feb90000 { 2786 compatible = "renesas,r8a77961-lvds"; 2787 reg = <0 0xfeb90000 0 0x14>; 2788 clocks = <&cpg CPG_MOD 727>; 2789 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2790 resets = <&cpg 727>; 2791 status = "disabled"; 2792 2793 ports { 2794 #address-cells = <1>; 2795 #size-cells = <0>; 2796 2797 port@0 { 2798 reg = <0>; 2799 lvds0_in: endpoint { 2800 remote-endpoint = <&du_out_lvds0>; 2801 }; 2802 }; 2803 port@1 { 2804 reg = <1>; 2805 lvds0_out: endpoint { 2806 }; 2807 }; 2808 }; 2809 }; 2810 2811 prr: chipid@fff00044 { 2812 compatible = "renesas,prr"; 2813 reg = <0 0xfff00044 0 4>; 2814 }; 2815 }; 2816 2817 thermal-zones { 2818 sensor1_thermal: sensor1-thermal { 2819 polling-delay-passive = <250>; 2820 polling-delay = <1000>; 2821 thermal-sensors = <&tsc 0>; 2822 sustainable-power = <3874>; 2823 2824 trips { 2825 sensor1_crit: sensor1-crit { 2826 temperature = <120000>; 2827 hysteresis = <1000>; 2828 type = "critical"; 2829 }; 2830 }; 2831 }; 2832 2833 sensor2_thermal: sensor2-thermal { 2834 polling-delay-passive = <250>; 2835 polling-delay = <1000>; 2836 thermal-sensors = <&tsc 1>; 2837 sustainable-power = <3874>; 2838 2839 trips { 2840 sensor2_crit: sensor2-crit { 2841 temperature = <120000>; 2842 hysteresis = <1000>; 2843 type = "critical"; 2844 }; 2845 }; 2846 }; 2847 2848 sensor3_thermal: sensor3-thermal { 2849 polling-delay-passive = <250>; 2850 polling-delay = <1000>; 2851 thermal-sensors = <&tsc 2>; 2852 sustainable-power = <3874>; 2853 2854 cooling-maps { 2855 map0 { 2856 trip = <&target>; 2857 cooling-device = <&a57_0 2 4>; 2858 contribution = <1024>; 2859 }; 2860 map1 { 2861 trip = <&target>; 2862 cooling-device = <&a53_0 0 2>; 2863 contribution = <1024>; 2864 }; 2865 }; 2866 trips { 2867 target: trip-point1 { 2868 temperature = <100000>; 2869 hysteresis = <1000>; 2870 type = "passive"; 2871 }; 2872 2873 sensor3_crit: sensor3-crit { 2874 temperature = <120000>; 2875 hysteresis = <1000>; 2876 type = "critical"; 2877 }; 2878 }; 2879 }; 2880 }; 2881 2882 timer { 2883 compatible = "arm,armv8-timer"; 2884 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2885 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2886 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2887 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 2888 }; 2889 2890 /* External USB clocks - can be overridden by the board */ 2891 usb3s0_clk: usb3s0 { 2892 compatible = "fixed-clock"; 2893 #clock-cells = <0>; 2894 clock-frequency = <0>; 2895 }; 2896 2897 usb_extal_clk: usb_extal { 2898 compatible = "fixed-clock"; 2899 #clock-cells = <0>; 2900 clock-frequency = <0>; 2901 }; 2902}; 2903