1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC 4 * 5 * Copyright (C) 2016-2017 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a77961-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a77961-sysc.h> 11 12#define CPG_AUDIO_CLK_I R8A77961_CLK_S0D4 13 14/ { 15 compatible = "renesas,r8a77961"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* 20 * The external audio clocks are configured as 0 Hz fixed frequency 21 * clocks by default. 22 * Boards that provide audio clocks should override them. 23 */ 24 audio_clk_a: audio_clk_a { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <0>; 28 }; 29 30 audio_clk_b: audio_clk_b { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <0>; 34 }; 35 36 audio_clk_c: audio_clk_c { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <0>; 40 }; 41 42 /* External CAN clock - to be overridden by boards that provide it */ 43 can_clk: can { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <0>; 47 }; 48 49 cluster0_opp: opp_table0 { 50 compatible = "operating-points-v2"; 51 opp-shared; 52 53 opp-500000000 { 54 opp-hz = /bits/ 64 <500000000>; 55 opp-microvolt = <820000>; 56 clock-latency-ns = <300000>; 57 }; 58 opp-1000000000 { 59 opp-hz = /bits/ 64 <1000000000>; 60 opp-microvolt = <820000>; 61 clock-latency-ns = <300000>; 62 }; 63 opp-1500000000 { 64 opp-hz = /bits/ 64 <1500000000>; 65 opp-microvolt = <820000>; 66 clock-latency-ns = <300000>; 67 }; 68 opp-1600000000 { 69 opp-hz = /bits/ 64 <1600000000>; 70 opp-microvolt = <900000>; 71 clock-latency-ns = <300000>; 72 turbo-mode; 73 }; 74 opp-1700000000 { 75 opp-hz = /bits/ 64 <1700000000>; 76 opp-microvolt = <900000>; 77 clock-latency-ns = <300000>; 78 turbo-mode; 79 }; 80 opp-1800000000 { 81 opp-hz = /bits/ 64 <1800000000>; 82 opp-microvolt = <960000>; 83 clock-latency-ns = <300000>; 84 turbo-mode; 85 }; 86 }; 87 88 cluster1_opp: opp_table1 { 89 compatible = "operating-points-v2"; 90 opp-shared; 91 92 opp-800000000 { 93 opp-hz = /bits/ 64 <800000000>; 94 opp-microvolt = <820000>; 95 clock-latency-ns = <300000>; 96 }; 97 opp-1000000000 { 98 opp-hz = /bits/ 64 <1000000000>; 99 opp-microvolt = <820000>; 100 clock-latency-ns = <300000>; 101 }; 102 opp-1200000000 { 103 opp-hz = /bits/ 64 <1200000000>; 104 opp-microvolt = <820000>; 105 clock-latency-ns = <300000>; 106 }; 107 opp-1300000000 { 108 opp-hz = /bits/ 64 <1300000000>; 109 opp-microvolt = <820000>; 110 clock-latency-ns = <300000>; 111 turbo-mode; 112 }; 113 }; 114 115 cpus { 116 #address-cells = <1>; 117 #size-cells = <0>; 118 119 cpu-map { 120 cluster0 { 121 core0 { 122 cpu = <&a57_0>; 123 }; 124 core1 { 125 cpu = <&a57_1>; 126 }; 127 }; 128 129 cluster1 { 130 core0 { 131 cpu = <&a53_0>; 132 }; 133 core1 { 134 cpu = <&a53_1>; 135 }; 136 core2 { 137 cpu = <&a53_2>; 138 }; 139 core3 { 140 cpu = <&a53_3>; 141 }; 142 }; 143 }; 144 145 a57_0: cpu@0 { 146 compatible = "arm,cortex-a57"; 147 reg = <0x0>; 148 device_type = "cpu"; 149 power-domains = <&sysc R8A77961_PD_CA57_CPU0>; 150 next-level-cache = <&L2_CA57>; 151 enable-method = "psci"; 152 cpu-idle-states = <&CPU_SLEEP_0>; 153 dynamic-power-coefficient = <854>; 154 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; 155 operating-points-v2 = <&cluster0_opp>; 156 capacity-dmips-mhz = <1024>; 157 #cooling-cells = <2>; 158 }; 159 160 a57_1: cpu@1 { 161 compatible = "arm,cortex-a57"; 162 reg = <0x1>; 163 device_type = "cpu"; 164 power-domains = <&sysc R8A77961_PD_CA57_CPU1>; 165 next-level-cache = <&L2_CA57>; 166 enable-method = "psci"; 167 cpu-idle-states = <&CPU_SLEEP_0>; 168 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; 169 operating-points-v2 = <&cluster0_opp>; 170 capacity-dmips-mhz = <1024>; 171 #cooling-cells = <2>; 172 }; 173 174 a53_0: cpu@100 { 175 compatible = "arm,cortex-a53"; 176 reg = <0x100>; 177 device_type = "cpu"; 178 power-domains = <&sysc R8A77961_PD_CA53_CPU0>; 179 next-level-cache = <&L2_CA53>; 180 enable-method = "psci"; 181 cpu-idle-states = <&CPU_SLEEP_1>; 182 #cooling-cells = <2>; 183 dynamic-power-coefficient = <277>; 184 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 185 operating-points-v2 = <&cluster1_opp>; 186 capacity-dmips-mhz = <535>; 187 }; 188 189 a53_1: cpu@101 { 190 compatible = "arm,cortex-a53"; 191 reg = <0x101>; 192 device_type = "cpu"; 193 power-domains = <&sysc R8A77961_PD_CA53_CPU1>; 194 next-level-cache = <&L2_CA53>; 195 enable-method = "psci"; 196 cpu-idle-states = <&CPU_SLEEP_1>; 197 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 198 operating-points-v2 = <&cluster1_opp>; 199 capacity-dmips-mhz = <535>; 200 }; 201 202 a53_2: cpu@102 { 203 compatible = "arm,cortex-a53"; 204 reg = <0x102>; 205 device_type = "cpu"; 206 power-domains = <&sysc R8A77961_PD_CA53_CPU2>; 207 next-level-cache = <&L2_CA53>; 208 enable-method = "psci"; 209 cpu-idle-states = <&CPU_SLEEP_1>; 210 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 211 operating-points-v2 = <&cluster1_opp>; 212 capacity-dmips-mhz = <535>; 213 }; 214 215 a53_3: cpu@103 { 216 compatible = "arm,cortex-a53"; 217 reg = <0x103>; 218 device_type = "cpu"; 219 power-domains = <&sysc R8A77961_PD_CA53_CPU3>; 220 next-level-cache = <&L2_CA53>; 221 enable-method = "psci"; 222 cpu-idle-states = <&CPU_SLEEP_1>; 223 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 224 operating-points-v2 = <&cluster1_opp>; 225 capacity-dmips-mhz = <535>; 226 }; 227 228 L2_CA57: cache-controller-0 { 229 compatible = "cache"; 230 power-domains = <&sysc R8A77961_PD_CA57_SCU>; 231 cache-unified; 232 cache-level = <2>; 233 }; 234 235 L2_CA53: cache-controller-1 { 236 compatible = "cache"; 237 power-domains = <&sysc R8A77961_PD_CA53_SCU>; 238 cache-unified; 239 cache-level = <2>; 240 }; 241 242 idle-states { 243 entry-method = "psci"; 244 245 CPU_SLEEP_0: cpu-sleep-0 { 246 compatible = "arm,idle-state"; 247 arm,psci-suspend-param = <0x0010000>; 248 local-timer-stop; 249 entry-latency-us = <400>; 250 exit-latency-us = <500>; 251 min-residency-us = <4000>; 252 }; 253 254 CPU_SLEEP_1: cpu-sleep-1 { 255 compatible = "arm,idle-state"; 256 arm,psci-suspend-param = <0x0010000>; 257 local-timer-stop; 258 entry-latency-us = <700>; 259 exit-latency-us = <700>; 260 min-residency-us = <5000>; 261 }; 262 }; 263 }; 264 265 extal_clk: extal { 266 compatible = "fixed-clock"; 267 #clock-cells = <0>; 268 /* This value must be overridden by the board */ 269 clock-frequency = <0>; 270 }; 271 272 extalr_clk: extalr { 273 compatible = "fixed-clock"; 274 #clock-cells = <0>; 275 /* This value must be overridden by the board */ 276 clock-frequency = <0>; 277 }; 278 279 /* External PCIe clock - can be overridden by the board */ 280 pcie_bus_clk: pcie_bus { 281 compatible = "fixed-clock"; 282 #clock-cells = <0>; 283 clock-frequency = <0>; 284 }; 285 286 pmu_a53 { 287 compatible = "arm,cortex-a53-pmu"; 288 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 289 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 290 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 291 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 292 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 293 }; 294 295 pmu_a57 { 296 compatible = "arm,cortex-a57-pmu"; 297 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 298 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 299 interrupt-affinity = <&a57_0>, <&a57_1>; 300 }; 301 302 psci { 303 compatible = "arm,psci-1.0", "arm,psci-0.2"; 304 method = "smc"; 305 }; 306 307 /* External SCIF clock - to be overridden by boards that provide it */ 308 scif_clk: scif { 309 compatible = "fixed-clock"; 310 #clock-cells = <0>; 311 clock-frequency = <0>; 312 }; 313 314 soc { 315 compatible = "simple-bus"; 316 interrupt-parent = <&gic>; 317 #address-cells = <2>; 318 #size-cells = <2>; 319 ranges; 320 321 rwdt: watchdog@e6020000 { 322 compatible = "renesas,r8a77961-wdt", 323 "renesas,rcar-gen3-wdt"; 324 reg = <0 0xe6020000 0 0x0c>; 325 clocks = <&cpg CPG_MOD 402>; 326 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 327 resets = <&cpg 402>; 328 status = "disabled"; 329 }; 330 331 gpio0: gpio@e6050000 { 332 compatible = "renesas,gpio-r8a77961", 333 "renesas,rcar-gen3-gpio"; 334 reg = <0 0xe6050000 0 0x50>; 335 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 336 #gpio-cells = <2>; 337 gpio-controller; 338 gpio-ranges = <&pfc 0 0 16>; 339 #interrupt-cells = <2>; 340 interrupt-controller; 341 clocks = <&cpg CPG_MOD 912>; 342 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 343 resets = <&cpg 912>; 344 }; 345 346 gpio1: gpio@e6051000 { 347 compatible = "renesas,gpio-r8a77961", 348 "renesas,rcar-gen3-gpio"; 349 reg = <0 0xe6051000 0 0x50>; 350 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 351 #gpio-cells = <2>; 352 gpio-controller; 353 gpio-ranges = <&pfc 0 32 29>; 354 #interrupt-cells = <2>; 355 interrupt-controller; 356 clocks = <&cpg CPG_MOD 911>; 357 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 358 resets = <&cpg 911>; 359 }; 360 361 gpio2: gpio@e6052000 { 362 compatible = "renesas,gpio-r8a77961", 363 "renesas,rcar-gen3-gpio"; 364 reg = <0 0xe6052000 0 0x50>; 365 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 366 #gpio-cells = <2>; 367 gpio-controller; 368 gpio-ranges = <&pfc 0 64 15>; 369 #interrupt-cells = <2>; 370 interrupt-controller; 371 clocks = <&cpg CPG_MOD 910>; 372 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 373 resets = <&cpg 910>; 374 }; 375 376 gpio3: gpio@e6053000 { 377 compatible = "renesas,gpio-r8a77961", 378 "renesas,rcar-gen3-gpio"; 379 reg = <0 0xe6053000 0 0x50>; 380 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 381 #gpio-cells = <2>; 382 gpio-controller; 383 gpio-ranges = <&pfc 0 96 16>; 384 #interrupt-cells = <2>; 385 interrupt-controller; 386 clocks = <&cpg CPG_MOD 909>; 387 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 388 resets = <&cpg 909>; 389 }; 390 391 gpio4: gpio@e6054000 { 392 compatible = "renesas,gpio-r8a77961", 393 "renesas,rcar-gen3-gpio"; 394 reg = <0 0xe6054000 0 0x50>; 395 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 396 #gpio-cells = <2>; 397 gpio-controller; 398 gpio-ranges = <&pfc 0 128 18>; 399 #interrupt-cells = <2>; 400 interrupt-controller; 401 clocks = <&cpg CPG_MOD 908>; 402 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 403 resets = <&cpg 908>; 404 }; 405 406 gpio5: gpio@e6055000 { 407 compatible = "renesas,gpio-r8a77961", 408 "renesas,rcar-gen3-gpio"; 409 reg = <0 0xe6055000 0 0x50>; 410 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 411 #gpio-cells = <2>; 412 gpio-controller; 413 gpio-ranges = <&pfc 0 160 26>; 414 #interrupt-cells = <2>; 415 interrupt-controller; 416 clocks = <&cpg CPG_MOD 907>; 417 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 418 resets = <&cpg 907>; 419 }; 420 421 gpio6: gpio@e6055400 { 422 compatible = "renesas,gpio-r8a77961", 423 "renesas,rcar-gen3-gpio"; 424 reg = <0 0xe6055400 0 0x50>; 425 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 426 #gpio-cells = <2>; 427 gpio-controller; 428 gpio-ranges = <&pfc 0 192 32>; 429 #interrupt-cells = <2>; 430 interrupt-controller; 431 clocks = <&cpg CPG_MOD 906>; 432 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 433 resets = <&cpg 906>; 434 }; 435 436 gpio7: gpio@e6055800 { 437 compatible = "renesas,gpio-r8a77961", 438 "renesas,rcar-gen3-gpio"; 439 reg = <0 0xe6055800 0 0x50>; 440 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 441 #gpio-cells = <2>; 442 gpio-controller; 443 gpio-ranges = <&pfc 0 224 4>; 444 #interrupt-cells = <2>; 445 interrupt-controller; 446 clocks = <&cpg CPG_MOD 905>; 447 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 448 resets = <&cpg 905>; 449 }; 450 451 pfc: pinctrl@e6060000 { 452 compatible = "renesas,pfc-r8a77961"; 453 reg = <0 0xe6060000 0 0x50c>; 454 }; 455 456 cmt0: timer@e60f0000 { 457 compatible = "renesas,r8a77961-cmt0", 458 "renesas,rcar-gen3-cmt0"; 459 reg = <0 0xe60f0000 0 0x1004>; 460 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&cpg CPG_MOD 303>; 463 clock-names = "fck"; 464 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 465 resets = <&cpg 303>; 466 status = "disabled"; 467 }; 468 469 cmt1: timer@e6130000 { 470 compatible = "renesas,r8a77961-cmt1", 471 "renesas,rcar-gen3-cmt1"; 472 reg = <0 0xe6130000 0 0x1004>; 473 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&cpg CPG_MOD 302>; 482 clock-names = "fck"; 483 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 484 resets = <&cpg 302>; 485 status = "disabled"; 486 }; 487 488 cmt2: timer@e6140000 { 489 compatible = "renesas,r8a77961-cmt1", 490 "renesas,rcar-gen3-cmt1"; 491 reg = <0 0xe6140000 0 0x1004>; 492 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&cpg CPG_MOD 301>; 501 clock-names = "fck"; 502 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 503 resets = <&cpg 301>; 504 status = "disabled"; 505 }; 506 507 cmt3: timer@e6148000 { 508 compatible = "renesas,r8a77961-cmt1", 509 "renesas,rcar-gen3-cmt1"; 510 reg = <0 0xe6148000 0 0x1004>; 511 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&cpg CPG_MOD 300>; 520 clock-names = "fck"; 521 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 522 resets = <&cpg 300>; 523 status = "disabled"; 524 }; 525 526 cpg: clock-controller@e6150000 { 527 compatible = "renesas,r8a77961-cpg-mssr"; 528 reg = <0 0xe6150000 0 0x1000>; 529 clocks = <&extal_clk>, <&extalr_clk>; 530 clock-names = "extal", "extalr"; 531 #clock-cells = <2>; 532 #power-domain-cells = <0>; 533 #reset-cells = <1>; 534 }; 535 536 rst: reset-controller@e6160000 { 537 compatible = "renesas,r8a77961-rst"; 538 reg = <0 0xe6160000 0 0x0200>; 539 }; 540 541 sysc: system-controller@e6180000 { 542 compatible = "renesas,r8a77961-sysc"; 543 reg = <0 0xe6180000 0 0x0400>; 544 #power-domain-cells = <1>; 545 }; 546 547 tsc: thermal@e6198000 { 548 compatible = "renesas,r8a77961-thermal"; 549 reg = <0 0xe6198000 0 0x100>, 550 <0 0xe61a0000 0 0x100>, 551 <0 0xe61a8000 0 0x100>; 552 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&cpg CPG_MOD 522>; 556 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 557 resets = <&cpg 522>; 558 #thermal-sensor-cells = <1>; 559 }; 560 561 intc_ex: interrupt-controller@e61c0000 { 562 #interrupt-cells = <2>; 563 interrupt-controller; 564 reg = <0 0xe61c0000 0 0x200>; 565 /* placeholder */ 566 }; 567 568 tmu0: timer@e61e0000 { 569 compatible = "renesas,tmu-r8a77961", "renesas,tmu"; 570 reg = <0 0xe61e0000 0 0x30>; 571 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&cpg CPG_MOD 125>; 575 clock-names = "fck"; 576 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 577 resets = <&cpg 125>; 578 status = "disabled"; 579 }; 580 581 tmu1: timer@e6fc0000 { 582 compatible = "renesas,tmu-r8a77961", "renesas,tmu"; 583 reg = <0 0xe6fc0000 0 0x30>; 584 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&cpg CPG_MOD 124>; 588 clock-names = "fck"; 589 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 590 resets = <&cpg 124>; 591 status = "disabled"; 592 }; 593 594 tmu2: timer@e6fd0000 { 595 compatible = "renesas,tmu-r8a77961", "renesas,tmu"; 596 reg = <0 0xe6fd0000 0 0x30>; 597 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 600 clocks = <&cpg CPG_MOD 123>; 601 clock-names = "fck"; 602 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 603 resets = <&cpg 123>; 604 status = "disabled"; 605 }; 606 607 tmu3: timer@e6fe0000 { 608 compatible = "renesas,tmu-r8a77961", "renesas,tmu"; 609 reg = <0 0xe6fe0000 0 0x30>; 610 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&cpg CPG_MOD 122>; 614 clock-names = "fck"; 615 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 616 resets = <&cpg 122>; 617 status = "disabled"; 618 }; 619 620 tmu4: timer@ffc00000 { 621 compatible = "renesas,tmu-r8a77961", "renesas,tmu"; 622 reg = <0 0xffc00000 0 0x30>; 623 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&cpg CPG_MOD 121>; 627 clock-names = "fck"; 628 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 629 resets = <&cpg 121>; 630 status = "disabled"; 631 }; 632 633 i2c0: i2c@e6500000 { 634 #address-cells = <1>; 635 #size-cells = <0>; 636 compatible = "renesas,i2c-r8a77961", 637 "renesas,rcar-gen3-i2c"; 638 reg = <0 0xe6500000 0 0x40>; 639 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&cpg CPG_MOD 931>; 641 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 642 resets = <&cpg 931>; 643 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 644 <&dmac2 0x91>, <&dmac2 0x90>; 645 dma-names = "tx", "rx", "tx", "rx"; 646 i2c-scl-internal-delay-ns = <110>; 647 status = "disabled"; 648 }; 649 650 i2c1: i2c@e6508000 { 651 #address-cells = <1>; 652 #size-cells = <0>; 653 compatible = "renesas,i2c-r8a77961", 654 "renesas,rcar-gen3-i2c"; 655 reg = <0 0xe6508000 0 0x40>; 656 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 657 clocks = <&cpg CPG_MOD 930>; 658 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 659 resets = <&cpg 930>; 660 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 661 <&dmac2 0x93>, <&dmac2 0x92>; 662 dma-names = "tx", "rx", "tx", "rx"; 663 i2c-scl-internal-delay-ns = <6>; 664 status = "disabled"; 665 }; 666 667 i2c2: i2c@e6510000 { 668 #address-cells = <1>; 669 #size-cells = <0>; 670 compatible = "renesas,i2c-r8a77961", 671 "renesas,rcar-gen3-i2c"; 672 reg = <0 0xe6510000 0 0x40>; 673 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 674 clocks = <&cpg CPG_MOD 929>; 675 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 676 resets = <&cpg 929>; 677 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 678 <&dmac2 0x95>, <&dmac2 0x94>; 679 dma-names = "tx", "rx", "tx", "rx"; 680 i2c-scl-internal-delay-ns = <6>; 681 status = "disabled"; 682 }; 683 684 i2c3: i2c@e66d0000 { 685 #address-cells = <1>; 686 #size-cells = <0>; 687 compatible = "renesas,i2c-r8a77961", 688 "renesas,rcar-gen3-i2c"; 689 reg = <0 0xe66d0000 0 0x40>; 690 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 691 clocks = <&cpg CPG_MOD 928>; 692 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 693 resets = <&cpg 928>; 694 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 695 dma-names = "tx", "rx"; 696 i2c-scl-internal-delay-ns = <110>; 697 status = "disabled"; 698 }; 699 700 i2c4: i2c@e66d8000 { 701 #address-cells = <1>; 702 #size-cells = <0>; 703 compatible = "renesas,i2c-r8a77961", 704 "renesas,rcar-gen3-i2c"; 705 reg = <0 0xe66d8000 0 0x40>; 706 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&cpg CPG_MOD 927>; 708 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 709 resets = <&cpg 927>; 710 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 711 dma-names = "tx", "rx"; 712 i2c-scl-internal-delay-ns = <110>; 713 status = "disabled"; 714 }; 715 716 i2c5: i2c@e66e0000 { 717 #address-cells = <1>; 718 #size-cells = <0>; 719 compatible = "renesas,i2c-r8a77961", 720 "renesas,rcar-gen3-i2c"; 721 reg = <0 0xe66e0000 0 0x40>; 722 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&cpg CPG_MOD 919>; 724 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 725 resets = <&cpg 919>; 726 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 727 dma-names = "tx", "rx"; 728 i2c-scl-internal-delay-ns = <110>; 729 status = "disabled"; 730 }; 731 732 i2c6: i2c@e66e8000 { 733 #address-cells = <1>; 734 #size-cells = <0>; 735 compatible = "renesas,i2c-r8a77961", 736 "renesas,rcar-gen3-i2c"; 737 reg = <0 0xe66e8000 0 0x40>; 738 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&cpg CPG_MOD 918>; 740 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 741 resets = <&cpg 918>; 742 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 743 dma-names = "tx", "rx"; 744 i2c-scl-internal-delay-ns = <6>; 745 status = "disabled"; 746 }; 747 748 i2c_dvfs: i2c@e60b0000 { 749 #address-cells = <1>; 750 #size-cells = <0>; 751 compatible = "renesas,iic-r8a77961", 752 "renesas,rcar-gen3-iic", 753 "renesas,rmobile-iic"; 754 reg = <0 0xe60b0000 0 0x425>; 755 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&cpg CPG_MOD 926>; 757 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 758 resets = <&cpg 926>; 759 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 760 dma-names = "tx", "rx"; 761 status = "disabled"; 762 }; 763 764 hscif0: serial@e6540000 { 765 compatible = "renesas,hscif-r8a77961", 766 "renesas,rcar-gen3-hscif", 767 "renesas,hscif"; 768 reg = <0 0xe6540000 0 0x60>; 769 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 770 clocks = <&cpg CPG_MOD 520>, 771 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 772 <&scif_clk>; 773 clock-names = "fck", "brg_int", "scif_clk"; 774 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 775 <&dmac2 0x31>, <&dmac2 0x30>; 776 dma-names = "tx", "rx", "tx", "rx"; 777 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 778 resets = <&cpg 520>; 779 status = "disabled"; 780 }; 781 782 hscif1: serial@e6550000 { 783 compatible = "renesas,hscif-r8a77961", 784 "renesas,rcar-gen3-hscif", 785 "renesas,hscif"; 786 reg = <0 0xe6550000 0 0x60>; 787 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&cpg CPG_MOD 519>, 789 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 790 <&scif_clk>; 791 clock-names = "fck", "brg_int", "scif_clk"; 792 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 793 <&dmac2 0x33>, <&dmac2 0x32>; 794 dma-names = "tx", "rx", "tx", "rx"; 795 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 796 resets = <&cpg 519>; 797 status = "disabled"; 798 }; 799 800 hscif2: serial@e6560000 { 801 compatible = "renesas,hscif-r8a77961", 802 "renesas,rcar-gen3-hscif", 803 "renesas,hscif"; 804 reg = <0 0xe6560000 0 0x60>; 805 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 806 clocks = <&cpg CPG_MOD 518>, 807 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 808 <&scif_clk>; 809 clock-names = "fck", "brg_int", "scif_clk"; 810 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 811 <&dmac2 0x35>, <&dmac2 0x34>; 812 dma-names = "tx", "rx", "tx", "rx"; 813 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 814 resets = <&cpg 518>; 815 status = "disabled"; 816 }; 817 818 hscif3: serial@e66a0000 { 819 compatible = "renesas,hscif-r8a77961", 820 "renesas,rcar-gen3-hscif", 821 "renesas,hscif"; 822 reg = <0 0xe66a0000 0 0x60>; 823 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&cpg CPG_MOD 517>, 825 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 826 <&scif_clk>; 827 clock-names = "fck", "brg_int", "scif_clk"; 828 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 829 dma-names = "tx", "rx"; 830 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 831 resets = <&cpg 517>; 832 status = "disabled"; 833 }; 834 835 hscif4: serial@e66b0000 { 836 compatible = "renesas,hscif-r8a77961", 837 "renesas,rcar-gen3-hscif", 838 "renesas,hscif"; 839 reg = <0 0xe66b0000 0 0x60>; 840 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 841 clocks = <&cpg CPG_MOD 516>, 842 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 843 <&scif_clk>; 844 clock-names = "fck", "brg_int", "scif_clk"; 845 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 846 dma-names = "tx", "rx"; 847 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 848 resets = <&cpg 516>; 849 status = "disabled"; 850 }; 851 852 hsusb: usb@e6590000 { 853 compatible = "renesas,usbhs-r8a77961", 854 "renesas,rcar-gen3-usbhs"; 855 reg = <0 0xe6590000 0 0x200>; 856 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 857 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 858 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 859 <&usb_dmac1 0>, <&usb_dmac1 1>; 860 dma-names = "ch0", "ch1", "ch2", "ch3"; 861 renesas,buswait = <11>; 862 phys = <&usb2_phy0 3>; 863 phy-names = "usb"; 864 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 865 resets = <&cpg 704>, <&cpg 703>; 866 status = "disabled"; 867 }; 868 869 usb_dmac0: dma-controller@e65a0000 { 870 compatible = "renesas,r8a77961-usb-dmac", 871 "renesas,usb-dmac"; 872 reg = <0 0xe65a0000 0 0x100>; 873 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 875 interrupt-names = "ch0", "ch1"; 876 clocks = <&cpg CPG_MOD 330>; 877 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 878 resets = <&cpg 330>; 879 #dma-cells = <1>; 880 dma-channels = <2>; 881 }; 882 883 usb_dmac1: dma-controller@e65b0000 { 884 compatible = "renesas,r8a77961-usb-dmac", 885 "renesas,usb-dmac"; 886 reg = <0 0xe65b0000 0 0x100>; 887 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 889 interrupt-names = "ch0", "ch1"; 890 clocks = <&cpg CPG_MOD 331>; 891 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 892 resets = <&cpg 331>; 893 #dma-cells = <1>; 894 dma-channels = <2>; 895 }; 896 897 usb3_phy0: usb-phy@e65ee000 { 898 compatible = "renesas,r8a77961-usb3-phy", 899 "renesas,rcar-gen3-usb3-phy"; 900 reg = <0 0xe65ee000 0 0x90>; 901 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 902 <&usb_extal_clk>; 903 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 904 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 905 resets = <&cpg 328>; 906 #phy-cells = <0>; 907 status = "disabled"; 908 }; 909 910 arm_cc630p: crypto@e6601000 { 911 compatible = "arm,cryptocell-630p-ree"; 912 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 913 reg = <0x0 0xe6601000 0 0x1000>; 914 clocks = <&cpg CPG_MOD 229>; 915 resets = <&cpg 229>; 916 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 917 }; 918 919 dmac0: dma-controller@e6700000 { 920 compatible = "renesas,dmac-r8a77961", 921 "renesas,rcar-dmac"; 922 reg = <0 0xe6700000 0 0x10000>; 923 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 940 interrupt-names = "error", 941 "ch0", "ch1", "ch2", "ch3", 942 "ch4", "ch5", "ch6", "ch7", 943 "ch8", "ch9", "ch10", "ch11", 944 "ch12", "ch13", "ch14", "ch15"; 945 clocks = <&cpg CPG_MOD 219>; 946 clock-names = "fck"; 947 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 948 resets = <&cpg 219>; 949 #dma-cells = <1>; 950 dma-channels = <16>; 951 }; 952 953 dmac1: dma-controller@e7300000 { 954 compatible = "renesas,dmac-r8a77961", 955 "renesas,rcar-dmac"; 956 reg = <0 0xe7300000 0 0x10000>; 957 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 974 interrupt-names = "error", 975 "ch0", "ch1", "ch2", "ch3", 976 "ch4", "ch5", "ch6", "ch7", 977 "ch8", "ch9", "ch10", "ch11", 978 "ch12", "ch13", "ch14", "ch15"; 979 clocks = <&cpg CPG_MOD 218>; 980 clock-names = "fck"; 981 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 982 resets = <&cpg 218>; 983 #dma-cells = <1>; 984 dma-channels = <16>; 985 }; 986 987 dmac2: dma-controller@e7310000 { 988 compatible = "renesas,dmac-r8a77961", 989 "renesas,rcar-dmac"; 990 reg = <0 0xe7310000 0 0x10000>; 991 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 1001 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 1002 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 1003 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 1004 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 1005 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 1006 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 1007 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 1008 interrupt-names = "error", 1009 "ch0", "ch1", "ch2", "ch3", 1010 "ch4", "ch5", "ch6", "ch7", 1011 "ch8", "ch9", "ch10", "ch11", 1012 "ch12", "ch13", "ch14", "ch15"; 1013 clocks = <&cpg CPG_MOD 217>; 1014 clock-names = "fck"; 1015 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1016 resets = <&cpg 217>; 1017 #dma-cells = <1>; 1018 dma-channels = <16>; 1019 }; 1020 1021 ipmmu_ds0: iommu@e6740000 { 1022 compatible = "renesas,ipmmu-r8a77961"; 1023 reg = <0 0xe6740000 0 0x1000>; 1024 renesas,ipmmu-main = <&ipmmu_mm 0>; 1025 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1026 #iommu-cells = <1>; 1027 }; 1028 1029 ipmmu_ds1: iommu@e7740000 { 1030 compatible = "renesas,ipmmu-r8a77961"; 1031 reg = <0 0xe7740000 0 0x1000>; 1032 renesas,ipmmu-main = <&ipmmu_mm 1>; 1033 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1034 #iommu-cells = <1>; 1035 }; 1036 1037 ipmmu_hc: iommu@e6570000 { 1038 compatible = "renesas,ipmmu-r8a77961"; 1039 reg = <0 0xe6570000 0 0x1000>; 1040 renesas,ipmmu-main = <&ipmmu_mm 2>; 1041 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1042 #iommu-cells = <1>; 1043 }; 1044 1045 ipmmu_ir: iommu@ff8b0000 { 1046 compatible = "renesas,ipmmu-r8a77961"; 1047 reg = <0 0xff8b0000 0 0x1000>; 1048 renesas,ipmmu-main = <&ipmmu_mm 3>; 1049 power-domains = <&sysc R8A77961_PD_A3IR>; 1050 #iommu-cells = <1>; 1051 }; 1052 1053 ipmmu_mm: iommu@e67b0000 { 1054 compatible = "renesas,ipmmu-r8a77961"; 1055 reg = <0 0xe67b0000 0 0x1000>; 1056 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1058 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1059 #iommu-cells = <1>; 1060 }; 1061 1062 ipmmu_mp: iommu@ec670000 { 1063 compatible = "renesas,ipmmu-r8a77961"; 1064 reg = <0 0xec670000 0 0x1000>; 1065 renesas,ipmmu-main = <&ipmmu_mm 4>; 1066 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1067 #iommu-cells = <1>; 1068 }; 1069 1070 ipmmu_pv0: iommu@fd800000 { 1071 compatible = "renesas,ipmmu-r8a77961"; 1072 reg = <0 0xfd800000 0 0x1000>; 1073 renesas,ipmmu-main = <&ipmmu_mm 5>; 1074 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1075 #iommu-cells = <1>; 1076 }; 1077 1078 ipmmu_pv1: iommu@fd950000 { 1079 compatible = "renesas,ipmmu-r8a77961"; 1080 reg = <0 0xfd950000 0 0x1000>; 1081 renesas,ipmmu-main = <&ipmmu_mm 6>; 1082 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1083 #iommu-cells = <1>; 1084 }; 1085 1086 ipmmu_rt: iommu@ffc80000 { 1087 compatible = "renesas,ipmmu-r8a77961"; 1088 reg = <0 0xffc80000 0 0x1000>; 1089 renesas,ipmmu-main = <&ipmmu_mm 7>; 1090 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1091 #iommu-cells = <1>; 1092 }; 1093 1094 ipmmu_vc0: iommu@fe6b0000 { 1095 compatible = "renesas,ipmmu-r8a77961"; 1096 reg = <0 0xfe6b0000 0 0x1000>; 1097 renesas,ipmmu-main = <&ipmmu_mm 8>; 1098 power-domains = <&sysc R8A77961_PD_A3VC>; 1099 #iommu-cells = <1>; 1100 }; 1101 1102 ipmmu_vi0: iommu@febd0000 { 1103 compatible = "renesas,ipmmu-r8a77961"; 1104 reg = <0 0xfebd0000 0 0x1000>; 1105 renesas,ipmmu-main = <&ipmmu_mm 9>; 1106 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1107 #iommu-cells = <1>; 1108 }; 1109 1110 avb: ethernet@e6800000 { 1111 compatible = "renesas,etheravb-r8a77961", 1112 "renesas,etheravb-rcar-gen3"; 1113 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 1114 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1139 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1140 "ch4", "ch5", "ch6", "ch7", 1141 "ch8", "ch9", "ch10", "ch11", 1142 "ch12", "ch13", "ch14", "ch15", 1143 "ch16", "ch17", "ch18", "ch19", 1144 "ch20", "ch21", "ch22", "ch23", 1145 "ch24"; 1146 clocks = <&cpg CPG_MOD 812>; 1147 clock-names = "fck"; 1148 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1149 resets = <&cpg 812>; 1150 phy-mode = "rgmii"; 1151 rx-internal-delay-ps = <0>; 1152 tx-internal-delay-ps = <0>; 1153 #address-cells = <1>; 1154 #size-cells = <0>; 1155 status = "disabled"; 1156 }; 1157 1158 can0: can@e6c30000 { 1159 compatible = "renesas,can-r8a77961", 1160 "renesas,rcar-gen3-can"; 1161 reg = <0 0xe6c30000 0 0x1000>; 1162 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1163 clocks = <&cpg CPG_MOD 916>, 1164 <&cpg CPG_CORE R8A77961_CLK_CANFD>, 1165 <&can_clk>; 1166 clock-names = "clkp1", "clkp2", "can_clk"; 1167 assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>; 1168 assigned-clock-rates = <40000000>; 1169 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1170 resets = <&cpg 916>; 1171 status = "disabled"; 1172 }; 1173 1174 can1: can@e6c38000 { 1175 compatible = "renesas,can-r8a77961", 1176 "renesas,rcar-gen3-can"; 1177 reg = <0 0xe6c38000 0 0x1000>; 1178 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1179 clocks = <&cpg CPG_MOD 915>, 1180 <&cpg CPG_CORE R8A77961_CLK_CANFD>, 1181 <&can_clk>; 1182 clock-names = "clkp1", "clkp2", "can_clk"; 1183 assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>; 1184 assigned-clock-rates = <40000000>; 1185 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1186 resets = <&cpg 915>; 1187 status = "disabled"; 1188 }; 1189 1190 pwm0: pwm@e6e30000 { 1191 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1192 reg = <0 0xe6e30000 0 8>; 1193 #pwm-cells = <2>; 1194 clocks = <&cpg CPG_MOD 523>; 1195 resets = <&cpg 523>; 1196 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1197 status = "disabled"; 1198 }; 1199 1200 pwm1: pwm@e6e31000 { 1201 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1202 reg = <0 0xe6e31000 0 8>; 1203 #pwm-cells = <2>; 1204 clocks = <&cpg CPG_MOD 523>; 1205 resets = <&cpg 523>; 1206 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1207 status = "disabled"; 1208 }; 1209 1210 pwm2: pwm@e6e32000 { 1211 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1212 reg = <0 0xe6e32000 0 8>; 1213 #pwm-cells = <2>; 1214 clocks = <&cpg CPG_MOD 523>; 1215 resets = <&cpg 523>; 1216 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1217 status = "disabled"; 1218 }; 1219 1220 pwm3: pwm@e6e33000 { 1221 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1222 reg = <0 0xe6e33000 0 8>; 1223 #pwm-cells = <2>; 1224 clocks = <&cpg CPG_MOD 523>; 1225 resets = <&cpg 523>; 1226 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1227 status = "disabled"; 1228 }; 1229 1230 pwm4: pwm@e6e34000 { 1231 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1232 reg = <0 0xe6e34000 0 8>; 1233 #pwm-cells = <2>; 1234 clocks = <&cpg CPG_MOD 523>; 1235 resets = <&cpg 523>; 1236 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1237 status = "disabled"; 1238 }; 1239 1240 pwm5: pwm@e6e35000 { 1241 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1242 reg = <0 0xe6e35000 0 8>; 1243 #pwm-cells = <2>; 1244 clocks = <&cpg CPG_MOD 523>; 1245 resets = <&cpg 523>; 1246 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1247 status = "disabled"; 1248 }; 1249 1250 pwm6: pwm@e6e36000 { 1251 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1252 reg = <0 0xe6e36000 0 8>; 1253 #pwm-cells = <2>; 1254 clocks = <&cpg CPG_MOD 523>; 1255 resets = <&cpg 523>; 1256 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1257 status = "disabled"; 1258 }; 1259 1260 scif0: serial@e6e60000 { 1261 compatible = "renesas,scif-r8a77961", 1262 "renesas,rcar-gen3-scif", "renesas,scif"; 1263 reg = <0 0xe6e60000 0 64>; 1264 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1265 clocks = <&cpg CPG_MOD 207>, 1266 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1267 <&scif_clk>; 1268 clock-names = "fck", "brg_int", "scif_clk"; 1269 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1270 <&dmac2 0x51>, <&dmac2 0x50>; 1271 dma-names = "tx", "rx", "tx", "rx"; 1272 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1273 resets = <&cpg 207>; 1274 status = "disabled"; 1275 }; 1276 1277 scif1: serial@e6e68000 { 1278 compatible = "renesas,scif-r8a77961", 1279 "renesas,rcar-gen3-scif", "renesas,scif"; 1280 reg = <0 0xe6e68000 0 64>; 1281 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1282 clocks = <&cpg CPG_MOD 206>, 1283 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1284 <&scif_clk>; 1285 clock-names = "fck", "brg_int", "scif_clk"; 1286 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1287 <&dmac2 0x53>, <&dmac2 0x52>; 1288 dma-names = "tx", "rx", "tx", "rx"; 1289 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1290 resets = <&cpg 206>; 1291 status = "disabled"; 1292 }; 1293 1294 scif2: serial@e6e88000 { 1295 compatible = "renesas,scif-r8a77961", 1296 "renesas,rcar-gen3-scif", "renesas,scif"; 1297 reg = <0 0xe6e88000 0 64>; 1298 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1299 clocks = <&cpg CPG_MOD 310>, 1300 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1301 <&scif_clk>; 1302 clock-names = "fck", "brg_int", "scif_clk"; 1303 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1304 <&dmac2 0x13>, <&dmac2 0x12>; 1305 dma-names = "tx", "rx", "tx", "rx"; 1306 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1307 resets = <&cpg 310>; 1308 status = "disabled"; 1309 }; 1310 1311 scif3: serial@e6c50000 { 1312 compatible = "renesas,scif-r8a77961", 1313 "renesas,rcar-gen3-scif", "renesas,scif"; 1314 reg = <0 0xe6c50000 0 64>; 1315 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1316 clocks = <&cpg CPG_MOD 204>, 1317 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1318 <&scif_clk>; 1319 clock-names = "fck", "brg_int", "scif_clk"; 1320 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1321 dma-names = "tx", "rx"; 1322 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1323 resets = <&cpg 204>; 1324 status = "disabled"; 1325 }; 1326 1327 scif4: serial@e6c40000 { 1328 compatible = "renesas,scif-r8a77961", 1329 "renesas,rcar-gen3-scif", "renesas,scif"; 1330 reg = <0 0xe6c40000 0 64>; 1331 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1332 clocks = <&cpg CPG_MOD 203>, 1333 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1334 <&scif_clk>; 1335 clock-names = "fck", "brg_int", "scif_clk"; 1336 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1337 dma-names = "tx", "rx"; 1338 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1339 resets = <&cpg 203>; 1340 status = "disabled"; 1341 }; 1342 1343 scif5: serial@e6f30000 { 1344 compatible = "renesas,scif-r8a77961", 1345 "renesas,rcar-gen3-scif", "renesas,scif"; 1346 reg = <0 0xe6f30000 0 64>; 1347 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1348 clocks = <&cpg CPG_MOD 202>, 1349 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1350 <&scif_clk>; 1351 clock-names = "fck", "brg_int", "scif_clk"; 1352 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1353 <&dmac2 0x5b>, <&dmac2 0x5a>; 1354 dma-names = "tx", "rx", "tx", "rx"; 1355 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1356 resets = <&cpg 202>; 1357 status = "disabled"; 1358 }; 1359 1360 msiof0: spi@e6e90000 { 1361 compatible = "renesas,msiof-r8a77961", 1362 "renesas,rcar-gen3-msiof"; 1363 reg = <0 0xe6e90000 0 0x0064>; 1364 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1365 clocks = <&cpg CPG_MOD 211>; 1366 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1367 <&dmac2 0x41>, <&dmac2 0x40>; 1368 dma-names = "tx", "rx", "tx", "rx"; 1369 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1370 resets = <&cpg 211>; 1371 #address-cells = <1>; 1372 #size-cells = <0>; 1373 status = "disabled"; 1374 }; 1375 1376 msiof1: spi@e6ea0000 { 1377 compatible = "renesas,msiof-r8a77961", 1378 "renesas,rcar-gen3-msiof"; 1379 reg = <0 0xe6ea0000 0 0x0064>; 1380 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1381 clocks = <&cpg CPG_MOD 210>; 1382 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1383 <&dmac2 0x43>, <&dmac2 0x42>; 1384 dma-names = "tx", "rx", "tx", "rx"; 1385 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1386 resets = <&cpg 210>; 1387 #address-cells = <1>; 1388 #size-cells = <0>; 1389 status = "disabled"; 1390 }; 1391 1392 msiof2: spi@e6c00000 { 1393 compatible = "renesas,msiof-r8a77961", 1394 "renesas,rcar-gen3-msiof"; 1395 reg = <0 0xe6c00000 0 0x0064>; 1396 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1397 clocks = <&cpg CPG_MOD 209>; 1398 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1399 dma-names = "tx", "rx"; 1400 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1401 resets = <&cpg 209>; 1402 #address-cells = <1>; 1403 #size-cells = <0>; 1404 status = "disabled"; 1405 }; 1406 1407 msiof3: spi@e6c10000 { 1408 compatible = "renesas,msiof-r8a77961", 1409 "renesas,rcar-gen3-msiof"; 1410 reg = <0 0xe6c10000 0 0x0064>; 1411 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1412 clocks = <&cpg CPG_MOD 208>; 1413 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1414 dma-names = "tx", "rx"; 1415 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1416 resets = <&cpg 208>; 1417 #address-cells = <1>; 1418 #size-cells = <0>; 1419 status = "disabled"; 1420 }; 1421 1422 vin0: video@e6ef0000 { 1423 compatible = "renesas,vin-r8a77961"; 1424 reg = <0 0xe6ef0000 0 0x1000>; 1425 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1426 clocks = <&cpg CPG_MOD 811>; 1427 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1428 resets = <&cpg 811>; 1429 renesas,id = <0>; 1430 status = "disabled"; 1431 1432 ports { 1433 #address-cells = <1>; 1434 #size-cells = <0>; 1435 1436 port@1 { 1437 #address-cells = <1>; 1438 #size-cells = <0>; 1439 1440 reg = <1>; 1441 1442 vin0csi20: endpoint@0 { 1443 reg = <0>; 1444 remote-endpoint = <&csi20vin0>; 1445 }; 1446 vin0csi40: endpoint@2 { 1447 reg = <2>; 1448 remote-endpoint = <&csi40vin0>; 1449 }; 1450 }; 1451 }; 1452 }; 1453 1454 vin1: video@e6ef1000 { 1455 compatible = "renesas,vin-r8a77961"; 1456 reg = <0 0xe6ef1000 0 0x1000>; 1457 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1458 clocks = <&cpg CPG_MOD 810>; 1459 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1460 resets = <&cpg 810>; 1461 renesas,id = <1>; 1462 status = "disabled"; 1463 1464 ports { 1465 #address-cells = <1>; 1466 #size-cells = <0>; 1467 1468 port@1 { 1469 #address-cells = <1>; 1470 #size-cells = <0>; 1471 1472 reg = <1>; 1473 1474 vin1csi20: endpoint@0 { 1475 reg = <0>; 1476 remote-endpoint = <&csi20vin1>; 1477 }; 1478 vin1csi40: endpoint@2 { 1479 reg = <2>; 1480 remote-endpoint = <&csi40vin1>; 1481 }; 1482 }; 1483 }; 1484 }; 1485 1486 vin2: video@e6ef2000 { 1487 compatible = "renesas,vin-r8a77961"; 1488 reg = <0 0xe6ef2000 0 0x1000>; 1489 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1490 clocks = <&cpg CPG_MOD 809>; 1491 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1492 resets = <&cpg 809>; 1493 renesas,id = <2>; 1494 status = "disabled"; 1495 1496 ports { 1497 #address-cells = <1>; 1498 #size-cells = <0>; 1499 1500 port@1 { 1501 #address-cells = <1>; 1502 #size-cells = <0>; 1503 1504 reg = <1>; 1505 1506 vin2csi20: endpoint@0 { 1507 reg = <0>; 1508 remote-endpoint = <&csi20vin2>; 1509 }; 1510 vin2csi40: endpoint@2 { 1511 reg = <2>; 1512 remote-endpoint = <&csi40vin2>; 1513 }; 1514 }; 1515 }; 1516 }; 1517 1518 vin3: video@e6ef3000 { 1519 compatible = "renesas,vin-r8a77961"; 1520 reg = <0 0xe6ef3000 0 0x1000>; 1521 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1522 clocks = <&cpg CPG_MOD 808>; 1523 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1524 resets = <&cpg 808>; 1525 renesas,id = <3>; 1526 status = "disabled"; 1527 1528 ports { 1529 #address-cells = <1>; 1530 #size-cells = <0>; 1531 1532 port@1 { 1533 #address-cells = <1>; 1534 #size-cells = <0>; 1535 1536 reg = <1>; 1537 1538 vin3csi20: endpoint@0 { 1539 reg = <0>; 1540 remote-endpoint = <&csi20vin3>; 1541 }; 1542 vin3csi40: endpoint@2 { 1543 reg = <2>; 1544 remote-endpoint = <&csi40vin3>; 1545 }; 1546 }; 1547 }; 1548 }; 1549 1550 vin4: video@e6ef4000 { 1551 compatible = "renesas,vin-r8a77961"; 1552 reg = <0 0xe6ef4000 0 0x1000>; 1553 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1554 clocks = <&cpg CPG_MOD 807>; 1555 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1556 resets = <&cpg 807>; 1557 renesas,id = <4>; 1558 status = "disabled"; 1559 1560 ports { 1561 #address-cells = <1>; 1562 #size-cells = <0>; 1563 1564 port@1 { 1565 #address-cells = <1>; 1566 #size-cells = <0>; 1567 1568 reg = <1>; 1569 1570 vin4csi20: endpoint@0 { 1571 reg = <0>; 1572 remote-endpoint = <&csi20vin4>; 1573 }; 1574 vin4csi40: endpoint@2 { 1575 reg = <2>; 1576 remote-endpoint = <&csi40vin4>; 1577 }; 1578 }; 1579 }; 1580 }; 1581 1582 vin5: video@e6ef5000 { 1583 compatible = "renesas,vin-r8a77961"; 1584 reg = <0 0xe6ef5000 0 0x1000>; 1585 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1586 clocks = <&cpg CPG_MOD 806>; 1587 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1588 resets = <&cpg 806>; 1589 renesas,id = <5>; 1590 status = "disabled"; 1591 1592 ports { 1593 #address-cells = <1>; 1594 #size-cells = <0>; 1595 1596 port@1 { 1597 #address-cells = <1>; 1598 #size-cells = <0>; 1599 1600 reg = <1>; 1601 1602 vin5csi20: endpoint@0 { 1603 reg = <0>; 1604 remote-endpoint = <&csi20vin5>; 1605 }; 1606 vin5csi40: endpoint@2 { 1607 reg = <2>; 1608 remote-endpoint = <&csi40vin5>; 1609 }; 1610 }; 1611 }; 1612 }; 1613 1614 vin6: video@e6ef6000 { 1615 compatible = "renesas,vin-r8a77961"; 1616 reg = <0 0xe6ef6000 0 0x1000>; 1617 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1618 clocks = <&cpg CPG_MOD 805>; 1619 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1620 resets = <&cpg 805>; 1621 renesas,id = <6>; 1622 status = "disabled"; 1623 1624 ports { 1625 #address-cells = <1>; 1626 #size-cells = <0>; 1627 1628 port@1 { 1629 #address-cells = <1>; 1630 #size-cells = <0>; 1631 1632 reg = <1>; 1633 1634 vin6csi20: endpoint@0 { 1635 reg = <0>; 1636 remote-endpoint = <&csi20vin6>; 1637 }; 1638 vin6csi40: endpoint@2 { 1639 reg = <2>; 1640 remote-endpoint = <&csi40vin6>; 1641 }; 1642 }; 1643 }; 1644 }; 1645 1646 vin7: video@e6ef7000 { 1647 compatible = "renesas,vin-r8a77961"; 1648 reg = <0 0xe6ef7000 0 0x1000>; 1649 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 1650 clocks = <&cpg CPG_MOD 804>; 1651 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1652 resets = <&cpg 804>; 1653 renesas,id = <7>; 1654 status = "disabled"; 1655 1656 ports { 1657 #address-cells = <1>; 1658 #size-cells = <0>; 1659 1660 port@1 { 1661 #address-cells = <1>; 1662 #size-cells = <0>; 1663 1664 reg = <1>; 1665 1666 vin7csi20: endpoint@0 { 1667 reg = <0>; 1668 remote-endpoint = <&csi20vin7>; 1669 }; 1670 vin7csi40: endpoint@2 { 1671 reg = <2>; 1672 remote-endpoint = <&csi40vin7>; 1673 }; 1674 }; 1675 }; 1676 }; 1677 1678 rcar_sound: sound@ec500000 { 1679 /* 1680 * #sound-dai-cells is required 1681 * 1682 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1683 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1684 */ 1685 /* 1686 * #clock-cells is required for audio_clkout0/1/2/3 1687 * 1688 * clkout : #clock-cells = <0>; <&rcar_sound>; 1689 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1690 */ 1691 compatible = "renesas,rcar_sound-r8a77961", "renesas,rcar_sound-gen3"; 1692 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1693 <0 0xec5a0000 0 0x100>, /* ADG */ 1694 <0 0xec540000 0 0x1000>, /* SSIU */ 1695 <0 0xec541000 0 0x280>, /* SSI */ 1696 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1697 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1698 1699 clocks = <&cpg CPG_MOD 1005>, 1700 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1701 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1702 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1703 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1704 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1705 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1706 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1707 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1708 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1709 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1710 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1711 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1712 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1713 <&audio_clk_a>, <&audio_clk_b>, 1714 <&audio_clk_c>, 1715 <&cpg CPG_CORE R8A77961_CLK_S0D4>; 1716 clock-names = "ssi-all", 1717 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1718 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1719 "ssi.1", "ssi.0", 1720 "src.9", "src.8", "src.7", "src.6", 1721 "src.5", "src.4", "src.3", "src.2", 1722 "src.1", "src.0", 1723 "mix.1", "mix.0", 1724 "ctu.1", "ctu.0", 1725 "dvc.0", "dvc.1", 1726 "clk_a", "clk_b", "clk_c", "clk_i"; 1727 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1728 resets = <&cpg 1005>, 1729 <&cpg 1006>, <&cpg 1007>, 1730 <&cpg 1008>, <&cpg 1009>, 1731 <&cpg 1010>, <&cpg 1011>, 1732 <&cpg 1012>, <&cpg 1013>, 1733 <&cpg 1014>, <&cpg 1015>; 1734 reset-names = "ssi-all", 1735 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1736 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1737 "ssi.1", "ssi.0"; 1738 status = "disabled"; 1739 1740 rcar_sound,ctu { 1741 ctu00: ctu-0 { }; 1742 ctu01: ctu-1 { }; 1743 ctu02: ctu-2 { }; 1744 ctu03: ctu-3 { }; 1745 ctu10: ctu-4 { }; 1746 ctu11: ctu-5 { }; 1747 ctu12: ctu-6 { }; 1748 ctu13: ctu-7 { }; 1749 }; 1750 1751 rcar_sound,dvc { 1752 dvc0: dvc-0 { 1753 dmas = <&audma1 0xbc>; 1754 dma-names = "tx"; 1755 }; 1756 dvc1: dvc-1 { 1757 dmas = <&audma1 0xbe>; 1758 dma-names = "tx"; 1759 }; 1760 }; 1761 1762 rcar_sound,mix { 1763 mix0: mix-0 { }; 1764 mix1: mix-1 { }; 1765 }; 1766 1767 rcar_sound,src { 1768 src0: src-0 { 1769 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1770 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1771 dma-names = "rx", "tx"; 1772 }; 1773 src1: src-1 { 1774 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1775 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1776 dma-names = "rx", "tx"; 1777 }; 1778 src2: src-2 { 1779 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1780 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1781 dma-names = "rx", "tx"; 1782 }; 1783 src3: src-3 { 1784 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1785 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1786 dma-names = "rx", "tx"; 1787 }; 1788 src4: src-4 { 1789 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1790 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1791 dma-names = "rx", "tx"; 1792 }; 1793 src5: src-5 { 1794 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1795 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1796 dma-names = "rx", "tx"; 1797 }; 1798 src6: src-6 { 1799 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1800 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1801 dma-names = "rx", "tx"; 1802 }; 1803 src7: src-7 { 1804 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1805 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1806 dma-names = "rx", "tx"; 1807 }; 1808 src8: src-8 { 1809 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1810 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1811 dma-names = "rx", "tx"; 1812 }; 1813 src9: src-9 { 1814 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1815 dmas = <&audma0 0x97>, <&audma1 0xba>; 1816 dma-names = "rx", "tx"; 1817 }; 1818 }; 1819 1820 rcar_sound,ssi { 1821 ssi0: ssi-0 { 1822 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1823 dmas = <&audma0 0x01>, <&audma1 0x02>; 1824 dma-names = "rx", "tx"; 1825 }; 1826 ssi1: ssi-1 { 1827 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1828 dmas = <&audma0 0x03>, <&audma1 0x04>; 1829 dma-names = "rx", "tx"; 1830 }; 1831 ssi2: ssi-2 { 1832 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1833 dmas = <&audma0 0x05>, <&audma1 0x06>; 1834 dma-names = "rx", "tx"; 1835 }; 1836 ssi3: ssi-3 { 1837 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1838 dmas = <&audma0 0x07>, <&audma1 0x08>; 1839 dma-names = "rx", "tx"; 1840 }; 1841 ssi4: ssi-4 { 1842 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1843 dmas = <&audma0 0x09>, <&audma1 0x0a>; 1844 dma-names = "rx", "tx"; 1845 }; 1846 ssi5: ssi-5 { 1847 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1848 dmas = <&audma0 0x0b>, <&audma1 0x0c>; 1849 dma-names = "rx", "tx"; 1850 }; 1851 ssi6: ssi-6 { 1852 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1853 dmas = <&audma0 0x0d>, <&audma1 0x0e>; 1854 dma-names = "rx", "tx"; 1855 }; 1856 ssi7: ssi-7 { 1857 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1858 dmas = <&audma0 0x0f>, <&audma1 0x10>; 1859 dma-names = "rx", "tx"; 1860 }; 1861 ssi8: ssi-8 { 1862 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1863 dmas = <&audma0 0x11>, <&audma1 0x12>; 1864 dma-names = "rx", "tx"; 1865 }; 1866 ssi9: ssi-9 { 1867 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1868 dmas = <&audma0 0x13>, <&audma1 0x14>; 1869 dma-names = "rx", "tx"; 1870 }; 1871 }; 1872 1873 rcar_sound,ssiu { 1874 ssiu00: ssiu-0 { 1875 dmas = <&audma0 0x15>, <&audma1 0x16>; 1876 dma-names = "rx", "tx"; 1877 }; 1878 ssiu01: ssiu-1 { 1879 dmas = <&audma0 0x35>, <&audma1 0x36>; 1880 dma-names = "rx", "tx"; 1881 }; 1882 ssiu02: ssiu-2 { 1883 dmas = <&audma0 0x37>, <&audma1 0x38>; 1884 dma-names = "rx", "tx"; 1885 }; 1886 ssiu03: ssiu-3 { 1887 dmas = <&audma0 0x47>, <&audma1 0x48>; 1888 dma-names = "rx", "tx"; 1889 }; 1890 ssiu04: ssiu-4 { 1891 dmas = <&audma0 0x3F>, <&audma1 0x40>; 1892 dma-names = "rx", "tx"; 1893 }; 1894 ssiu05: ssiu-5 { 1895 dmas = <&audma0 0x43>, <&audma1 0x44>; 1896 dma-names = "rx", "tx"; 1897 }; 1898 ssiu06: ssiu-6 { 1899 dmas = <&audma0 0x4F>, <&audma1 0x50>; 1900 dma-names = "rx", "tx"; 1901 }; 1902 ssiu07: ssiu-7 { 1903 dmas = <&audma0 0x53>, <&audma1 0x54>; 1904 dma-names = "rx", "tx"; 1905 }; 1906 ssiu10: ssiu-8 { 1907 dmas = <&audma0 0x49>, <&audma1 0x4a>; 1908 dma-names = "rx", "tx"; 1909 }; 1910 ssiu11: ssiu-9 { 1911 dmas = <&audma0 0x4B>, <&audma1 0x4C>; 1912 dma-names = "rx", "tx"; 1913 }; 1914 ssiu12: ssiu-10 { 1915 dmas = <&audma0 0x57>, <&audma1 0x58>; 1916 dma-names = "rx", "tx"; 1917 }; 1918 ssiu13: ssiu-11 { 1919 dmas = <&audma0 0x59>, <&audma1 0x5A>; 1920 dma-names = "rx", "tx"; 1921 }; 1922 ssiu14: ssiu-12 { 1923 dmas = <&audma0 0x5F>, <&audma1 0x60>; 1924 dma-names = "rx", "tx"; 1925 }; 1926 ssiu15: ssiu-13 { 1927 dmas = <&audma0 0xC3>, <&audma1 0xC4>; 1928 dma-names = "rx", "tx"; 1929 }; 1930 ssiu16: ssiu-14 { 1931 dmas = <&audma0 0xC7>, <&audma1 0xC8>; 1932 dma-names = "rx", "tx"; 1933 }; 1934 ssiu17: ssiu-15 { 1935 dmas = <&audma0 0xCB>, <&audma1 0xCC>; 1936 dma-names = "rx", "tx"; 1937 }; 1938 ssiu20: ssiu-16 { 1939 dmas = <&audma0 0x63>, <&audma1 0x64>; 1940 dma-names = "rx", "tx"; 1941 }; 1942 ssiu21: ssiu-17 { 1943 dmas = <&audma0 0x67>, <&audma1 0x68>; 1944 dma-names = "rx", "tx"; 1945 }; 1946 ssiu22: ssiu-18 { 1947 dmas = <&audma0 0x6B>, <&audma1 0x6C>; 1948 dma-names = "rx", "tx"; 1949 }; 1950 ssiu23: ssiu-19 { 1951 dmas = <&audma0 0x6D>, <&audma1 0x6E>; 1952 dma-names = "rx", "tx"; 1953 }; 1954 ssiu24: ssiu-20 { 1955 dmas = <&audma0 0xCF>, <&audma1 0xCE>; 1956 dma-names = "rx", "tx"; 1957 }; 1958 ssiu25: ssiu-21 { 1959 dmas = <&audma0 0xEB>, <&audma1 0xEC>; 1960 dma-names = "rx", "tx"; 1961 }; 1962 ssiu26: ssiu-22 { 1963 dmas = <&audma0 0xED>, <&audma1 0xEE>; 1964 dma-names = "rx", "tx"; 1965 }; 1966 ssiu27: ssiu-23 { 1967 dmas = <&audma0 0xEF>, <&audma1 0xF0>; 1968 dma-names = "rx", "tx"; 1969 }; 1970 ssiu30: ssiu-24 { 1971 dmas = <&audma0 0x6f>, <&audma1 0x70>; 1972 dma-names = "rx", "tx"; 1973 }; 1974 ssiu31: ssiu-25 { 1975 dmas = <&audma0 0x21>, <&audma1 0x22>; 1976 dma-names = "rx", "tx"; 1977 }; 1978 ssiu32: ssiu-26 { 1979 dmas = <&audma0 0x23>, <&audma1 0x24>; 1980 dma-names = "rx", "tx"; 1981 }; 1982 ssiu33: ssiu-27 { 1983 dmas = <&audma0 0x25>, <&audma1 0x26>; 1984 dma-names = "rx", "tx"; 1985 }; 1986 ssiu34: ssiu-28 { 1987 dmas = <&audma0 0x27>, <&audma1 0x28>; 1988 dma-names = "rx", "tx"; 1989 }; 1990 ssiu35: ssiu-29 { 1991 dmas = <&audma0 0x29>, <&audma1 0x2A>; 1992 dma-names = "rx", "tx"; 1993 }; 1994 ssiu36: ssiu-30 { 1995 dmas = <&audma0 0x2B>, <&audma1 0x2C>; 1996 dma-names = "rx", "tx"; 1997 }; 1998 ssiu37: ssiu-31 { 1999 dmas = <&audma0 0x2D>, <&audma1 0x2E>; 2000 dma-names = "rx", "tx"; 2001 }; 2002 ssiu40: ssiu-32 { 2003 dmas = <&audma0 0x71>, <&audma1 0x72>; 2004 dma-names = "rx", "tx"; 2005 }; 2006 ssiu41: ssiu-33 { 2007 dmas = <&audma0 0x17>, <&audma1 0x18>; 2008 dma-names = "rx", "tx"; 2009 }; 2010 ssiu42: ssiu-34 { 2011 dmas = <&audma0 0x19>, <&audma1 0x1A>; 2012 dma-names = "rx", "tx"; 2013 }; 2014 ssiu43: ssiu-35 { 2015 dmas = <&audma0 0x1B>, <&audma1 0x1C>; 2016 dma-names = "rx", "tx"; 2017 }; 2018 ssiu44: ssiu-36 { 2019 dmas = <&audma0 0x1D>, <&audma1 0x1E>; 2020 dma-names = "rx", "tx"; 2021 }; 2022 ssiu45: ssiu-37 { 2023 dmas = <&audma0 0x1F>, <&audma1 0x20>; 2024 dma-names = "rx", "tx"; 2025 }; 2026 ssiu46: ssiu-38 { 2027 dmas = <&audma0 0x31>, <&audma1 0x32>; 2028 dma-names = "rx", "tx"; 2029 }; 2030 ssiu47: ssiu-39 { 2031 dmas = <&audma0 0x33>, <&audma1 0x34>; 2032 dma-names = "rx", "tx"; 2033 }; 2034 ssiu50: ssiu-40 { 2035 dmas = <&audma0 0x73>, <&audma1 0x74>; 2036 dma-names = "rx", "tx"; 2037 }; 2038 ssiu60: ssiu-41 { 2039 dmas = <&audma0 0x75>, <&audma1 0x76>; 2040 dma-names = "rx", "tx"; 2041 }; 2042 ssiu70: ssiu-42 { 2043 dmas = <&audma0 0x79>, <&audma1 0x7a>; 2044 dma-names = "rx", "tx"; 2045 }; 2046 ssiu80: ssiu-43 { 2047 dmas = <&audma0 0x7b>, <&audma1 0x7c>; 2048 dma-names = "rx", "tx"; 2049 }; 2050 ssiu90: ssiu-44 { 2051 dmas = <&audma0 0x7d>, <&audma1 0x7e>; 2052 dma-names = "rx", "tx"; 2053 }; 2054 ssiu91: ssiu-45 { 2055 dmas = <&audma0 0x7F>, <&audma1 0x80>; 2056 dma-names = "rx", "tx"; 2057 }; 2058 ssiu92: ssiu-46 { 2059 dmas = <&audma0 0x81>, <&audma1 0x82>; 2060 dma-names = "rx", "tx"; 2061 }; 2062 ssiu93: ssiu-47 { 2063 dmas = <&audma0 0x83>, <&audma1 0x84>; 2064 dma-names = "rx", "tx"; 2065 }; 2066 ssiu94: ssiu-48 { 2067 dmas = <&audma0 0xA3>, <&audma1 0xA4>; 2068 dma-names = "rx", "tx"; 2069 }; 2070 ssiu95: ssiu-49 { 2071 dmas = <&audma0 0xA5>, <&audma1 0xA6>; 2072 dma-names = "rx", "tx"; 2073 }; 2074 ssiu96: ssiu-50 { 2075 dmas = <&audma0 0xA7>, <&audma1 0xA8>; 2076 dma-names = "rx", "tx"; 2077 }; 2078 ssiu97: ssiu-51 { 2079 dmas = <&audma0 0xA9>, <&audma1 0xAA>; 2080 dma-names = "rx", "tx"; 2081 }; 2082 }; 2083 }; 2084 2085 audma0: dma-controller@ec700000 { 2086 compatible = "renesas,dmac-r8a77961", 2087 "renesas,rcar-dmac"; 2088 reg = <0 0xec700000 0 0x10000>; 2089 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 2090 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2091 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2092 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2093 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2094 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2095 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2096 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2097 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2098 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2099 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2100 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2101 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 2106 interrupt-names = "error", 2107 "ch0", "ch1", "ch2", "ch3", 2108 "ch4", "ch5", "ch6", "ch7", 2109 "ch8", "ch9", "ch10", "ch11", 2110 "ch12", "ch13", "ch14", "ch15"; 2111 clocks = <&cpg CPG_MOD 502>; 2112 clock-names = "fck"; 2113 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2114 resets = <&cpg 502>; 2115 #dma-cells = <1>; 2116 dma-channels = <16>; 2117 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 2118 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 2119 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 2120 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 2121 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 2122 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 2123 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 2124 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 2125 }; 2126 2127 audma1: dma-controller@ec720000 { 2128 compatible = "renesas,dmac-r8a77961", 2129 "renesas,rcar-dmac"; 2130 reg = <0 0xec720000 0 0x10000>; 2131 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 2132 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2133 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2134 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2135 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2136 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2137 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2138 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2139 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2140 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2142 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 2143 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2144 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 2145 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 2146 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 2147 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 2148 interrupt-names = "error", 2149 "ch0", "ch1", "ch2", "ch3", 2150 "ch4", "ch5", "ch6", "ch7", 2151 "ch8", "ch9", "ch10", "ch11", 2152 "ch12", "ch13", "ch14", "ch15"; 2153 clocks = <&cpg CPG_MOD 501>; 2154 clock-names = "fck"; 2155 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2156 resets = <&cpg 501>; 2157 #dma-cells = <1>; 2158 dma-channels = <16>; 2159 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, 2160 <&ipmmu_mp 18>, <&ipmmu_mp 19>, 2161 <&ipmmu_mp 20>, <&ipmmu_mp 21>, 2162 <&ipmmu_mp 22>, <&ipmmu_mp 23>, 2163 <&ipmmu_mp 24>, <&ipmmu_mp 25>, 2164 <&ipmmu_mp 26>, <&ipmmu_mp 27>, 2165 <&ipmmu_mp 28>, <&ipmmu_mp 29>, 2166 <&ipmmu_mp 30>, <&ipmmu_mp 31>; 2167 }; 2168 2169 xhci0: usb@ee000000 { 2170 compatible = "renesas,xhci-r8a77961", 2171 "renesas,rcar-gen3-xhci"; 2172 reg = <0 0xee000000 0 0xc00>; 2173 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2174 clocks = <&cpg CPG_MOD 328>; 2175 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2176 resets = <&cpg 328>; 2177 status = "disabled"; 2178 }; 2179 2180 usb3_peri0: usb@ee020000 { 2181 compatible = "renesas,r8a77961-usb3-peri", 2182 "renesas,rcar-gen3-usb3-peri"; 2183 reg = <0 0xee020000 0 0x400>; 2184 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2185 clocks = <&cpg CPG_MOD 328>; 2186 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2187 resets = <&cpg 328>; 2188 status = "disabled"; 2189 }; 2190 2191 ohci0: usb@ee080000 { 2192 compatible = "generic-ohci"; 2193 reg = <0 0xee080000 0 0x100>; 2194 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2195 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2196 phys = <&usb2_phy0 1>; 2197 phy-names = "usb"; 2198 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2199 resets = <&cpg 703>, <&cpg 704>; 2200 status = "disabled"; 2201 }; 2202 2203 ohci1: usb@ee0a0000 { 2204 compatible = "generic-ohci"; 2205 reg = <0 0xee0a0000 0 0x100>; 2206 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2207 clocks = <&cpg CPG_MOD 702>; 2208 phys = <&usb2_phy1 1>; 2209 phy-names = "usb"; 2210 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2211 resets = <&cpg 702>; 2212 status = "disabled"; 2213 }; 2214 2215 ehci0: usb@ee080100 { 2216 compatible = "generic-ehci"; 2217 reg = <0 0xee080100 0 0x100>; 2218 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2219 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2220 phys = <&usb2_phy0 2>; 2221 phy-names = "usb"; 2222 companion = <&ohci0>; 2223 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2224 resets = <&cpg 703>, <&cpg 704>; 2225 status = "disabled"; 2226 }; 2227 2228 ehci1: usb@ee0a0100 { 2229 compatible = "generic-ehci"; 2230 reg = <0 0xee0a0100 0 0x100>; 2231 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2232 clocks = <&cpg CPG_MOD 702>; 2233 phys = <&usb2_phy1 2>; 2234 phy-names = "usb"; 2235 companion = <&ohci1>; 2236 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2237 resets = <&cpg 702>; 2238 status = "disabled"; 2239 }; 2240 2241 usb2_phy0: usb-phy@ee080200 { 2242 compatible = "renesas,usb2-phy-r8a77961", 2243 "renesas,rcar-gen3-usb2-phy"; 2244 reg = <0 0xee080200 0 0x700>; 2245 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2246 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2247 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2248 resets = <&cpg 703>, <&cpg 704>; 2249 #phy-cells = <1>; 2250 status = "disabled"; 2251 }; 2252 2253 usb2_phy1: usb-phy@ee0a0200 { 2254 compatible = "renesas,usb2-phy-r8a77961", 2255 "renesas,rcar-gen3-usb2-phy"; 2256 reg = <0 0xee0a0200 0 0x700>; 2257 clocks = <&cpg CPG_MOD 702>; 2258 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2259 resets = <&cpg 702>; 2260 #phy-cells = <1>; 2261 status = "disabled"; 2262 }; 2263 2264 sdhi0: mmc@ee100000 { 2265 compatible = "renesas,sdhi-r8a77961", 2266 "renesas,rcar-gen3-sdhi"; 2267 reg = <0 0xee100000 0 0x2000>; 2268 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 2269 clocks = <&cpg CPG_MOD 314>; 2270 max-frequency = <200000000>; 2271 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2272 resets = <&cpg 314>; 2273 status = "disabled"; 2274 }; 2275 2276 sdhi1: mmc@ee120000 { 2277 compatible = "renesas,sdhi-r8a77961", 2278 "renesas,rcar-gen3-sdhi"; 2279 reg = <0 0xee120000 0 0x2000>; 2280 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 2281 clocks = <&cpg CPG_MOD 313>; 2282 max-frequency = <200000000>; 2283 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2284 resets = <&cpg 313>; 2285 status = "disabled"; 2286 }; 2287 2288 sdhi2: mmc@ee140000 { 2289 compatible = "renesas,sdhi-r8a77961", 2290 "renesas,rcar-gen3-sdhi"; 2291 reg = <0 0xee140000 0 0x2000>; 2292 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 2293 clocks = <&cpg CPG_MOD 312>; 2294 max-frequency = <200000000>; 2295 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2296 resets = <&cpg 312>; 2297 status = "disabled"; 2298 }; 2299 2300 sdhi3: mmc@ee160000 { 2301 compatible = "renesas,sdhi-r8a77961", 2302 "renesas,rcar-gen3-sdhi"; 2303 reg = <0 0xee160000 0 0x2000>; 2304 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 2305 clocks = <&cpg CPG_MOD 311>; 2306 max-frequency = <200000000>; 2307 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2308 resets = <&cpg 311>; 2309 status = "disabled"; 2310 }; 2311 2312 gic: interrupt-controller@f1010000 { 2313 compatible = "arm,gic-400"; 2314 #interrupt-cells = <3>; 2315 #address-cells = <0>; 2316 interrupt-controller; 2317 reg = <0x0 0xf1010000 0 0x1000>, 2318 <0x0 0xf1020000 0 0x20000>, 2319 <0x0 0xf1040000 0 0x20000>, 2320 <0x0 0xf1060000 0 0x20000>; 2321 interrupts = <GIC_PPI 9 2322 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 2323 clocks = <&cpg CPG_MOD 408>; 2324 clock-names = "clk"; 2325 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2326 resets = <&cpg 408>; 2327 }; 2328 2329 pciec0: pcie@fe000000 { 2330 compatible = "renesas,pcie-r8a77961", 2331 "renesas,pcie-rcar-gen3"; 2332 reg = <0 0xfe000000 0 0x80000>; 2333 #address-cells = <3>; 2334 #size-cells = <2>; 2335 bus-range = <0x00 0xff>; 2336 device_type = "pci"; 2337 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 2338 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 2339 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 2340 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 2341 /* Map all possible DDR as inbound ranges */ 2342 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2343 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2344 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2345 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2346 #interrupt-cells = <1>; 2347 interrupt-map-mask = <0 0 0 0>; 2348 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2349 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 2350 clock-names = "pcie", "pcie_bus"; 2351 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2352 resets = <&cpg 319>; 2353 status = "disabled"; 2354 }; 2355 2356 pciec1: pcie@ee800000 { 2357 compatible = "renesas,pcie-r8a77961", 2358 "renesas,pcie-rcar-gen3"; 2359 reg = <0 0xee800000 0 0x80000>; 2360 #address-cells = <3>; 2361 #size-cells = <2>; 2362 bus-range = <0x00 0xff>; 2363 device_type = "pci"; 2364 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, 2365 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, 2366 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, 2367 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 2368 /* Map all possible DDR as inbound ranges */ 2369 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2370 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2371 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2372 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2373 #interrupt-cells = <1>; 2374 interrupt-map-mask = <0 0 0 0>; 2375 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2376 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 2377 clock-names = "pcie", "pcie_bus"; 2378 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2379 resets = <&cpg 318>; 2380 status = "disabled"; 2381 }; 2382 2383 fcpf0: fcp@fe950000 { 2384 compatible = "renesas,fcpf"; 2385 reg = <0 0xfe950000 0 0x200>; 2386 clocks = <&cpg CPG_MOD 615>; 2387 power-domains = <&sysc R8A77961_PD_A3VC>; 2388 resets = <&cpg 615>; 2389 }; 2390 2391 fcpvb0: fcp@fe96f000 { 2392 compatible = "renesas,fcpv"; 2393 reg = <0 0xfe96f000 0 0x200>; 2394 clocks = <&cpg CPG_MOD 607>; 2395 power-domains = <&sysc R8A77961_PD_A3VC>; 2396 resets = <&cpg 607>; 2397 }; 2398 2399 fcpvi0: fcp@fe9af000 { 2400 compatible = "renesas,fcpv"; 2401 reg = <0 0xfe9af000 0 0x200>; 2402 clocks = <&cpg CPG_MOD 611>; 2403 power-domains = <&sysc R8A77961_PD_A3VC>; 2404 resets = <&cpg 611>; 2405 iommus = <&ipmmu_vc0 19>; 2406 }; 2407 2408 fcpvd0: fcp@fea27000 { 2409 compatible = "renesas,fcpv"; 2410 reg = <0 0xfea27000 0 0x200>; 2411 clocks = <&cpg CPG_MOD 603>; 2412 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2413 resets = <&cpg 603>; 2414 iommus = <&ipmmu_vi0 8>; 2415 }; 2416 2417 fcpvd1: fcp@fea2f000 { 2418 compatible = "renesas,fcpv"; 2419 reg = <0 0xfea2f000 0 0x200>; 2420 clocks = <&cpg CPG_MOD 602>; 2421 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2422 resets = <&cpg 602>; 2423 iommus = <&ipmmu_vi0 9>; 2424 }; 2425 2426 fcpvd2: fcp@fea37000 { 2427 compatible = "renesas,fcpv"; 2428 reg = <0 0xfea37000 0 0x200>; 2429 clocks = <&cpg CPG_MOD 601>; 2430 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2431 resets = <&cpg 601>; 2432 iommus = <&ipmmu_vi0 10>; 2433 }; 2434 2435 vspb: vsp@fe960000 { 2436 compatible = "renesas,vsp2"; 2437 reg = <0 0xfe960000 0 0x8000>; 2438 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 2439 clocks = <&cpg CPG_MOD 626>; 2440 power-domains = <&sysc R8A77961_PD_A3VC>; 2441 resets = <&cpg 626>; 2442 2443 renesas,fcp = <&fcpvb0>; 2444 }; 2445 2446 vspd0: vsp@fea20000 { 2447 compatible = "renesas,vsp2"; 2448 reg = <0 0xfea20000 0 0x5000>; 2449 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 2450 clocks = <&cpg CPG_MOD 623>; 2451 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2452 resets = <&cpg 623>; 2453 2454 renesas,fcp = <&fcpvd0>; 2455 }; 2456 2457 vspd1: vsp@fea28000 { 2458 compatible = "renesas,vsp2"; 2459 reg = <0 0xfea28000 0 0x5000>; 2460 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 2461 clocks = <&cpg CPG_MOD 622>; 2462 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2463 resets = <&cpg 622>; 2464 2465 renesas,fcp = <&fcpvd1>; 2466 }; 2467 2468 vspd2: vsp@fea30000 { 2469 compatible = "renesas,vsp2"; 2470 reg = <0 0xfea30000 0 0x5000>; 2471 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 2472 clocks = <&cpg CPG_MOD 621>; 2473 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2474 resets = <&cpg 621>; 2475 2476 renesas,fcp = <&fcpvd2>; 2477 }; 2478 2479 vspi0: vsp@fe9a0000 { 2480 compatible = "renesas,vsp2"; 2481 reg = <0 0xfe9a0000 0 0x8000>; 2482 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 2483 clocks = <&cpg CPG_MOD 631>; 2484 power-domains = <&sysc R8A77961_PD_A3VC>; 2485 resets = <&cpg 631>; 2486 2487 renesas,fcp = <&fcpvi0>; 2488 }; 2489 2490 csi20: csi2@fea80000 { 2491 compatible = "renesas,r8a77961-csi2"; 2492 reg = <0 0xfea80000 0 0x10000>; 2493 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2494 clocks = <&cpg CPG_MOD 714>; 2495 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2496 resets = <&cpg 714>; 2497 status = "disabled"; 2498 2499 ports { 2500 #address-cells = <1>; 2501 #size-cells = <0>; 2502 2503 port@0 { 2504 reg = <0>; 2505 }; 2506 2507 port@1 { 2508 #address-cells = <1>; 2509 #size-cells = <0>; 2510 2511 reg = <1>; 2512 2513 csi20vin0: endpoint@0 { 2514 reg = <0>; 2515 remote-endpoint = <&vin0csi20>; 2516 }; 2517 csi20vin1: endpoint@1 { 2518 reg = <1>; 2519 remote-endpoint = <&vin1csi20>; 2520 }; 2521 csi20vin2: endpoint@2 { 2522 reg = <2>; 2523 remote-endpoint = <&vin2csi20>; 2524 }; 2525 csi20vin3: endpoint@3 { 2526 reg = <3>; 2527 remote-endpoint = <&vin3csi20>; 2528 }; 2529 csi20vin4: endpoint@4 { 2530 reg = <4>; 2531 remote-endpoint = <&vin4csi20>; 2532 }; 2533 csi20vin5: endpoint@5 { 2534 reg = <5>; 2535 remote-endpoint = <&vin5csi20>; 2536 }; 2537 csi20vin6: endpoint@6 { 2538 reg = <6>; 2539 remote-endpoint = <&vin6csi20>; 2540 }; 2541 csi20vin7: endpoint@7 { 2542 reg = <7>; 2543 remote-endpoint = <&vin7csi20>; 2544 }; 2545 }; 2546 }; 2547 }; 2548 2549 csi40: csi2@feaa0000 { 2550 compatible = "renesas,r8a77961-csi2"; 2551 reg = <0 0xfeaa0000 0 0x10000>; 2552 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2553 clocks = <&cpg CPG_MOD 716>; 2554 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2555 resets = <&cpg 716>; 2556 status = "disabled"; 2557 2558 ports { 2559 #address-cells = <1>; 2560 #size-cells = <0>; 2561 2562 port@0 { 2563 reg = <0>; 2564 }; 2565 2566 port@1 { 2567 #address-cells = <1>; 2568 #size-cells = <0>; 2569 2570 reg = <1>; 2571 2572 csi40vin0: endpoint@0 { 2573 reg = <0>; 2574 remote-endpoint = <&vin0csi40>; 2575 }; 2576 csi40vin1: endpoint@1 { 2577 reg = <1>; 2578 remote-endpoint = <&vin1csi40>; 2579 }; 2580 csi40vin2: endpoint@2 { 2581 reg = <2>; 2582 remote-endpoint = <&vin2csi40>; 2583 }; 2584 csi40vin3: endpoint@3 { 2585 reg = <3>; 2586 remote-endpoint = <&vin3csi40>; 2587 }; 2588 csi40vin4: endpoint@4 { 2589 reg = <4>; 2590 remote-endpoint = <&vin4csi40>; 2591 }; 2592 csi40vin5: endpoint@5 { 2593 reg = <5>; 2594 remote-endpoint = <&vin5csi40>; 2595 }; 2596 csi40vin6: endpoint@6 { 2597 reg = <6>; 2598 remote-endpoint = <&vin6csi40>; 2599 }; 2600 csi40vin7: endpoint@7 { 2601 reg = <7>; 2602 remote-endpoint = <&vin7csi40>; 2603 }; 2604 }; 2605 2606 }; 2607 }; 2608 2609 hdmi0: hdmi@fead0000 { 2610 compatible = "renesas,r8a77961-hdmi", "renesas,rcar-gen3-hdmi"; 2611 reg = <0 0xfead0000 0 0x10000>; 2612 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 2613 clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A77961_CLK_HDMI>; 2614 clock-names = "iahb", "isfr"; 2615 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2616 resets = <&cpg 729>; 2617 status = "disabled"; 2618 2619 ports { 2620 #address-cells = <1>; 2621 #size-cells = <0>; 2622 port@0 { 2623 reg = <0>; 2624 dw_hdmi0_in: endpoint { 2625 remote-endpoint = <&du_out_hdmi0>; 2626 }; 2627 }; 2628 port@1 { 2629 reg = <1>; 2630 }; 2631 port@2 { 2632 /* HDMI sound */ 2633 reg = <2>; 2634 }; 2635 }; 2636 }; 2637 2638 du: display@feb00000 { 2639 compatible = "renesas,du-r8a77961"; 2640 reg = <0 0xfeb00000 0 0x70000>; 2641 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2642 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2643 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2644 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, 2645 <&cpg CPG_MOD 722>; 2646 clock-names = "du.0", "du.1", "du.2"; 2647 resets = <&cpg 724>, <&cpg 722>; 2648 reset-names = "du.0", "du.2"; 2649 2650 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; 2651 status = "disabled"; 2652 2653 ports { 2654 #address-cells = <1>; 2655 #size-cells = <0>; 2656 2657 port@0 { 2658 reg = <0>; 2659 du_out_rgb: endpoint { 2660 }; 2661 }; 2662 port@1 { 2663 reg = <1>; 2664 du_out_hdmi0: endpoint { 2665 remote-endpoint = <&dw_hdmi0_in>; 2666 }; 2667 }; 2668 port@2 { 2669 reg = <2>; 2670 du_out_lvds0: endpoint { 2671 }; 2672 }; 2673 }; 2674 }; 2675 2676 prr: chipid@fff00044 { 2677 compatible = "renesas,prr"; 2678 reg = <0 0xfff00044 0 4>; 2679 }; 2680 }; 2681 2682 thermal-zones { 2683 sensor_thermal1: sensor-thermal1 { 2684 polling-delay-passive = <250>; 2685 polling-delay = <1000>; 2686 thermal-sensors = <&tsc 0>; 2687 sustainable-power = <3874>; 2688 2689 trips { 2690 sensor1_crit: sensor1-crit { 2691 temperature = <120000>; 2692 hysteresis = <1000>; 2693 type = "critical"; 2694 }; 2695 }; 2696 }; 2697 2698 sensor_thermal2: sensor-thermal2 { 2699 polling-delay-passive = <250>; 2700 polling-delay = <1000>; 2701 thermal-sensors = <&tsc 1>; 2702 sustainable-power = <3874>; 2703 2704 trips { 2705 sensor2_crit: sensor2-crit { 2706 temperature = <120000>; 2707 hysteresis = <1000>; 2708 type = "critical"; 2709 }; 2710 }; 2711 }; 2712 2713 sensor_thermal3: sensor-thermal3 { 2714 polling-delay-passive = <250>; 2715 polling-delay = <1000>; 2716 thermal-sensors = <&tsc 2>; 2717 sustainable-power = <3874>; 2718 2719 cooling-maps { 2720 map0 { 2721 trip = <&target>; 2722 cooling-device = <&a57_0 2 4>; 2723 contribution = <1024>; 2724 }; 2725 map1 { 2726 trip = <&target>; 2727 cooling-device = <&a53_0 0 2>; 2728 contribution = <1024>; 2729 }; 2730 }; 2731 trips { 2732 target: trip-point1 { 2733 temperature = <100000>; 2734 hysteresis = <1000>; 2735 type = "passive"; 2736 }; 2737 2738 sensor3_crit: sensor3-crit { 2739 temperature = <120000>; 2740 hysteresis = <1000>; 2741 type = "critical"; 2742 }; 2743 }; 2744 }; 2745 }; 2746 2747 timer { 2748 compatible = "arm,armv8-timer"; 2749 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2750 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2751 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2752 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 2753 }; 2754 2755 /* External USB clocks - can be overridden by the board */ 2756 usb3s0_clk: usb3s0 { 2757 compatible = "fixed-clock"; 2758 #clock-cells = <0>; 2759 clock-frequency = <0>; 2760 }; 2761 2762 usb_extal_clk: usb_extal { 2763 compatible = "fixed-clock"; 2764 #clock-cells = <0>; 2765 clock-frequency = <0>; 2766 }; 2767}; 2768