1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774e1 SoC 4 * 5 * Copyright (C) 2020 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r8a774e1-cpg-mssr.h> 11#include <dt-bindings/power/r8a774e1-sysc.h> 12 13#define CPG_AUDIO_CLK_I R8A774E1_CLK_S0D4 14 15/ { 16 compatible = "renesas,r8a774e1"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 /* 21 * The external audio clocks are configured as 0 Hz fixed frequency 22 * clocks by default. 23 * Boards that provide audio clocks should override them. 24 */ 25 audio_clk_a: audio_clk_a { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <0>; 29 }; 30 31 audio_clk_c: audio_clk_c { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 /* External CAN clock - to be overridden by boards that provide it */ 38 can_clk: can { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <0>; 42 }; 43 44 cluster0_opp: opp_table0 { 45 compatible = "operating-points-v2"; 46 opp-shared; 47 48 opp-500000000 { 49 opp-hz = /bits/ 64 <500000000>; 50 opp-microvolt = <820000>; 51 clock-latency-ns = <300000>; 52 }; 53 opp-1000000000 { 54 opp-hz = /bits/ 64 <1000000000>; 55 opp-microvolt = <820000>; 56 clock-latency-ns = <300000>; 57 }; 58 opp-1500000000 { 59 opp-hz = /bits/ 64 <1500000000>; 60 opp-microvolt = <820000>; 61 clock-latency-ns = <300000>; 62 opp-suspend; 63 }; 64 }; 65 66 cluster1_opp: opp_table1 { 67 compatible = "operating-points-v2"; 68 opp-shared; 69 70 opp-800000000 { 71 opp-hz = /bits/ 64 <800000000>; 72 opp-microvolt = <820000>; 73 clock-latency-ns = <300000>; 74 }; 75 opp-1000000000 { 76 opp-hz = /bits/ 64 <1000000000>; 77 opp-microvolt = <820000>; 78 clock-latency-ns = <300000>; 79 }; 80 opp-1200000000 { 81 opp-hz = /bits/ 64 <1200000000>; 82 opp-microvolt = <820000>; 83 clock-latency-ns = <300000>; 84 }; 85 }; 86 87 cpus { 88 #address-cells = <1>; 89 #size-cells = <0>; 90 91 cpu-map { 92 cluster0 { 93 core0 { 94 cpu = <&a57_0>; 95 }; 96 core1 { 97 cpu = <&a57_1>; 98 }; 99 core2 { 100 cpu = <&a57_2>; 101 }; 102 core3 { 103 cpu = <&a57_3>; 104 }; 105 }; 106 107 cluster1 { 108 core0 { 109 cpu = <&a53_0>; 110 }; 111 core1 { 112 cpu = <&a53_1>; 113 }; 114 core2 { 115 cpu = <&a53_2>; 116 }; 117 core3 { 118 cpu = <&a53_3>; 119 }; 120 }; 121 }; 122 123 a57_0: cpu@0 { 124 compatible = "arm,cortex-a57"; 125 reg = <0x0>; 126 device_type = "cpu"; 127 power-domains = <&sysc R8A774E1_PD_CA57_CPU0>; 128 next-level-cache = <&L2_CA57>; 129 enable-method = "psci"; 130 dynamic-power-coefficient = <854>; 131 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 132 operating-points-v2 = <&cluster0_opp>; 133 capacity-dmips-mhz = <1024>; 134 #cooling-cells = <2>; 135 }; 136 137 a57_1: cpu@1 { 138 compatible = "arm,cortex-a57"; 139 reg = <0x1>; 140 device_type = "cpu"; 141 power-domains = <&sysc R8A774E1_PD_CA57_CPU1>; 142 next-level-cache = <&L2_CA57>; 143 enable-method = "psci"; 144 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 145 operating-points-v2 = <&cluster0_opp>; 146 capacity-dmips-mhz = <1024>; 147 #cooling-cells = <2>; 148 }; 149 150 a57_2: cpu@2 { 151 compatible = "arm,cortex-a57"; 152 reg = <0x2>; 153 device_type = "cpu"; 154 power-domains = <&sysc R8A774E1_PD_CA57_CPU2>; 155 next-level-cache = <&L2_CA57>; 156 enable-method = "psci"; 157 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 158 operating-points-v2 = <&cluster0_opp>; 159 capacity-dmips-mhz = <1024>; 160 #cooling-cells = <2>; 161 }; 162 163 a57_3: cpu@3 { 164 compatible = "arm,cortex-a57"; 165 reg = <0x3>; 166 device_type = "cpu"; 167 power-domains = <&sysc R8A774E1_PD_CA57_CPU3>; 168 next-level-cache = <&L2_CA57>; 169 enable-method = "psci"; 170 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 171 operating-points-v2 = <&cluster0_opp>; 172 capacity-dmips-mhz = <1024>; 173 #cooling-cells = <2>; 174 }; 175 176 a53_0: cpu@100 { 177 compatible = "arm,cortex-a53"; 178 reg = <0x100>; 179 device_type = "cpu"; 180 power-domains = <&sysc R8A774E1_PD_CA53_CPU0>; 181 next-level-cache = <&L2_CA53>; 182 enable-method = "psci"; 183 #cooling-cells = <2>; 184 dynamic-power-coefficient = <277>; 185 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 186 operating-points-v2 = <&cluster1_opp>; 187 capacity-dmips-mhz = <535>; 188 }; 189 190 a53_1: cpu@101 { 191 compatible = "arm,cortex-a53"; 192 reg = <0x101>; 193 device_type = "cpu"; 194 power-domains = <&sysc R8A774E1_PD_CA53_CPU1>; 195 next-level-cache = <&L2_CA53>; 196 enable-method = "psci"; 197 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 198 operating-points-v2 = <&cluster1_opp>; 199 capacity-dmips-mhz = <535>; 200 }; 201 202 a53_2: cpu@102 { 203 compatible = "arm,cortex-a53"; 204 reg = <0x102>; 205 device_type = "cpu"; 206 power-domains = <&sysc R8A774E1_PD_CA53_CPU2>; 207 next-level-cache = <&L2_CA53>; 208 enable-method = "psci"; 209 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 210 operating-points-v2 = <&cluster1_opp>; 211 capacity-dmips-mhz = <535>; 212 }; 213 214 a53_3: cpu@103 { 215 compatible = "arm,cortex-a53"; 216 reg = <0x103>; 217 device_type = "cpu"; 218 power-domains = <&sysc R8A774E1_PD_CA53_CPU3>; 219 next-level-cache = <&L2_CA53>; 220 enable-method = "psci"; 221 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 222 operating-points-v2 = <&cluster1_opp>; 223 capacity-dmips-mhz = <535>; 224 }; 225 226 L2_CA57: cache-controller-0 { 227 compatible = "cache"; 228 power-domains = <&sysc R8A774E1_PD_CA57_SCU>; 229 cache-unified; 230 cache-level = <2>; 231 }; 232 233 L2_CA53: cache-controller-1 { 234 compatible = "cache"; 235 power-domains = <&sysc R8A774E1_PD_CA53_SCU>; 236 cache-unified; 237 cache-level = <2>; 238 }; 239 }; 240 241 extal_clk: extal { 242 compatible = "fixed-clock"; 243 #clock-cells = <0>; 244 /* This value must be overridden by the board */ 245 clock-frequency = <0>; 246 }; 247 248 extalr_clk: extalr { 249 compatible = "fixed-clock"; 250 #clock-cells = <0>; 251 /* This value must be overridden by the board */ 252 clock-frequency = <0>; 253 }; 254 255 /* External PCIe clock - can be overridden by the board */ 256 pcie_bus_clk: pcie_bus { 257 compatible = "fixed-clock"; 258 #clock-cells = <0>; 259 clock-frequency = <0>; 260 }; 261 262 pmu_a53 { 263 compatible = "arm,cortex-a53-pmu"; 264 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 265 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 266 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 267 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 268 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 269 }; 270 271 pmu_a57 { 272 compatible = "arm,cortex-a57-pmu"; 273 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 274 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 275 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 276 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 277 interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>; 278 }; 279 280 psci { 281 compatible = "arm,psci-1.0", "arm,psci-0.2"; 282 method = "smc"; 283 }; 284 285 /* External SCIF clock - to be overridden by boards that provide it */ 286 scif_clk: scif { 287 compatible = "fixed-clock"; 288 #clock-cells = <0>; 289 clock-frequency = <0>; 290 }; 291 292 soc { 293 compatible = "simple-bus"; 294 interrupt-parent = <&gic>; 295 #address-cells = <2>; 296 #size-cells = <2>; 297 ranges; 298 299 rwdt: watchdog@e6020000 { 300 compatible = "renesas,r8a774e1-wdt", 301 "renesas,rcar-gen3-wdt"; 302 reg = <0 0xe6020000 0 0x0c>; 303 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&cpg CPG_MOD 402>; 305 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 306 resets = <&cpg 402>; 307 status = "disabled"; 308 }; 309 310 gpio0: gpio@e6050000 { 311 compatible = "renesas,gpio-r8a774e1", 312 "renesas,rcar-gen3-gpio"; 313 reg = <0 0xe6050000 0 0x50>; 314 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 315 #gpio-cells = <2>; 316 gpio-controller; 317 gpio-ranges = <&pfc 0 0 16>; 318 #interrupt-cells = <2>; 319 interrupt-controller; 320 clocks = <&cpg CPG_MOD 912>; 321 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 322 resets = <&cpg 912>; 323 }; 324 325 gpio1: gpio@e6051000 { 326 compatible = "renesas,gpio-r8a774e1", 327 "renesas,rcar-gen3-gpio"; 328 reg = <0 0xe6051000 0 0x50>; 329 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 330 #gpio-cells = <2>; 331 gpio-controller; 332 gpio-ranges = <&pfc 0 32 29>; 333 #interrupt-cells = <2>; 334 interrupt-controller; 335 clocks = <&cpg CPG_MOD 911>; 336 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 337 resets = <&cpg 911>; 338 }; 339 340 gpio2: gpio@e6052000 { 341 compatible = "renesas,gpio-r8a774e1", 342 "renesas,rcar-gen3-gpio"; 343 reg = <0 0xe6052000 0 0x50>; 344 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 345 #gpio-cells = <2>; 346 gpio-controller; 347 gpio-ranges = <&pfc 0 64 15>; 348 #interrupt-cells = <2>; 349 interrupt-controller; 350 clocks = <&cpg CPG_MOD 910>; 351 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 352 resets = <&cpg 910>; 353 }; 354 355 gpio3: gpio@e6053000 { 356 compatible = "renesas,gpio-r8a774e1", 357 "renesas,rcar-gen3-gpio"; 358 reg = <0 0xe6053000 0 0x50>; 359 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 360 #gpio-cells = <2>; 361 gpio-controller; 362 gpio-ranges = <&pfc 0 96 16>; 363 #interrupt-cells = <2>; 364 interrupt-controller; 365 clocks = <&cpg CPG_MOD 909>; 366 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 367 resets = <&cpg 909>; 368 }; 369 370 gpio4: gpio@e6054000 { 371 compatible = "renesas,gpio-r8a774e1", 372 "renesas,rcar-gen3-gpio"; 373 reg = <0 0xe6054000 0 0x50>; 374 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 375 #gpio-cells = <2>; 376 gpio-controller; 377 gpio-ranges = <&pfc 0 128 18>; 378 #interrupt-cells = <2>; 379 interrupt-controller; 380 clocks = <&cpg CPG_MOD 908>; 381 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 382 resets = <&cpg 908>; 383 }; 384 385 gpio5: gpio@e6055000 { 386 compatible = "renesas,gpio-r8a774e1", 387 "renesas,rcar-gen3-gpio"; 388 reg = <0 0xe6055000 0 0x50>; 389 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 390 #gpio-cells = <2>; 391 gpio-controller; 392 gpio-ranges = <&pfc 0 160 26>; 393 #interrupt-cells = <2>; 394 interrupt-controller; 395 clocks = <&cpg CPG_MOD 907>; 396 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 397 resets = <&cpg 907>; 398 }; 399 400 gpio6: gpio@e6055400 { 401 compatible = "renesas,gpio-r8a774e1", 402 "renesas,rcar-gen3-gpio"; 403 reg = <0 0xe6055400 0 0x50>; 404 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 405 #gpio-cells = <2>; 406 gpio-controller; 407 gpio-ranges = <&pfc 0 192 32>; 408 #interrupt-cells = <2>; 409 interrupt-controller; 410 clocks = <&cpg CPG_MOD 906>; 411 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 412 resets = <&cpg 906>; 413 }; 414 415 gpio7: gpio@e6055800 { 416 compatible = "renesas,gpio-r8a774e1", 417 "renesas,rcar-gen3-gpio"; 418 reg = <0 0xe6055800 0 0x50>; 419 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 420 #gpio-cells = <2>; 421 gpio-controller; 422 gpio-ranges = <&pfc 0 224 4>; 423 #interrupt-cells = <2>; 424 interrupt-controller; 425 clocks = <&cpg CPG_MOD 905>; 426 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 427 resets = <&cpg 905>; 428 }; 429 430 pfc: pin-controller@e6060000 { 431 compatible = "renesas,pfc-r8a774e1"; 432 reg = <0 0xe6060000 0 0x50c>; 433 }; 434 435 cmt0: timer@e60f0000 { 436 compatible = "renesas,r8a774e1-cmt0", 437 "renesas,rcar-gen3-cmt0"; 438 reg = <0 0xe60f0000 0 0x1004>; 439 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&cpg CPG_MOD 303>; 442 clock-names = "fck"; 443 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 444 resets = <&cpg 303>; 445 status = "disabled"; 446 }; 447 448 cmt1: timer@e6130000 { 449 compatible = "renesas,r8a774e1-cmt1", 450 "renesas,rcar-gen3-cmt1"; 451 reg = <0 0xe6130000 0 0x1004>; 452 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&cpg CPG_MOD 302>; 461 clock-names = "fck"; 462 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 463 resets = <&cpg 302>; 464 status = "disabled"; 465 }; 466 467 cmt2: timer@e6140000 { 468 compatible = "renesas,r8a774e1-cmt1", 469 "renesas,rcar-gen3-cmt1"; 470 reg = <0 0xe6140000 0 0x1004>; 471 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&cpg CPG_MOD 301>; 480 clock-names = "fck"; 481 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 482 resets = <&cpg 301>; 483 status = "disabled"; 484 }; 485 486 cmt3: timer@e6148000 { 487 compatible = "renesas,r8a774e1-cmt1", 488 "renesas,rcar-gen3-cmt1"; 489 reg = <0 0xe6148000 0 0x1004>; 490 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&cpg CPG_MOD 300>; 499 clock-names = "fck"; 500 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 501 resets = <&cpg 300>; 502 status = "disabled"; 503 }; 504 505 cpg: clock-controller@e6150000 { 506 compatible = "renesas,r8a774e1-cpg-mssr"; 507 reg = <0 0xe6150000 0 0x1000>; 508 clocks = <&extal_clk>, <&extalr_clk>; 509 clock-names = "extal", "extalr"; 510 #clock-cells = <2>; 511 #power-domain-cells = <0>; 512 #reset-cells = <1>; 513 }; 514 515 rst: reset-controller@e6160000 { 516 compatible = "renesas,r8a774e1-rst"; 517 reg = <0 0xe6160000 0 0x0200>; 518 }; 519 520 sysc: system-controller@e6180000 { 521 compatible = "renesas,r8a774e1-sysc"; 522 reg = <0 0xe6180000 0 0x0400>; 523 #power-domain-cells = <1>; 524 }; 525 526 tsc: thermal@e6198000 { 527 compatible = "renesas,r8a774e1-thermal"; 528 reg = <0 0xe6198000 0 0x100>, 529 <0 0xe61a0000 0 0x100>, 530 <0 0xe61a8000 0 0x100>; 531 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&cpg CPG_MOD 522>; 535 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 536 resets = <&cpg 522>; 537 #thermal-sensor-cells = <1>; 538 }; 539 540 intc_ex: interrupt-controller@e61c0000 { 541 compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc"; 542 #interrupt-cells = <2>; 543 interrupt-controller; 544 reg = <0 0xe61c0000 0 0x200>; 545 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&cpg CPG_MOD 407>; 552 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 553 resets = <&cpg 407>; 554 }; 555 556 tmu0: timer@e61e0000 { 557 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 558 reg = <0 0xe61e0000 0 0x30>; 559 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&cpg CPG_MOD 125>; 563 clock-names = "fck"; 564 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 565 resets = <&cpg 125>; 566 status = "disabled"; 567 }; 568 569 tmu1: timer@e6fc0000 { 570 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 571 reg = <0 0xe6fc0000 0 0x30>; 572 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&cpg CPG_MOD 124>; 576 clock-names = "fck"; 577 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 578 resets = <&cpg 124>; 579 status = "disabled"; 580 }; 581 582 tmu2: timer@e6fd0000 { 583 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 584 reg = <0 0xe6fd0000 0 0x30>; 585 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&cpg CPG_MOD 123>; 589 clock-names = "fck"; 590 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 591 resets = <&cpg 123>; 592 status = "disabled"; 593 }; 594 595 tmu3: timer@e6fe0000 { 596 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 597 reg = <0 0xe6fe0000 0 0x30>; 598 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&cpg CPG_MOD 122>; 602 clock-names = "fck"; 603 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 604 resets = <&cpg 122>; 605 status = "disabled"; 606 }; 607 608 tmu4: timer@ffc00000 { 609 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 610 reg = <0 0xffc00000 0 0x30>; 611 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 614 clocks = <&cpg CPG_MOD 121>; 615 clock-names = "fck"; 616 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 617 resets = <&cpg 121>; 618 status = "disabled"; 619 }; 620 621 i2c0: i2c@e6500000 { 622 #address-cells = <1>; 623 #size-cells = <0>; 624 compatible = "renesas,i2c-r8a774e1", 625 "renesas,rcar-gen3-i2c"; 626 reg = <0 0xe6500000 0 0x40>; 627 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&cpg CPG_MOD 931>; 629 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 630 resets = <&cpg 931>; 631 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 632 <&dmac2 0x91>, <&dmac2 0x90>; 633 dma-names = "tx", "rx", "tx", "rx"; 634 i2c-scl-internal-delay-ns = <110>; 635 status = "disabled"; 636 }; 637 638 i2c1: i2c@e6508000 { 639 #address-cells = <1>; 640 #size-cells = <0>; 641 compatible = "renesas,i2c-r8a774e1", 642 "renesas,rcar-gen3-i2c"; 643 reg = <0 0xe6508000 0 0x40>; 644 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 645 clocks = <&cpg CPG_MOD 930>; 646 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 647 resets = <&cpg 930>; 648 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 649 <&dmac2 0x93>, <&dmac2 0x92>; 650 dma-names = "tx", "rx", "tx", "rx"; 651 i2c-scl-internal-delay-ns = <6>; 652 status = "disabled"; 653 }; 654 655 i2c2: i2c@e6510000 { 656 #address-cells = <1>; 657 #size-cells = <0>; 658 compatible = "renesas,i2c-r8a774e1", 659 "renesas,rcar-gen3-i2c"; 660 reg = <0 0xe6510000 0 0x40>; 661 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&cpg CPG_MOD 929>; 663 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 664 resets = <&cpg 929>; 665 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 666 <&dmac2 0x95>, <&dmac2 0x94>; 667 dma-names = "tx", "rx", "tx", "rx"; 668 i2c-scl-internal-delay-ns = <6>; 669 status = "disabled"; 670 }; 671 672 i2c3: i2c@e66d0000 { 673 #address-cells = <1>; 674 #size-cells = <0>; 675 compatible = "renesas,i2c-r8a774e1", 676 "renesas,rcar-gen3-i2c"; 677 reg = <0 0xe66d0000 0 0x40>; 678 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 679 clocks = <&cpg CPG_MOD 928>; 680 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 681 resets = <&cpg 928>; 682 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 683 dma-names = "tx", "rx"; 684 i2c-scl-internal-delay-ns = <110>; 685 status = "disabled"; 686 }; 687 688 i2c4: i2c@e66d8000 { 689 #address-cells = <1>; 690 #size-cells = <0>; 691 compatible = "renesas,i2c-r8a774e1", 692 "renesas,rcar-gen3-i2c"; 693 reg = <0 0xe66d8000 0 0x40>; 694 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 695 clocks = <&cpg CPG_MOD 927>; 696 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 697 resets = <&cpg 927>; 698 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 699 dma-names = "tx", "rx"; 700 i2c-scl-internal-delay-ns = <110>; 701 status = "disabled"; 702 }; 703 704 i2c5: i2c@e66e0000 { 705 #address-cells = <1>; 706 #size-cells = <0>; 707 compatible = "renesas,i2c-r8a774e1", 708 "renesas,rcar-gen3-i2c"; 709 reg = <0 0xe66e0000 0 0x40>; 710 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&cpg CPG_MOD 919>; 712 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 713 resets = <&cpg 919>; 714 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 715 dma-names = "tx", "rx"; 716 i2c-scl-internal-delay-ns = <110>; 717 status = "disabled"; 718 }; 719 720 i2c6: i2c@e66e8000 { 721 #address-cells = <1>; 722 #size-cells = <0>; 723 compatible = "renesas,i2c-r8a774e1", 724 "renesas,rcar-gen3-i2c"; 725 reg = <0 0xe66e8000 0 0x40>; 726 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&cpg CPG_MOD 918>; 728 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 729 resets = <&cpg 918>; 730 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 731 dma-names = "tx", "rx"; 732 i2c-scl-internal-delay-ns = <6>; 733 status = "disabled"; 734 }; 735 736 i2c_dvfs: i2c@e60b0000 { 737 #address-cells = <1>; 738 #size-cells = <0>; 739 compatible = "renesas,iic-r8a774e1", 740 "renesas,rcar-gen3-iic", 741 "renesas,rmobile-iic"; 742 reg = <0 0xe60b0000 0 0x425>; 743 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&cpg CPG_MOD 926>; 745 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 746 resets = <&cpg 926>; 747 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 748 dma-names = "tx", "rx"; 749 status = "disabled"; 750 }; 751 752 hscif0: serial@e6540000 { 753 compatible = "renesas,hscif-r8a774e1", 754 "renesas,rcar-gen3-hscif", 755 "renesas,hscif"; 756 reg = <0 0xe6540000 0 0x60>; 757 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&cpg CPG_MOD 520>, 759 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 760 <&scif_clk>; 761 clock-names = "fck", "brg_int", "scif_clk"; 762 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 763 <&dmac2 0x31>, <&dmac2 0x30>; 764 dma-names = "tx", "rx", "tx", "rx"; 765 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 766 resets = <&cpg 520>; 767 status = "disabled"; 768 }; 769 770 hscif1: serial@e6550000 { 771 compatible = "renesas,hscif-r8a774e1", 772 "renesas,rcar-gen3-hscif", 773 "renesas,hscif"; 774 reg = <0 0xe6550000 0 0x60>; 775 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 776 clocks = <&cpg CPG_MOD 519>, 777 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 778 <&scif_clk>; 779 clock-names = "fck", "brg_int", "scif_clk"; 780 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 781 <&dmac2 0x33>, <&dmac2 0x32>; 782 dma-names = "tx", "rx", "tx", "rx"; 783 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 784 resets = <&cpg 519>; 785 status = "disabled"; 786 }; 787 788 hscif2: serial@e6560000 { 789 compatible = "renesas,hscif-r8a774e1", 790 "renesas,rcar-gen3-hscif", 791 "renesas,hscif"; 792 reg = <0 0xe6560000 0 0x60>; 793 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 794 clocks = <&cpg CPG_MOD 518>, 795 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 796 <&scif_clk>; 797 clock-names = "fck", "brg_int", "scif_clk"; 798 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 799 <&dmac2 0x35>, <&dmac2 0x34>; 800 dma-names = "tx", "rx", "tx", "rx"; 801 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 802 resets = <&cpg 518>; 803 status = "disabled"; 804 }; 805 806 hscif3: serial@e66a0000 { 807 compatible = "renesas,hscif-r8a774e1", 808 "renesas,rcar-gen3-hscif", 809 "renesas,hscif"; 810 reg = <0 0xe66a0000 0 0x60>; 811 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&cpg CPG_MOD 517>, 813 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 814 <&scif_clk>; 815 clock-names = "fck", "brg_int", "scif_clk"; 816 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 817 dma-names = "tx", "rx"; 818 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 819 resets = <&cpg 517>; 820 status = "disabled"; 821 }; 822 823 hscif4: serial@e66b0000 { 824 compatible = "renesas,hscif-r8a774e1", 825 "renesas,rcar-gen3-hscif", 826 "renesas,hscif"; 827 reg = <0 0xe66b0000 0 0x60>; 828 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 829 clocks = <&cpg CPG_MOD 516>, 830 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 831 <&scif_clk>; 832 clock-names = "fck", "brg_int", "scif_clk"; 833 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 834 dma-names = "tx", "rx"; 835 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 836 resets = <&cpg 516>; 837 status = "disabled"; 838 }; 839 840 hsusb: usb@e6590000 { 841 compatible = "renesas,usbhs-r8a774e1", 842 "renesas,rcar-gen3-usbhs"; 843 reg = <0 0xe6590000 0 0x200>; 844 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 845 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 846 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 847 <&usb_dmac1 0>, <&usb_dmac1 1>; 848 dma-names = "ch0", "ch1", "ch2", "ch3"; 849 renesas,buswait = <11>; 850 phys = <&usb2_phy0 3>; 851 phy-names = "usb"; 852 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 853 resets = <&cpg 704>, <&cpg 703>; 854 status = "disabled"; 855 }; 856 857 usb_dmac0: dma-controller@e65a0000 { 858 compatible = "renesas,r8a774e1-usb-dmac", 859 "renesas,usb-dmac"; 860 reg = <0 0xe65a0000 0 0x100>; 861 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 863 interrupt-names = "ch0", "ch1"; 864 clocks = <&cpg CPG_MOD 330>; 865 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 866 resets = <&cpg 330>; 867 #dma-cells = <1>; 868 dma-channels = <2>; 869 }; 870 871 usb_dmac1: dma-controller@e65b0000 { 872 compatible = "renesas,r8a774e1-usb-dmac", 873 "renesas,usb-dmac"; 874 reg = <0 0xe65b0000 0 0x100>; 875 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 877 interrupt-names = "ch0", "ch1"; 878 clocks = <&cpg CPG_MOD 331>; 879 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 880 resets = <&cpg 331>; 881 #dma-cells = <1>; 882 dma-channels = <2>; 883 }; 884 885 usb3_phy0: usb-phy@e65ee000 { 886 compatible = "renesas,r8a774e1-usb3-phy", 887 "renesas,rcar-gen3-usb3-phy"; 888 reg = <0 0xe65ee000 0 0x90>; 889 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 890 <&usb_extal_clk>; 891 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 892 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 893 resets = <&cpg 328>; 894 #phy-cells = <0>; 895 status = "disabled"; 896 }; 897 898 dmac0: dma-controller@e6700000 { 899 compatible = "renesas,dmac-r8a774e1", 900 "renesas,rcar-dmac"; 901 reg = <0 0xe6700000 0 0x10000>; 902 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 918 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 919 interrupt-names = "error", 920 "ch0", "ch1", "ch2", "ch3", 921 "ch4", "ch5", "ch6", "ch7", 922 "ch8", "ch9", "ch10", "ch11", 923 "ch12", "ch13", "ch14", "ch15"; 924 clocks = <&cpg CPG_MOD 219>; 925 clock-names = "fck"; 926 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 927 resets = <&cpg 219>; 928 #dma-cells = <1>; 929 dma-channels = <16>; 930 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 931 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 932 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 933 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 934 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 935 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 936 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 937 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 938 }; 939 940 dmac1: dma-controller@e7300000 { 941 compatible = "renesas,dmac-r8a774e1", 942 "renesas,rcar-dmac"; 943 reg = <0 0xe7300000 0 0x10000>; 944 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 961 interrupt-names = "error", 962 "ch0", "ch1", "ch2", "ch3", 963 "ch4", "ch5", "ch6", "ch7", 964 "ch8", "ch9", "ch10", "ch11", 965 "ch12", "ch13", "ch14", "ch15"; 966 clocks = <&cpg CPG_MOD 218>; 967 clock-names = "fck"; 968 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 969 resets = <&cpg 218>; 970 #dma-cells = <1>; 971 dma-channels = <16>; 972 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 973 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 974 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 975 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 976 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 977 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 978 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 979 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 980 }; 981 982 dmac2: dma-controller@e7310000 { 983 compatible = "renesas,dmac-r8a774e1", 984 "renesas,rcar-dmac"; 985 reg = <0 0xe7310000 0 0x10000>; 986 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 1001 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 1002 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 1003 interrupt-names = "error", 1004 "ch0", "ch1", "ch2", "ch3", 1005 "ch4", "ch5", "ch6", "ch7", 1006 "ch8", "ch9", "ch10", "ch11", 1007 "ch12", "ch13", "ch14", "ch15"; 1008 clocks = <&cpg CPG_MOD 217>; 1009 clock-names = "fck"; 1010 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1011 resets = <&cpg 217>; 1012 #dma-cells = <1>; 1013 dma-channels = <16>; 1014 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 1015 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 1016 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 1017 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 1018 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 1019 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 1020 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 1021 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 1022 }; 1023 1024 ipmmu_ds0: iommu@e6740000 { 1025 compatible = "renesas,ipmmu-r8a774e1"; 1026 reg = <0 0xe6740000 0 0x1000>; 1027 renesas,ipmmu-main = <&ipmmu_mm 0>; 1028 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1029 #iommu-cells = <1>; 1030 }; 1031 1032 ipmmu_ds1: iommu@e7740000 { 1033 compatible = "renesas,ipmmu-r8a774e1"; 1034 reg = <0 0xe7740000 0 0x1000>; 1035 renesas,ipmmu-main = <&ipmmu_mm 1>; 1036 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1037 #iommu-cells = <1>; 1038 }; 1039 1040 ipmmu_hc: iommu@e6570000 { 1041 compatible = "renesas,ipmmu-r8a774e1"; 1042 reg = <0 0xe6570000 0 0x1000>; 1043 renesas,ipmmu-main = <&ipmmu_mm 2>; 1044 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1045 #iommu-cells = <1>; 1046 }; 1047 1048 ipmmu_mm: iommu@e67b0000 { 1049 compatible = "renesas,ipmmu-r8a774e1"; 1050 reg = <0 0xe67b0000 0 0x1000>; 1051 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1053 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1054 #iommu-cells = <1>; 1055 }; 1056 1057 ipmmu_mp0: iommu@ec670000 { 1058 compatible = "renesas,ipmmu-r8a774e1"; 1059 reg = <0 0xec670000 0 0x1000>; 1060 renesas,ipmmu-main = <&ipmmu_mm 4>; 1061 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1062 #iommu-cells = <1>; 1063 }; 1064 1065 ipmmu_pv0: iommu@fd800000 { 1066 compatible = "renesas,ipmmu-r8a774e1"; 1067 reg = <0 0xfd800000 0 0x1000>; 1068 renesas,ipmmu-main = <&ipmmu_mm 6>; 1069 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1070 #iommu-cells = <1>; 1071 }; 1072 1073 ipmmu_pv1: iommu@fd950000 { 1074 compatible = "renesas,ipmmu-r8a774e1"; 1075 reg = <0 0xfd950000 0 0x1000>; 1076 renesas,ipmmu-main = <&ipmmu_mm 7>; 1077 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1078 #iommu-cells = <1>; 1079 }; 1080 1081 ipmmu_pv2: iommu@fd960000 { 1082 compatible = "renesas,ipmmu-r8a774e1"; 1083 reg = <0 0xfd960000 0 0x1000>; 1084 renesas,ipmmu-main = <&ipmmu_mm 8>; 1085 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1086 #iommu-cells = <1>; 1087 }; 1088 1089 ipmmu_pv3: iommu@fd970000 { 1090 compatible = "renesas,ipmmu-r8a774e1"; 1091 reg = <0 0xfd970000 0 0x1000>; 1092 renesas,ipmmu-main = <&ipmmu_mm 9>; 1093 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1094 #iommu-cells = <1>; 1095 }; 1096 1097 ipmmu_vc0: iommu@fe6b0000 { 1098 compatible = "renesas,ipmmu-r8a774e1"; 1099 reg = <0 0xfe6b0000 0 0x1000>; 1100 renesas,ipmmu-main = <&ipmmu_mm 12>; 1101 power-domains = <&sysc R8A774E1_PD_A3VC>; 1102 #iommu-cells = <1>; 1103 }; 1104 1105 ipmmu_vc1: iommu@fe6f0000 { 1106 compatible = "renesas,ipmmu-r8a774e1"; 1107 reg = <0 0xfe6f0000 0 0x1000>; 1108 renesas,ipmmu-main = <&ipmmu_mm 13>; 1109 power-domains = <&sysc R8A774E1_PD_A3VC>; 1110 #iommu-cells = <1>; 1111 }; 1112 1113 ipmmu_vi0: iommu@febd0000 { 1114 compatible = "renesas,ipmmu-r8a774e1"; 1115 reg = <0 0xfebd0000 0 0x1000>; 1116 renesas,ipmmu-main = <&ipmmu_mm 14>; 1117 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1118 #iommu-cells = <1>; 1119 }; 1120 1121 ipmmu_vi1: iommu@febe0000 { 1122 compatible = "renesas,ipmmu-r8a774e1"; 1123 reg = <0 0xfebe0000 0 0x1000>; 1124 renesas,ipmmu-main = <&ipmmu_mm 15>; 1125 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1126 #iommu-cells = <1>; 1127 }; 1128 1129 ipmmu_vp0: iommu@fe990000 { 1130 compatible = "renesas,ipmmu-r8a774e1"; 1131 reg = <0 0xfe990000 0 0x1000>; 1132 renesas,ipmmu-main = <&ipmmu_mm 16>; 1133 power-domains = <&sysc R8A774E1_PD_A3VP>; 1134 #iommu-cells = <1>; 1135 }; 1136 1137 ipmmu_vp1: iommu@fe980000 { 1138 compatible = "renesas,ipmmu-r8a774e1"; 1139 reg = <0 0xfe980000 0 0x1000>; 1140 renesas,ipmmu-main = <&ipmmu_mm 17>; 1141 power-domains = <&sysc R8A774E1_PD_A3VP>; 1142 #iommu-cells = <1>; 1143 }; 1144 1145 avb: ethernet@e6800000 { 1146 compatible = "renesas,etheravb-r8a774e1", 1147 "renesas,etheravb-rcar-gen3"; 1148 reg = <0 0xe6800000 0 0x800>; 1149 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1174 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1175 "ch4", "ch5", "ch6", "ch7", 1176 "ch8", "ch9", "ch10", "ch11", 1177 "ch12", "ch13", "ch14", "ch15", 1178 "ch16", "ch17", "ch18", "ch19", 1179 "ch20", "ch21", "ch22", "ch23", 1180 "ch24"; 1181 clocks = <&cpg CPG_MOD 812>; 1182 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1183 resets = <&cpg 812>; 1184 phy-mode = "rgmii"; 1185 iommus = <&ipmmu_ds0 16>; 1186 #address-cells = <1>; 1187 #size-cells = <0>; 1188 status = "disabled"; 1189 }; 1190 1191 can0: can@e6c30000 { 1192 compatible = "renesas,can-r8a774e1", 1193 "renesas,rcar-gen3-can"; 1194 reg = <0 0xe6c30000 0 0x1000>; 1195 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1196 clocks = <&cpg CPG_MOD 916>, 1197 <&cpg CPG_CORE R8A774E1_CLK_CANFD>, 1198 <&can_clk>; 1199 clock-names = "clkp1", "clkp2", "can_clk"; 1200 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; 1201 assigned-clock-rates = <40000000>; 1202 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1203 resets = <&cpg 916>; 1204 status = "disabled"; 1205 }; 1206 1207 can1: can@e6c38000 { 1208 compatible = "renesas,can-r8a774e1", 1209 "renesas,rcar-gen3-can"; 1210 reg = <0 0xe6c38000 0 0x1000>; 1211 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1212 clocks = <&cpg CPG_MOD 915>, 1213 <&cpg CPG_CORE R8A774E1_CLK_CANFD>, 1214 <&can_clk>; 1215 clock-names = "clkp1", "clkp2", "can_clk"; 1216 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; 1217 assigned-clock-rates = <40000000>; 1218 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1219 resets = <&cpg 915>; 1220 status = "disabled"; 1221 }; 1222 1223 canfd: can@e66c0000 { 1224 compatible = "renesas,r8a774e1-canfd", 1225 "renesas,rcar-gen3-canfd"; 1226 reg = <0 0xe66c0000 0 0x8000>; 1227 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1229 clocks = <&cpg CPG_MOD 914>, 1230 <&cpg CPG_CORE R8A774E1_CLK_CANFD>, 1231 <&can_clk>; 1232 clock-names = "fck", "canfd", "can_clk"; 1233 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; 1234 assigned-clock-rates = <40000000>; 1235 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1236 resets = <&cpg 914>; 1237 status = "disabled"; 1238 1239 channel0 { 1240 status = "disabled"; 1241 }; 1242 1243 channel1 { 1244 status = "disabled"; 1245 }; 1246 }; 1247 1248 pwm0: pwm@e6e30000 { 1249 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; 1250 reg = <0 0xe6e30000 0 0x8>; 1251 clocks = <&cpg CPG_MOD 523>; 1252 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1253 resets = <&cpg 523>; 1254 #pwm-cells = <2>; 1255 status = "disabled"; 1256 }; 1257 1258 pwm1: pwm@e6e31000 { 1259 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; 1260 reg = <0 0xe6e31000 0 0x8>; 1261 clocks = <&cpg CPG_MOD 523>; 1262 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1263 resets = <&cpg 523>; 1264 #pwm-cells = <2>; 1265 status = "disabled"; 1266 }; 1267 1268 pwm2: pwm@e6e32000 { 1269 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; 1270 reg = <0 0xe6e32000 0 0x8>; 1271 clocks = <&cpg CPG_MOD 523>; 1272 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1273 resets = <&cpg 523>; 1274 #pwm-cells = <2>; 1275 status = "disabled"; 1276 }; 1277 1278 pwm3: pwm@e6e33000 { 1279 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; 1280 reg = <0 0xe6e33000 0 0x8>; 1281 clocks = <&cpg CPG_MOD 523>; 1282 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1283 resets = <&cpg 523>; 1284 #pwm-cells = <2>; 1285 status = "disabled"; 1286 }; 1287 1288 pwm4: pwm@e6e34000 { 1289 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; 1290 reg = <0 0xe6e34000 0 0x8>; 1291 clocks = <&cpg CPG_MOD 523>; 1292 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1293 resets = <&cpg 523>; 1294 #pwm-cells = <2>; 1295 status = "disabled"; 1296 }; 1297 1298 pwm5: pwm@e6e35000 { 1299 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; 1300 reg = <0 0xe6e35000 0 0x8>; 1301 clocks = <&cpg CPG_MOD 523>; 1302 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1303 resets = <&cpg 523>; 1304 #pwm-cells = <2>; 1305 status = "disabled"; 1306 }; 1307 1308 pwm6: pwm@e6e36000 { 1309 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; 1310 reg = <0 0xe6e36000 0 0x8>; 1311 clocks = <&cpg CPG_MOD 523>; 1312 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1313 resets = <&cpg 523>; 1314 #pwm-cells = <2>; 1315 status = "disabled"; 1316 }; 1317 1318 scif0: serial@e6e60000 { 1319 compatible = "renesas,scif-r8a774e1", 1320 "renesas,rcar-gen3-scif", "renesas,scif"; 1321 reg = <0 0xe6e60000 0 0x40>; 1322 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1323 clocks = <&cpg CPG_MOD 207>, 1324 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1325 <&scif_clk>; 1326 clock-names = "fck", "brg_int", "scif_clk"; 1327 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1328 <&dmac2 0x51>, <&dmac2 0x50>; 1329 dma-names = "tx", "rx", "tx", "rx"; 1330 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1331 resets = <&cpg 207>; 1332 status = "disabled"; 1333 }; 1334 1335 scif1: serial@e6e68000 { 1336 compatible = "renesas,scif-r8a774e1", 1337 "renesas,rcar-gen3-scif", "renesas,scif"; 1338 reg = <0 0xe6e68000 0 0x40>; 1339 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1340 clocks = <&cpg CPG_MOD 206>, 1341 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1342 <&scif_clk>; 1343 clock-names = "fck", "brg_int", "scif_clk"; 1344 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1345 <&dmac2 0x53>, <&dmac2 0x52>; 1346 dma-names = "tx", "rx", "tx", "rx"; 1347 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1348 resets = <&cpg 206>; 1349 status = "disabled"; 1350 }; 1351 1352 scif2: serial@e6e88000 { 1353 compatible = "renesas,scif-r8a774e1", 1354 "renesas,rcar-gen3-scif", "renesas,scif"; 1355 reg = <0 0xe6e88000 0 0x40>; 1356 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1357 clocks = <&cpg CPG_MOD 310>, 1358 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1359 <&scif_clk>; 1360 clock-names = "fck", "brg_int", "scif_clk"; 1361 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1362 <&dmac2 0x13>, <&dmac2 0x12>; 1363 dma-names = "tx", "rx", "tx", "rx"; 1364 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1365 resets = <&cpg 310>; 1366 status = "disabled"; 1367 }; 1368 1369 scif3: serial@e6c50000 { 1370 compatible = "renesas,scif-r8a774e1", 1371 "renesas,rcar-gen3-scif", "renesas,scif"; 1372 reg = <0 0xe6c50000 0 0x40>; 1373 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1374 clocks = <&cpg CPG_MOD 204>, 1375 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1376 <&scif_clk>; 1377 clock-names = "fck", "brg_int", "scif_clk"; 1378 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1379 dma-names = "tx", "rx"; 1380 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1381 resets = <&cpg 204>; 1382 status = "disabled"; 1383 }; 1384 1385 scif4: serial@e6c40000 { 1386 compatible = "renesas,scif-r8a774e1", 1387 "renesas,rcar-gen3-scif", "renesas,scif"; 1388 reg = <0 0xe6c40000 0 0x40>; 1389 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1390 clocks = <&cpg CPG_MOD 203>, 1391 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1392 <&scif_clk>; 1393 clock-names = "fck", "brg_int", "scif_clk"; 1394 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1395 dma-names = "tx", "rx"; 1396 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1397 resets = <&cpg 203>; 1398 status = "disabled"; 1399 }; 1400 1401 scif5: serial@e6f30000 { 1402 compatible = "renesas,scif-r8a774e1", 1403 "renesas,rcar-gen3-scif", "renesas,scif"; 1404 reg = <0 0xe6f30000 0 0x40>; 1405 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1406 clocks = <&cpg CPG_MOD 202>, 1407 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1408 <&scif_clk>; 1409 clock-names = "fck", "brg_int", "scif_clk"; 1410 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1411 <&dmac2 0x5b>, <&dmac2 0x5a>; 1412 dma-names = "tx", "rx", "tx", "rx"; 1413 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1414 resets = <&cpg 202>; 1415 status = "disabled"; 1416 }; 1417 1418 msiof0: spi@e6e90000 { 1419 compatible = "renesas,msiof-r8a774e1", 1420 "renesas,rcar-gen3-msiof"; 1421 reg = <0 0xe6e90000 0 0x0064>; 1422 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1423 clocks = <&cpg CPG_MOD 211>; 1424 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1425 <&dmac2 0x41>, <&dmac2 0x40>; 1426 dma-names = "tx", "rx", "tx", "rx"; 1427 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1428 resets = <&cpg 211>; 1429 #address-cells = <1>; 1430 #size-cells = <0>; 1431 status = "disabled"; 1432 }; 1433 1434 msiof1: spi@e6ea0000 { 1435 compatible = "renesas,msiof-r8a774e1", 1436 "renesas,rcar-gen3-msiof"; 1437 reg = <0 0xe6ea0000 0 0x0064>; 1438 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1439 clocks = <&cpg CPG_MOD 210>; 1440 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1441 <&dmac2 0x43>, <&dmac2 0x42>; 1442 dma-names = "tx", "rx", "tx", "rx"; 1443 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1444 resets = <&cpg 210>; 1445 #address-cells = <1>; 1446 #size-cells = <0>; 1447 status = "disabled"; 1448 }; 1449 1450 msiof2: spi@e6c00000 { 1451 compatible = "renesas,msiof-r8a774e1", 1452 "renesas,rcar-gen3-msiof"; 1453 reg = <0 0xe6c00000 0 0x0064>; 1454 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1455 clocks = <&cpg CPG_MOD 209>; 1456 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1457 dma-names = "tx", "rx"; 1458 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1459 resets = <&cpg 209>; 1460 #address-cells = <1>; 1461 #size-cells = <0>; 1462 status = "disabled"; 1463 }; 1464 1465 msiof3: spi@e6c10000 { 1466 compatible = "renesas,msiof-r8a774e1", 1467 "renesas,rcar-gen3-msiof"; 1468 reg = <0 0xe6c10000 0 0x0064>; 1469 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1470 clocks = <&cpg CPG_MOD 208>; 1471 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1472 dma-names = "tx", "rx"; 1473 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1474 resets = <&cpg 208>; 1475 #address-cells = <1>; 1476 #size-cells = <0>; 1477 status = "disabled"; 1478 }; 1479 1480 vin0: video@e6ef0000 { 1481 compatible = "renesas,vin-r8a774e1"; 1482 reg = <0 0xe6ef0000 0 0x1000>; 1483 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1484 clocks = <&cpg CPG_MOD 811>; 1485 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1486 resets = <&cpg 811>; 1487 renesas,id = <0>; 1488 status = "disabled"; 1489 1490 ports { 1491 #address-cells = <1>; 1492 #size-cells = <0>; 1493 1494 port@1 { 1495 #address-cells = <1>; 1496 #size-cells = <0>; 1497 1498 reg = <1>; 1499 1500 vin0csi20: endpoint@0 { 1501 reg = <0>; 1502 remote-endpoint = <&csi20vin0>; 1503 }; 1504 vin0csi40: endpoint@2 { 1505 reg = <2>; 1506 remote-endpoint = <&csi40vin0>; 1507 }; 1508 }; 1509 }; 1510 }; 1511 1512 vin1: video@e6ef1000 { 1513 compatible = "renesas,vin-r8a774e1"; 1514 reg = <0 0xe6ef1000 0 0x1000>; 1515 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1516 clocks = <&cpg CPG_MOD 810>; 1517 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1518 resets = <&cpg 810>; 1519 renesas,id = <1>; 1520 status = "disabled"; 1521 1522 ports { 1523 #address-cells = <1>; 1524 #size-cells = <0>; 1525 1526 port@1 { 1527 #address-cells = <1>; 1528 #size-cells = <0>; 1529 1530 reg = <1>; 1531 1532 vin1csi20: endpoint@0 { 1533 reg = <0>; 1534 remote-endpoint = <&csi20vin1>; 1535 }; 1536 vin1csi40: endpoint@2 { 1537 reg = <2>; 1538 remote-endpoint = <&csi40vin1>; 1539 }; 1540 }; 1541 }; 1542 }; 1543 1544 vin2: video@e6ef2000 { 1545 compatible = "renesas,vin-r8a774e1"; 1546 reg = <0 0xe6ef2000 0 0x1000>; 1547 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1548 clocks = <&cpg CPG_MOD 809>; 1549 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1550 resets = <&cpg 809>; 1551 renesas,id = <2>; 1552 status = "disabled"; 1553 1554 ports { 1555 #address-cells = <1>; 1556 #size-cells = <0>; 1557 1558 port@1 { 1559 #address-cells = <1>; 1560 #size-cells = <0>; 1561 1562 reg = <1>; 1563 1564 vin2csi20: endpoint@0 { 1565 reg = <0>; 1566 remote-endpoint = <&csi20vin2>; 1567 }; 1568 vin2csi40: endpoint@2 { 1569 reg = <2>; 1570 remote-endpoint = <&csi40vin2>; 1571 }; 1572 }; 1573 }; 1574 }; 1575 1576 vin3: video@e6ef3000 { 1577 compatible = "renesas,vin-r8a774e1"; 1578 reg = <0 0xe6ef3000 0 0x1000>; 1579 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1580 clocks = <&cpg CPG_MOD 808>; 1581 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1582 resets = <&cpg 808>; 1583 renesas,id = <3>; 1584 status = "disabled"; 1585 1586 ports { 1587 #address-cells = <1>; 1588 #size-cells = <0>; 1589 1590 port@1 { 1591 #address-cells = <1>; 1592 #size-cells = <0>; 1593 1594 reg = <1>; 1595 1596 vin3csi20: endpoint@0 { 1597 reg = <0>; 1598 remote-endpoint = <&csi20vin3>; 1599 }; 1600 vin3csi40: endpoint@2 { 1601 reg = <2>; 1602 remote-endpoint = <&csi40vin3>; 1603 }; 1604 }; 1605 }; 1606 }; 1607 1608 vin4: video@e6ef4000 { 1609 compatible = "renesas,vin-r8a774e1"; 1610 reg = <0 0xe6ef4000 0 0x1000>; 1611 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1612 clocks = <&cpg CPG_MOD 807>; 1613 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1614 resets = <&cpg 807>; 1615 renesas,id = <4>; 1616 status = "disabled"; 1617 1618 ports { 1619 #address-cells = <1>; 1620 #size-cells = <0>; 1621 1622 port@1 { 1623 #address-cells = <1>; 1624 #size-cells = <0>; 1625 1626 reg = <1>; 1627 1628 vin4csi20: endpoint@0 { 1629 reg = <0>; 1630 remote-endpoint = <&csi20vin4>; 1631 }; 1632 }; 1633 }; 1634 }; 1635 1636 vin5: video@e6ef5000 { 1637 compatible = "renesas,vin-r8a774e1"; 1638 reg = <0 0xe6ef5000 0 0x1000>; 1639 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1640 clocks = <&cpg CPG_MOD 806>; 1641 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1642 resets = <&cpg 806>; 1643 renesas,id = <5>; 1644 status = "disabled"; 1645 1646 ports { 1647 #address-cells = <1>; 1648 #size-cells = <0>; 1649 1650 port@1 { 1651 #address-cells = <1>; 1652 #size-cells = <0>; 1653 1654 reg = <1>; 1655 1656 vin5csi20: endpoint@0 { 1657 reg = <0>; 1658 remote-endpoint = <&csi20vin5>; 1659 }; 1660 }; 1661 }; 1662 }; 1663 1664 vin6: video@e6ef6000 { 1665 compatible = "renesas,vin-r8a774e1"; 1666 reg = <0 0xe6ef6000 0 0x1000>; 1667 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1668 clocks = <&cpg CPG_MOD 805>; 1669 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1670 resets = <&cpg 805>; 1671 renesas,id = <6>; 1672 status = "disabled"; 1673 1674 ports { 1675 #address-cells = <1>; 1676 #size-cells = <0>; 1677 1678 port@1 { 1679 #address-cells = <1>; 1680 #size-cells = <0>; 1681 1682 reg = <1>; 1683 1684 vin6csi20: endpoint@0 { 1685 reg = <0>; 1686 remote-endpoint = <&csi20vin6>; 1687 }; 1688 }; 1689 }; 1690 }; 1691 1692 vin7: video@e6ef7000 { 1693 compatible = "renesas,vin-r8a774e1"; 1694 reg = <0 0xe6ef7000 0 0x1000>; 1695 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 1696 clocks = <&cpg CPG_MOD 804>; 1697 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1698 resets = <&cpg 804>; 1699 renesas,id = <7>; 1700 status = "disabled"; 1701 1702 ports { 1703 #address-cells = <1>; 1704 #size-cells = <0>; 1705 1706 port@1 { 1707 #address-cells = <1>; 1708 #size-cells = <0>; 1709 1710 reg = <1>; 1711 1712 vin7csi20: endpoint@0 { 1713 reg = <0>; 1714 remote-endpoint = <&csi20vin7>; 1715 }; 1716 }; 1717 }; 1718 }; 1719 1720 rcar_sound: sound@ec500000 { 1721 /* 1722 * #sound-dai-cells is required 1723 * 1724 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1725 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1726 */ 1727 /* 1728 * #clock-cells is required for audio_clkout0/1/2/3 1729 * 1730 * clkout : #clock-cells = <0>; <&rcar_sound>; 1731 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1732 */ 1733 compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3"; 1734 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1735 <0 0xec5a0000 0 0x100>, /* ADG */ 1736 <0 0xec540000 0 0x1000>, /* SSIU */ 1737 <0 0xec541000 0 0x280>, /* SSI */ 1738 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1739 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1740 1741 clocks = <&cpg CPG_MOD 1005>, 1742 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1743 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1744 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1745 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1746 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1747 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1748 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1749 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1750 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1751 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1752 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1753 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1754 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1755 <&audio_clk_a>, <&audio_clk_b>, 1756 <&audio_clk_c>, 1757 <&cpg CPG_CORE R8A774E1_CLK_S0D4>; 1758 clock-names = "ssi-all", 1759 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1760 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1761 "ssi.1", "ssi.0", 1762 "src.9", "src.8", "src.7", "src.6", 1763 "src.5", "src.4", "src.3", "src.2", 1764 "src.1", "src.0", 1765 "mix.1", "mix.0", 1766 "ctu.1", "ctu.0", 1767 "dvc.0", "dvc.1", 1768 "clk_a", "clk_b", "clk_c", "clk_i"; 1769 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1770 resets = <&cpg 1005>, 1771 <&cpg 1006>, <&cpg 1007>, 1772 <&cpg 1008>, <&cpg 1009>, 1773 <&cpg 1010>, <&cpg 1011>, 1774 <&cpg 1012>, <&cpg 1013>, 1775 <&cpg 1014>, <&cpg 1015>; 1776 reset-names = "ssi-all", 1777 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1778 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1779 "ssi.1", "ssi.0"; 1780 status = "disabled"; 1781 1782 rcar_sound,dvc { 1783 dvc0: dvc-0 { 1784 dmas = <&audma1 0xbc>; 1785 dma-names = "tx"; 1786 }; 1787 dvc1: dvc-1 { 1788 dmas = <&audma1 0xbe>; 1789 dma-names = "tx"; 1790 }; 1791 }; 1792 1793 rcar_sound,mix { 1794 mix0: mix-0 { }; 1795 mix1: mix-1 { }; 1796 }; 1797 1798 rcar_sound,ctu { 1799 ctu00: ctu-0 { }; 1800 ctu01: ctu-1 { }; 1801 ctu02: ctu-2 { }; 1802 ctu03: ctu-3 { }; 1803 ctu10: ctu-4 { }; 1804 ctu11: ctu-5 { }; 1805 ctu12: ctu-6 { }; 1806 ctu13: ctu-7 { }; 1807 }; 1808 1809 rcar_sound,src { 1810 src0: src-0 { 1811 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1812 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1813 dma-names = "rx", "tx"; 1814 }; 1815 src1: src-1 { 1816 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1817 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1818 dma-names = "rx", "tx"; 1819 }; 1820 src2: src-2 { 1821 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1822 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1823 dma-names = "rx", "tx"; 1824 }; 1825 src3: src-3 { 1826 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1827 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1828 dma-names = "rx", "tx"; 1829 }; 1830 src4: src-4 { 1831 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1832 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1833 dma-names = "rx", "tx"; 1834 }; 1835 src5: src-5 { 1836 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1837 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1838 dma-names = "rx", "tx"; 1839 }; 1840 src6: src-6 { 1841 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1842 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1843 dma-names = "rx", "tx"; 1844 }; 1845 src7: src-7 { 1846 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1847 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1848 dma-names = "rx", "tx"; 1849 }; 1850 src8: src-8 { 1851 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1852 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1853 dma-names = "rx", "tx"; 1854 }; 1855 src9: src-9 { 1856 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1857 dmas = <&audma0 0x97>, <&audma1 0xba>; 1858 dma-names = "rx", "tx"; 1859 }; 1860 }; 1861 1862 rcar_sound,ssiu { 1863 ssiu00: ssiu-0 { 1864 dmas = <&audma0 0x15>, <&audma1 0x16>; 1865 dma-names = "rx", "tx"; 1866 }; 1867 ssiu01: ssiu-1 { 1868 dmas = <&audma0 0x35>, <&audma1 0x36>; 1869 dma-names = "rx", "tx"; 1870 }; 1871 ssiu02: ssiu-2 { 1872 dmas = <&audma0 0x37>, <&audma1 0x38>; 1873 dma-names = "rx", "tx"; 1874 }; 1875 ssiu03: ssiu-3 { 1876 dmas = <&audma0 0x47>, <&audma1 0x48>; 1877 dma-names = "rx", "tx"; 1878 }; 1879 ssiu04: ssiu-4 { 1880 dmas = <&audma0 0x3F>, <&audma1 0x40>; 1881 dma-names = "rx", "tx"; 1882 }; 1883 ssiu05: ssiu-5 { 1884 dmas = <&audma0 0x43>, <&audma1 0x44>; 1885 dma-names = "rx", "tx"; 1886 }; 1887 ssiu06: ssiu-6 { 1888 dmas = <&audma0 0x4F>, <&audma1 0x50>; 1889 dma-names = "rx", "tx"; 1890 }; 1891 ssiu07: ssiu-7 { 1892 dmas = <&audma0 0x53>, <&audma1 0x54>; 1893 dma-names = "rx", "tx"; 1894 }; 1895 ssiu10: ssiu-8 { 1896 dmas = <&audma0 0x49>, <&audma1 0x4a>; 1897 dma-names = "rx", "tx"; 1898 }; 1899 ssiu11: ssiu-9 { 1900 dmas = <&audma0 0x4B>, <&audma1 0x4C>; 1901 dma-names = "rx", "tx"; 1902 }; 1903 ssiu12: ssiu-10 { 1904 dmas = <&audma0 0x57>, <&audma1 0x58>; 1905 dma-names = "rx", "tx"; 1906 }; 1907 ssiu13: ssiu-11 { 1908 dmas = <&audma0 0x59>, <&audma1 0x5A>; 1909 dma-names = "rx", "tx"; 1910 }; 1911 ssiu14: ssiu-12 { 1912 dmas = <&audma0 0x5F>, <&audma1 0x60>; 1913 dma-names = "rx", "tx"; 1914 }; 1915 ssiu15: ssiu-13 { 1916 dmas = <&audma0 0xC3>, <&audma1 0xC4>; 1917 dma-names = "rx", "tx"; 1918 }; 1919 ssiu16: ssiu-14 { 1920 dmas = <&audma0 0xC7>, <&audma1 0xC8>; 1921 dma-names = "rx", "tx"; 1922 }; 1923 ssiu17: ssiu-15 { 1924 dmas = <&audma0 0xCB>, <&audma1 0xCC>; 1925 dma-names = "rx", "tx"; 1926 }; 1927 ssiu20: ssiu-16 { 1928 dmas = <&audma0 0x63>, <&audma1 0x64>; 1929 dma-names = "rx", "tx"; 1930 }; 1931 ssiu21: ssiu-17 { 1932 dmas = <&audma0 0x67>, <&audma1 0x68>; 1933 dma-names = "rx", "tx"; 1934 }; 1935 ssiu22: ssiu-18 { 1936 dmas = <&audma0 0x6B>, <&audma1 0x6C>; 1937 dma-names = "rx", "tx"; 1938 }; 1939 ssiu23: ssiu-19 { 1940 dmas = <&audma0 0x6D>, <&audma1 0x6E>; 1941 dma-names = "rx", "tx"; 1942 }; 1943 ssiu24: ssiu-20 { 1944 dmas = <&audma0 0xCF>, <&audma1 0xCE>; 1945 dma-names = "rx", "tx"; 1946 }; 1947 ssiu25: ssiu-21 { 1948 dmas = <&audma0 0xEB>, <&audma1 0xEC>; 1949 dma-names = "rx", "tx"; 1950 }; 1951 ssiu26: ssiu-22 { 1952 dmas = <&audma0 0xED>, <&audma1 0xEE>; 1953 dma-names = "rx", "tx"; 1954 }; 1955 ssiu27: ssiu-23 { 1956 dmas = <&audma0 0xEF>, <&audma1 0xF0>; 1957 dma-names = "rx", "tx"; 1958 }; 1959 ssiu30: ssiu-24 { 1960 dmas = <&audma0 0x6f>, <&audma1 0x70>; 1961 dma-names = "rx", "tx"; 1962 }; 1963 ssiu31: ssiu-25 { 1964 dmas = <&audma0 0x21>, <&audma1 0x22>; 1965 dma-names = "rx", "tx"; 1966 }; 1967 ssiu32: ssiu-26 { 1968 dmas = <&audma0 0x23>, <&audma1 0x24>; 1969 dma-names = "rx", "tx"; 1970 }; 1971 ssiu33: ssiu-27 { 1972 dmas = <&audma0 0x25>, <&audma1 0x26>; 1973 dma-names = "rx", "tx"; 1974 }; 1975 ssiu34: ssiu-28 { 1976 dmas = <&audma0 0x27>, <&audma1 0x28>; 1977 dma-names = "rx", "tx"; 1978 }; 1979 ssiu35: ssiu-29 { 1980 dmas = <&audma0 0x29>, <&audma1 0x2A>; 1981 dma-names = "rx", "tx"; 1982 }; 1983 ssiu36: ssiu-30 { 1984 dmas = <&audma0 0x2B>, <&audma1 0x2C>; 1985 dma-names = "rx", "tx"; 1986 }; 1987 ssiu37: ssiu-31 { 1988 dmas = <&audma0 0x2D>, <&audma1 0x2E>; 1989 dma-names = "rx", "tx"; 1990 }; 1991 ssiu40: ssiu-32 { 1992 dmas = <&audma0 0x71>, <&audma1 0x72>; 1993 dma-names = "rx", "tx"; 1994 }; 1995 ssiu41: ssiu-33 { 1996 dmas = <&audma0 0x17>, <&audma1 0x18>; 1997 dma-names = "rx", "tx"; 1998 }; 1999 ssiu42: ssiu-34 { 2000 dmas = <&audma0 0x19>, <&audma1 0x1A>; 2001 dma-names = "rx", "tx"; 2002 }; 2003 ssiu43: ssiu-35 { 2004 dmas = <&audma0 0x1B>, <&audma1 0x1C>; 2005 dma-names = "rx", "tx"; 2006 }; 2007 ssiu44: ssiu-36 { 2008 dmas = <&audma0 0x1D>, <&audma1 0x1E>; 2009 dma-names = "rx", "tx"; 2010 }; 2011 ssiu45: ssiu-37 { 2012 dmas = <&audma0 0x1F>, <&audma1 0x20>; 2013 dma-names = "rx", "tx"; 2014 }; 2015 ssiu46: ssiu-38 { 2016 dmas = <&audma0 0x31>, <&audma1 0x32>; 2017 dma-names = "rx", "tx"; 2018 }; 2019 ssiu47: ssiu-39 { 2020 dmas = <&audma0 0x33>, <&audma1 0x34>; 2021 dma-names = "rx", "tx"; 2022 }; 2023 ssiu50: ssiu-40 { 2024 dmas = <&audma0 0x73>, <&audma1 0x74>; 2025 dma-names = "rx", "tx"; 2026 }; 2027 ssiu60: ssiu-41 { 2028 dmas = <&audma0 0x75>, <&audma1 0x76>; 2029 dma-names = "rx", "tx"; 2030 }; 2031 ssiu70: ssiu-42 { 2032 dmas = <&audma0 0x79>, <&audma1 0x7a>; 2033 dma-names = "rx", "tx"; 2034 }; 2035 ssiu80: ssiu-43 { 2036 dmas = <&audma0 0x7b>, <&audma1 0x7c>; 2037 dma-names = "rx", "tx"; 2038 }; 2039 ssiu90: ssiu-44 { 2040 dmas = <&audma0 0x7d>, <&audma1 0x7e>; 2041 dma-names = "rx", "tx"; 2042 }; 2043 ssiu91: ssiu-45 { 2044 dmas = <&audma0 0x7F>, <&audma1 0x80>; 2045 dma-names = "rx", "tx"; 2046 }; 2047 ssiu92: ssiu-46 { 2048 dmas = <&audma0 0x81>, <&audma1 0x82>; 2049 dma-names = "rx", "tx"; 2050 }; 2051 ssiu93: ssiu-47 { 2052 dmas = <&audma0 0x83>, <&audma1 0x84>; 2053 dma-names = "rx", "tx"; 2054 }; 2055 ssiu94: ssiu-48 { 2056 dmas = <&audma0 0xA3>, <&audma1 0xA4>; 2057 dma-names = "rx", "tx"; 2058 }; 2059 ssiu95: ssiu-49 { 2060 dmas = <&audma0 0xA5>, <&audma1 0xA6>; 2061 dma-names = "rx", "tx"; 2062 }; 2063 ssiu96: ssiu-50 { 2064 dmas = <&audma0 0xA7>, <&audma1 0xA8>; 2065 dma-names = "rx", "tx"; 2066 }; 2067 ssiu97: ssiu-51 { 2068 dmas = <&audma0 0xA9>, <&audma1 0xAA>; 2069 dma-names = "rx", "tx"; 2070 }; 2071 }; 2072 2073 rcar_sound,ssi { 2074 ssi0: ssi-0 { 2075 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 2076 dmas = <&audma0 0x01>, <&audma1 0x02>; 2077 dma-names = "rx", "tx"; 2078 }; 2079 ssi1: ssi-1 { 2080 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 2081 dmas = <&audma0 0x03>, <&audma1 0x04>; 2082 dma-names = "rx", "tx"; 2083 }; 2084 ssi2: ssi-2 { 2085 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 2086 dmas = <&audma0 0x05>, <&audma1 0x06>; 2087 dma-names = "rx", "tx"; 2088 }; 2089 ssi3: ssi-3 { 2090 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2091 dmas = <&audma0 0x07>, <&audma1 0x08>; 2092 dma-names = "rx", "tx"; 2093 }; 2094 ssi4: ssi-4 { 2095 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 2096 dmas = <&audma0 0x09>, <&audma1 0x0a>; 2097 dma-names = "rx", "tx"; 2098 }; 2099 ssi5: ssi-5 { 2100 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 2101 dmas = <&audma0 0x0b>, <&audma1 0x0c>; 2102 dma-names = "rx", "tx"; 2103 }; 2104 ssi6: ssi-6 { 2105 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 2106 dmas = <&audma0 0x0d>, <&audma1 0x0e>; 2107 dma-names = "rx", "tx"; 2108 }; 2109 ssi7: ssi-7 { 2110 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 2111 dmas = <&audma0 0x0f>, <&audma1 0x10>; 2112 dma-names = "rx", "tx"; 2113 }; 2114 ssi8: ssi-8 { 2115 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 2116 dmas = <&audma0 0x11>, <&audma1 0x12>; 2117 dma-names = "rx", "tx"; 2118 }; 2119 ssi9: ssi-9 { 2120 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 2121 dmas = <&audma0 0x13>, <&audma1 0x14>; 2122 dma-names = "rx", "tx"; 2123 }; 2124 }; 2125 }; 2126 2127 audma0: dma-controller@ec700000 { 2128 compatible = "renesas,dmac-r8a774e1", 2129 "renesas,rcar-dmac"; 2130 reg = <0 0xec700000 0 0x10000>; 2131 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 2132 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2133 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2134 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2135 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2136 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2137 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2138 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2139 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2140 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2142 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2143 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2144 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2145 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2146 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2147 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 2148 interrupt-names = "error", 2149 "ch0", "ch1", "ch2", "ch3", 2150 "ch4", "ch5", "ch6", "ch7", 2151 "ch8", "ch9", "ch10", "ch11", 2152 "ch12", "ch13", "ch14", "ch15"; 2153 clocks = <&cpg CPG_MOD 502>; 2154 clock-names = "fck"; 2155 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2156 resets = <&cpg 502>; 2157 #dma-cells = <1>; 2158 dma-channels = <16>; 2159 iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, 2160 <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, 2161 <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, 2162 <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, 2163 <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, 2164 <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, 2165 <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, 2166 <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; 2167 }; 2168 2169 audma1: dma-controller@ec720000 { 2170 compatible = "renesas,dmac-r8a774e1", 2171 "renesas,rcar-dmac"; 2172 reg = <0 0xec720000 0 0x10000>; 2173 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 2174 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2175 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2176 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2177 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2178 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2179 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2180 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2181 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2182 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2183 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2184 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 2185 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2186 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 2187 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 2188 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 2189 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 2190 interrupt-names = "error", 2191 "ch0", "ch1", "ch2", "ch3", 2192 "ch4", "ch5", "ch6", "ch7", 2193 "ch8", "ch9", "ch10", "ch11", 2194 "ch12", "ch13", "ch14", "ch15"; 2195 clocks = <&cpg CPG_MOD 501>; 2196 clock-names = "fck"; 2197 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2198 resets = <&cpg 501>; 2199 #dma-cells = <1>; 2200 dma-channels = <16>; 2201 iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, 2202 <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, 2203 <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, 2204 <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, 2205 <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, 2206 <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, 2207 <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, 2208 <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; 2209 }; 2210 2211 xhci0: usb@ee000000 { 2212 compatible = "renesas,xhci-r8a774e1", 2213 "renesas,rcar-gen3-xhci"; 2214 reg = <0 0xee000000 0 0xc00>; 2215 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2216 clocks = <&cpg CPG_MOD 328>; 2217 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2218 resets = <&cpg 328>; 2219 status = "disabled"; 2220 }; 2221 2222 usb3_peri0: usb@ee020000 { 2223 compatible = "renesas,r8a774e1-usb3-peri", 2224 "renesas,rcar-gen3-usb3-peri"; 2225 reg = <0 0xee020000 0 0x400>; 2226 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2227 clocks = <&cpg CPG_MOD 328>; 2228 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2229 resets = <&cpg 328>; 2230 status = "disabled"; 2231 }; 2232 2233 ohci0: usb@ee080000 { 2234 compatible = "generic-ohci"; 2235 reg = <0 0xee080000 0 0x100>; 2236 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2237 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2238 phys = <&usb2_phy0 1>; 2239 phy-names = "usb"; 2240 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2241 resets = <&cpg 703>, <&cpg 704>; 2242 status = "disabled"; 2243 }; 2244 2245 ohci1: usb@ee0a0000 { 2246 compatible = "generic-ohci"; 2247 reg = <0 0xee0a0000 0 0x100>; 2248 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2249 clocks = <&cpg CPG_MOD 702>; 2250 phys = <&usb2_phy1 1>; 2251 phy-names = "usb"; 2252 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2253 resets = <&cpg 702>; 2254 status = "disabled"; 2255 }; 2256 2257 ehci0: usb@ee080100 { 2258 compatible = "generic-ehci"; 2259 reg = <0 0xee080100 0 0x100>; 2260 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2261 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2262 phys = <&usb2_phy0 2>; 2263 phy-names = "usb"; 2264 companion = <&ohci0>; 2265 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2266 resets = <&cpg 703>, <&cpg 704>; 2267 status = "disabled"; 2268 }; 2269 2270 ehci1: usb@ee0a0100 { 2271 compatible = "generic-ehci"; 2272 reg = <0 0xee0a0100 0 0x100>; 2273 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2274 clocks = <&cpg CPG_MOD 702>; 2275 phys = <&usb2_phy1 2>; 2276 phy-names = "usb"; 2277 companion = <&ohci1>; 2278 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2279 resets = <&cpg 702>; 2280 status = "disabled"; 2281 }; 2282 2283 usb2_phy0: usb-phy@ee080200 { 2284 compatible = "renesas,usb2-phy-r8a774e1", 2285 "renesas,rcar-gen3-usb2-phy"; 2286 reg = <0 0xee080200 0 0x700>; 2287 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2288 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2289 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2290 resets = <&cpg 703>, <&cpg 704>; 2291 #phy-cells = <1>; 2292 status = "disabled"; 2293 }; 2294 2295 usb2_phy1: usb-phy@ee0a0200 { 2296 compatible = "renesas,usb2-phy-r8a774e1", 2297 "renesas,rcar-gen3-usb2-phy"; 2298 reg = <0 0xee0a0200 0 0x700>; 2299 clocks = <&cpg CPG_MOD 702>; 2300 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2301 resets = <&cpg 702>; 2302 #phy-cells = <1>; 2303 status = "disabled"; 2304 }; 2305 2306 sdhi0: mmc@ee100000 { 2307 compatible = "renesas,sdhi-r8a774e1", 2308 "renesas,rcar-gen3-sdhi"; 2309 reg = <0 0xee100000 0 0x2000>; 2310 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 2311 clocks = <&cpg CPG_MOD 314>; 2312 max-frequency = <200000000>; 2313 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2314 resets = <&cpg 314>; 2315 iommus = <&ipmmu_ds1 32>; 2316 status = "disabled"; 2317 }; 2318 2319 sdhi1: mmc@ee120000 { 2320 compatible = "renesas,sdhi-r8a774e1", 2321 "renesas,rcar-gen3-sdhi"; 2322 reg = <0 0xee120000 0 0x2000>; 2323 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 2324 clocks = <&cpg CPG_MOD 313>; 2325 max-frequency = <200000000>; 2326 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2327 resets = <&cpg 313>; 2328 iommus = <&ipmmu_ds1 33>; 2329 status = "disabled"; 2330 }; 2331 2332 sdhi2: mmc@ee140000 { 2333 compatible = "renesas,sdhi-r8a774e1", 2334 "renesas,rcar-gen3-sdhi"; 2335 reg = <0 0xee140000 0 0x2000>; 2336 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 2337 clocks = <&cpg CPG_MOD 312>; 2338 max-frequency = <200000000>; 2339 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2340 resets = <&cpg 312>; 2341 iommus = <&ipmmu_ds1 34>; 2342 status = "disabled"; 2343 }; 2344 2345 sdhi3: mmc@ee160000 { 2346 compatible = "renesas,sdhi-r8a774e1", 2347 "renesas,rcar-gen3-sdhi"; 2348 reg = <0 0xee160000 0 0x2000>; 2349 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 2350 clocks = <&cpg CPG_MOD 311>; 2351 max-frequency = <200000000>; 2352 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2353 resets = <&cpg 311>; 2354 iommus = <&ipmmu_ds1 35>; 2355 status = "disabled"; 2356 }; 2357 2358 sata: sata@ee300000 { 2359 compatible = "renesas,sata-r8a774e1", 2360 "renesas,rcar-gen3-sata"; 2361 reg = <0 0xee300000 0 0x200000>; 2362 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2363 clocks = <&cpg CPG_MOD 815>; 2364 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2365 resets = <&cpg 815>; 2366 iommus = <&ipmmu_hc 2>; 2367 status = "disabled"; 2368 }; 2369 2370 gic: interrupt-controller@f1010000 { 2371 compatible = "arm,gic-400"; 2372 #interrupt-cells = <3>; 2373 #address-cells = <0>; 2374 interrupt-controller; 2375 reg = <0x0 0xf1010000 0 0x1000>, 2376 <0x0 0xf1020000 0 0x20000>, 2377 <0x0 0xf1040000 0 0x20000>, 2378 <0x0 0xf1060000 0 0x20000>; 2379 interrupts = <GIC_PPI 9 2380 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2381 clocks = <&cpg CPG_MOD 408>; 2382 clock-names = "clk"; 2383 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2384 resets = <&cpg 408>; 2385 }; 2386 2387 pciec0: pcie@fe000000 { 2388 compatible = "renesas,pcie-r8a774e1", 2389 "renesas,pcie-rcar-gen3"; 2390 reg = <0 0xfe000000 0 0x80000>; 2391 #address-cells = <3>; 2392 #size-cells = <2>; 2393 bus-range = <0x00 0xff>; 2394 device_type = "pci"; 2395 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 2396 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 2397 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 2398 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 2399 /* Map all possible DDR as inbound ranges */ 2400 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2401 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2402 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2403 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2404 #interrupt-cells = <1>; 2405 interrupt-map-mask = <0 0 0 0>; 2406 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2407 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 2408 clock-names = "pcie", "pcie_bus"; 2409 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2410 resets = <&cpg 319>; 2411 status = "disabled"; 2412 }; 2413 2414 pciec1: pcie@ee800000 { 2415 compatible = "renesas,pcie-r8a774e1", 2416 "renesas,pcie-rcar-gen3"; 2417 reg = <0 0xee800000 0 0x80000>; 2418 #address-cells = <3>; 2419 #size-cells = <2>; 2420 bus-range = <0x00 0xff>; 2421 device_type = "pci"; 2422 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, 2423 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, 2424 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, 2425 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 2426 /* Map all possible DDR as inbound ranges */ 2427 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2428 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2429 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2430 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2431 #interrupt-cells = <1>; 2432 interrupt-map-mask = <0 0 0 0>; 2433 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2434 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 2435 clock-names = "pcie", "pcie_bus"; 2436 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2437 resets = <&cpg 318>; 2438 status = "disabled"; 2439 }; 2440 2441 vspbc: vsp@fe920000 { 2442 compatible = "renesas,vsp2"; 2443 reg = <0 0xfe920000 0 0x8000>; 2444 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 2445 clocks = <&cpg CPG_MOD 624>; 2446 power-domains = <&sysc R8A774E1_PD_A3VP>; 2447 resets = <&cpg 624>; 2448 2449 renesas,fcp = <&fcpvb1>; 2450 }; 2451 2452 vspbd: vsp@fe960000 { 2453 compatible = "renesas,vsp2"; 2454 reg = <0 0xfe960000 0 0x8000>; 2455 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 2456 clocks = <&cpg CPG_MOD 626>; 2457 power-domains = <&sysc R8A774E1_PD_A3VP>; 2458 resets = <&cpg 626>; 2459 2460 renesas,fcp = <&fcpvb0>; 2461 }; 2462 2463 vspd0: vsp@fea20000 { 2464 compatible = "renesas,vsp2"; 2465 reg = <0 0xfea20000 0 0x5000>; 2466 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 2467 clocks = <&cpg CPG_MOD 623>; 2468 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2469 resets = <&cpg 623>; 2470 2471 renesas,fcp = <&fcpvd0>; 2472 }; 2473 2474 vspd1: vsp@fea28000 { 2475 compatible = "renesas,vsp2"; 2476 reg = <0 0xfea28000 0 0x5000>; 2477 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 2478 clocks = <&cpg CPG_MOD 622>; 2479 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2480 resets = <&cpg 622>; 2481 2482 renesas,fcp = <&fcpvd1>; 2483 }; 2484 2485 vspi0: vsp@fe9a0000 { 2486 compatible = "renesas,vsp2"; 2487 reg = <0 0xfe9a0000 0 0x8000>; 2488 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 2489 clocks = <&cpg CPG_MOD 631>; 2490 power-domains = <&sysc R8A774E1_PD_A3VP>; 2491 resets = <&cpg 631>; 2492 2493 renesas,fcp = <&fcpvi0>; 2494 }; 2495 2496 vspi1: vsp@fe9b0000 { 2497 compatible = "renesas,vsp2"; 2498 reg = <0 0xfe9b0000 0 0x8000>; 2499 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 2500 clocks = <&cpg CPG_MOD 630>; 2501 power-domains = <&sysc R8A774E1_PD_A3VP>; 2502 resets = <&cpg 630>; 2503 2504 renesas,fcp = <&fcpvi1>; 2505 }; 2506 2507 fdp1@fe940000 { 2508 compatible = "renesas,fdp1"; 2509 reg = <0 0xfe940000 0 0x2400>; 2510 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 2511 clocks = <&cpg CPG_MOD 119>; 2512 power-domains = <&sysc R8A774E1_PD_A3VP>; 2513 resets = <&cpg 119>; 2514 renesas,fcp = <&fcpf0>; 2515 }; 2516 2517 fdp1@fe944000 { 2518 compatible = "renesas,fdp1"; 2519 reg = <0 0xfe944000 0 0x2400>; 2520 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 2521 clocks = <&cpg CPG_MOD 118>; 2522 power-domains = <&sysc R8A774E1_PD_A3VP>; 2523 resets = <&cpg 118>; 2524 renesas,fcp = <&fcpf1>; 2525 }; 2526 2527 fcpf0: fcp@fe950000 { 2528 compatible = "renesas,fcpf"; 2529 reg = <0 0xfe950000 0 0x200>; 2530 clocks = <&cpg CPG_MOD 615>; 2531 power-domains = <&sysc R8A774E1_PD_A3VP>; 2532 resets = <&cpg 615>; 2533 }; 2534 2535 fcpf1: fcp@fe951000 { 2536 compatible = "renesas,fcpf"; 2537 reg = <0 0xfe951000 0 0x200>; 2538 clocks = <&cpg CPG_MOD 614>; 2539 power-domains = <&sysc R8A774E1_PD_A3VP>; 2540 resets = <&cpg 614>; 2541 }; 2542 2543 fcpvb0: fcp@fe96f000 { 2544 compatible = "renesas,fcpv"; 2545 reg = <0 0xfe96f000 0 0x200>; 2546 clocks = <&cpg CPG_MOD 607>; 2547 power-domains = <&sysc R8A774E1_PD_A3VP>; 2548 resets = <&cpg 607>; 2549 }; 2550 2551 fcpvb1: fcp@fe92f000 { 2552 compatible = "renesas,fcpv"; 2553 reg = <0 0xfe92f000 0 0x200>; 2554 clocks = <&cpg CPG_MOD 606>; 2555 power-domains = <&sysc R8A774E1_PD_A3VP>; 2556 resets = <&cpg 606>; 2557 }; 2558 2559 fcpvi0: fcp@fe9af000 { 2560 compatible = "renesas,fcpv"; 2561 reg = <0 0xfe9af000 0 0x200>; 2562 clocks = <&cpg CPG_MOD 611>; 2563 power-domains = <&sysc R8A774E1_PD_A3VP>; 2564 resets = <&cpg 611>; 2565 }; 2566 2567 fcpvi1: fcp@fe9bf000 { 2568 compatible = "renesas,fcpv"; 2569 reg = <0 0xfe9bf000 0 0x200>; 2570 clocks = <&cpg CPG_MOD 610>; 2571 power-domains = <&sysc R8A774E1_PD_A3VP>; 2572 resets = <&cpg 610>; 2573 }; 2574 2575 fcpvd0: fcp@fea27000 { 2576 compatible = "renesas,fcpv"; 2577 reg = <0 0xfea27000 0 0x200>; 2578 clocks = <&cpg CPG_MOD 603>; 2579 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2580 resets = <&cpg 603>; 2581 }; 2582 2583 fcpvd1: fcp@fea2f000 { 2584 compatible = "renesas,fcpv"; 2585 reg = <0 0xfea2f000 0 0x200>; 2586 clocks = <&cpg CPG_MOD 602>; 2587 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2588 resets = <&cpg 602>; 2589 }; 2590 2591 csi20: csi2@fea80000 { 2592 compatible = "renesas,r8a774e1-csi2"; 2593 reg = <0 0xfea80000 0 0x10000>; 2594 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2595 clocks = <&cpg CPG_MOD 714>; 2596 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2597 resets = <&cpg 714>; 2598 status = "disabled"; 2599 2600 ports { 2601 #address-cells = <1>; 2602 #size-cells = <0>; 2603 2604 port@1 { 2605 #address-cells = <1>; 2606 #size-cells = <0>; 2607 2608 reg = <1>; 2609 2610 csi20vin0: endpoint@0 { 2611 reg = <0>; 2612 remote-endpoint = <&vin0csi20>; 2613 }; 2614 csi20vin1: endpoint@1 { 2615 reg = <1>; 2616 remote-endpoint = <&vin1csi20>; 2617 }; 2618 csi20vin2: endpoint@2 { 2619 reg = <2>; 2620 remote-endpoint = <&vin2csi20>; 2621 }; 2622 csi20vin3: endpoint@3 { 2623 reg = <3>; 2624 remote-endpoint = <&vin3csi20>; 2625 }; 2626 csi20vin4: endpoint@4 { 2627 reg = <4>; 2628 remote-endpoint = <&vin4csi20>; 2629 }; 2630 csi20vin5: endpoint@5 { 2631 reg = <5>; 2632 remote-endpoint = <&vin5csi20>; 2633 }; 2634 csi20vin6: endpoint@6 { 2635 reg = <6>; 2636 remote-endpoint = <&vin6csi20>; 2637 }; 2638 csi20vin7: endpoint@7 { 2639 reg = <7>; 2640 remote-endpoint = <&vin7csi20>; 2641 }; 2642 }; 2643 }; 2644 }; 2645 2646 csi40: csi2@feaa0000 { 2647 compatible = "renesas,r8a774e1-csi2"; 2648 reg = <0 0xfeaa0000 0 0x10000>; 2649 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2650 clocks = <&cpg CPG_MOD 716>; 2651 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2652 resets = <&cpg 716>; 2653 status = "disabled"; 2654 2655 ports { 2656 #address-cells = <1>; 2657 #size-cells = <0>; 2658 2659 port@1 { 2660 #address-cells = <1>; 2661 #size-cells = <0>; 2662 2663 reg = <1>; 2664 2665 csi40vin0: endpoint@0 { 2666 reg = <0>; 2667 remote-endpoint = <&vin0csi40>; 2668 }; 2669 csi40vin1: endpoint@1 { 2670 reg = <1>; 2671 remote-endpoint = <&vin1csi40>; 2672 }; 2673 csi40vin2: endpoint@2 { 2674 reg = <2>; 2675 remote-endpoint = <&vin2csi40>; 2676 }; 2677 csi40vin3: endpoint@3 { 2678 reg = <3>; 2679 remote-endpoint = <&vin3csi40>; 2680 }; 2681 }; 2682 }; 2683 }; 2684 2685 hdmi0: hdmi@fead0000 { 2686 compatible = "renesas,r8a774e1-hdmi", 2687 "renesas,rcar-gen3-hdmi"; 2688 reg = <0 0xfead0000 0 0x10000>; 2689 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 2690 clocks = <&cpg CPG_MOD 729>, 2691 <&cpg CPG_CORE R8A774E1_CLK_HDMI>; 2692 clock-names = "iahb", "isfr"; 2693 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2694 resets = <&cpg 729>; 2695 status = "disabled"; 2696 2697 ports { 2698 #address-cells = <1>; 2699 #size-cells = <0>; 2700 2701 port@0 { 2702 reg = <0>; 2703 dw_hdmi0_in: endpoint { 2704 remote-endpoint = <&du_out_hdmi0>; 2705 }; 2706 }; 2707 port@1 { 2708 reg = <1>; 2709 }; 2710 port@2 { 2711 /* HDMI sound */ 2712 reg = <2>; 2713 }; 2714 }; 2715 }; 2716 2717 du: display@feb00000 { 2718 compatible = "renesas,du-r8a774e1"; 2719 reg = <0 0xfeb00000 0 0x80000>; 2720 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2721 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2722 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; 2723 clocks = <&cpg CPG_MOD 724>, 2724 <&cpg CPG_MOD 723>, 2725 <&cpg CPG_MOD 721>; 2726 clock-names = "du.0", "du.1", "du.3"; 2727 resets = <&cpg 724>, <&cpg 722>; 2728 reset-names = "du.0", "du.3"; 2729 status = "disabled"; 2730 2731 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; 2732 2733 ports { 2734 #address-cells = <1>; 2735 #size-cells = <0>; 2736 2737 port@0 { 2738 reg = <0>; 2739 du_out_rgb: endpoint { 2740 }; 2741 }; 2742 port@1 { 2743 reg = <1>; 2744 du_out_hdmi0: endpoint { 2745 remote-endpoint = <&dw_hdmi0_in>; 2746 }; 2747 }; 2748 port@2 { 2749 reg = <2>; 2750 du_out_lvds0: endpoint { 2751 remote-endpoint = <&lvds0_in>; 2752 }; 2753 }; 2754 }; 2755 }; 2756 2757 lvds0: lvds@feb90000 { 2758 compatible = "renesas,r8a774e1-lvds"; 2759 reg = <0 0xfeb90000 0 0x14>; 2760 clocks = <&cpg CPG_MOD 727>; 2761 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2762 resets = <&cpg 727>; 2763 status = "disabled"; 2764 2765 ports { 2766 #address-cells = <1>; 2767 #size-cells = <0>; 2768 2769 port@0 { 2770 reg = <0>; 2771 lvds0_in: endpoint { 2772 remote-endpoint = <&du_out_lvds0>; 2773 }; 2774 }; 2775 port@1 { 2776 reg = <1>; 2777 lvds0_out: endpoint { 2778 }; 2779 }; 2780 }; 2781 }; 2782 2783 prr: chipid@fff00044 { 2784 compatible = "renesas,prr"; 2785 reg = <0 0xfff00044 0 4>; 2786 }; 2787 }; 2788 2789 thermal-zones { 2790 sensor_thermal1: sensor-thermal1 { 2791 polling-delay-passive = <250>; 2792 polling-delay = <1000>; 2793 thermal-sensors = <&tsc 0>; 2794 sustainable-power = <6313>; 2795 2796 trips { 2797 sensor1_crit: sensor1-crit { 2798 temperature = <120000>; 2799 hysteresis = <1000>; 2800 type = "critical"; 2801 }; 2802 }; 2803 }; 2804 2805 sensor_thermal2: sensor-thermal2 { 2806 polling-delay-passive = <250>; 2807 polling-delay = <1000>; 2808 thermal-sensors = <&tsc 1>; 2809 sustainable-power = <6313>; 2810 2811 trips { 2812 sensor2_crit: sensor2-crit { 2813 temperature = <120000>; 2814 hysteresis = <1000>; 2815 type = "critical"; 2816 }; 2817 }; 2818 }; 2819 2820 sensor_thermal3: sensor-thermal3 { 2821 polling-delay-passive = <250>; 2822 polling-delay = <1000>; 2823 thermal-sensors = <&tsc 2>; 2824 sustainable-power = <6313>; 2825 2826 trips { 2827 target: trip-point1 { 2828 temperature = <100000>; 2829 hysteresis = <1000>; 2830 type = "passive"; 2831 }; 2832 2833 sensor3_crit: sensor3-crit { 2834 temperature = <120000>; 2835 hysteresis = <1000>; 2836 type = "critical"; 2837 }; 2838 }; 2839 2840 cooling-maps { 2841 map0 { 2842 trip = <&target>; 2843 cooling-device = <&a57_0 0 2>; 2844 contribution = <1024>; 2845 }; 2846 2847 map1 { 2848 trip = <&target>; 2849 cooling-device = <&a53_0 0 2>; 2850 contribution = <1024>; 2851 }; 2852 }; 2853 }; 2854 }; 2855 2856 timer { 2857 compatible = "arm,armv8-timer"; 2858 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2859 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2860 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2861 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2862 }; 2863 2864 /* External USB clocks - can be overridden by the board */ 2865 usb3s0_clk: usb3s0 { 2866 compatible = "fixed-clock"; 2867 #clock-cells = <0>; 2868 clock-frequency = <0>; 2869 }; 2870 2871 usb_extal_clk: usb_extal { 2872 compatible = "fixed-clock"; 2873 #clock-cells = <0>; 2874 clock-frequency = <0>; 2875 }; 2876}; 2877