1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774e1 SoC 4 * 5 * Copyright (C) 2020 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r8a774e1-cpg-mssr.h> 11#include <dt-bindings/power/r8a774e1-sysc.h> 12 13#define CPG_AUDIO_CLK_I R8A774E1_CLK_S0D4 14 15/ { 16 compatible = "renesas,r8a774e1"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 /* 21 * The external audio clocks are configured as 0 Hz fixed frequency 22 * clocks by default. 23 * Boards that provide audio clocks should override them. 24 */ 25 audio_clk_a: audio_clk_a { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <0>; 29 }; 30 31 audio_clk_c: audio_clk_c { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 cpus { 38 #address-cells = <1>; 39 #size-cells = <0>; 40 41 cpu-map { 42 cluster0 { 43 core0 { 44 cpu = <&a57_0>; 45 }; 46 core1 { 47 cpu = <&a57_1>; 48 }; 49 core2 { 50 cpu = <&a57_2>; 51 }; 52 core3 { 53 cpu = <&a57_3>; 54 }; 55 }; 56 57 cluster1 { 58 core0 { 59 cpu = <&a53_0>; 60 }; 61 core1 { 62 cpu = <&a53_1>; 63 }; 64 core2 { 65 cpu = <&a53_2>; 66 }; 67 core3 { 68 cpu = <&a53_3>; 69 }; 70 }; 71 }; 72 73 a57_0: cpu@0 { 74 compatible = "arm,cortex-a57"; 75 reg = <0x0>; 76 device_type = "cpu"; 77 power-domains = <&sysc R8A774E1_PD_CA57_CPU0>; 78 next-level-cache = <&L2_CA57>; 79 enable-method = "psci"; 80 dynamic-power-coefficient = <854>; 81 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 82 capacity-dmips-mhz = <1024>; 83 #cooling-cells = <2>; 84 }; 85 86 a57_1: cpu@1 { 87 compatible = "arm,cortex-a57"; 88 reg = <0x1>; 89 device_type = "cpu"; 90 power-domains = <&sysc R8A774E1_PD_CA57_CPU1>; 91 next-level-cache = <&L2_CA57>; 92 enable-method = "psci"; 93 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 94 capacity-dmips-mhz = <1024>; 95 #cooling-cells = <2>; 96 }; 97 98 a57_2: cpu@2 { 99 compatible = "arm,cortex-a57"; 100 reg = <0x2>; 101 device_type = "cpu"; 102 power-domains = <&sysc R8A774E1_PD_CA57_CPU2>; 103 next-level-cache = <&L2_CA57>; 104 enable-method = "psci"; 105 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 106 capacity-dmips-mhz = <1024>; 107 #cooling-cells = <2>; 108 }; 109 110 a57_3: cpu@3 { 111 compatible = "arm,cortex-a57"; 112 reg = <0x3>; 113 device_type = "cpu"; 114 power-domains = <&sysc R8A774E1_PD_CA57_CPU3>; 115 next-level-cache = <&L2_CA57>; 116 enable-method = "psci"; 117 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 118 capacity-dmips-mhz = <1024>; 119 #cooling-cells = <2>; 120 }; 121 122 a53_0: cpu@100 { 123 compatible = "arm,cortex-a53"; 124 reg = <0x100>; 125 device_type = "cpu"; 126 power-domains = <&sysc R8A774E1_PD_CA53_CPU0>; 127 next-level-cache = <&L2_CA53>; 128 enable-method = "psci"; 129 #cooling-cells = <2>; 130 dynamic-power-coefficient = <277>; 131 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 132 capacity-dmips-mhz = <535>; 133 }; 134 135 a53_1: cpu@101 { 136 compatible = "arm,cortex-a53"; 137 reg = <0x101>; 138 device_type = "cpu"; 139 power-domains = <&sysc R8A774E1_PD_CA53_CPU1>; 140 next-level-cache = <&L2_CA53>; 141 enable-method = "psci"; 142 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 143 capacity-dmips-mhz = <535>; 144 }; 145 146 a53_2: cpu@102 { 147 compatible = "arm,cortex-a53"; 148 reg = <0x102>; 149 device_type = "cpu"; 150 power-domains = <&sysc R8A774E1_PD_CA53_CPU2>; 151 next-level-cache = <&L2_CA53>; 152 enable-method = "psci"; 153 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 154 capacity-dmips-mhz = <535>; 155 }; 156 157 a53_3: cpu@103 { 158 compatible = "arm,cortex-a53"; 159 reg = <0x103>; 160 device_type = "cpu"; 161 power-domains = <&sysc R8A774E1_PD_CA53_CPU3>; 162 next-level-cache = <&L2_CA53>; 163 enable-method = "psci"; 164 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 165 capacity-dmips-mhz = <535>; 166 }; 167 168 L2_CA57: cache-controller-0 { 169 compatible = "cache"; 170 power-domains = <&sysc R8A774E1_PD_CA57_SCU>; 171 cache-unified; 172 cache-level = <2>; 173 }; 174 175 L2_CA53: cache-controller-1 { 176 compatible = "cache"; 177 power-domains = <&sysc R8A774E1_PD_CA53_SCU>; 178 cache-unified; 179 cache-level = <2>; 180 }; 181 }; 182 183 extal_clk: extal { 184 compatible = "fixed-clock"; 185 #clock-cells = <0>; 186 /* This value must be overridden by the board */ 187 clock-frequency = <0>; 188 }; 189 190 extalr_clk: extalr { 191 compatible = "fixed-clock"; 192 #clock-cells = <0>; 193 /* This value must be overridden by the board */ 194 clock-frequency = <0>; 195 }; 196 197 /* External PCIe clock - can be overridden by the board */ 198 pcie_bus_clk: pcie_bus { 199 compatible = "fixed-clock"; 200 #clock-cells = <0>; 201 clock-frequency = <0>; 202 }; 203 204 pmu_a53 { 205 compatible = "arm,cortex-a53-pmu"; 206 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 207 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 208 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 209 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 210 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 211 }; 212 213 pmu_a57 { 214 compatible = "arm,cortex-a57-pmu"; 215 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 216 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 217 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 218 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 219 interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>; 220 }; 221 222 psci { 223 compatible = "arm,psci-1.0", "arm,psci-0.2"; 224 method = "smc"; 225 }; 226 227 /* External SCIF clock - to be overridden by boards that provide it */ 228 scif_clk: scif { 229 compatible = "fixed-clock"; 230 #clock-cells = <0>; 231 clock-frequency = <0>; 232 }; 233 234 soc { 235 compatible = "simple-bus"; 236 interrupt-parent = <&gic>; 237 #address-cells = <2>; 238 #size-cells = <2>; 239 ranges; 240 241 rwdt: watchdog@e6020000 { 242 reg = <0 0xe6020000 0 0x0c>; 243 status = "disabled"; 244 245 /* placeholder */ 246 }; 247 248 gpio0: gpio@e6050000 { 249 reg = <0 0xe6050000 0 0x50>; 250 #gpio-cells = <2>; 251 gpio-controller; 252 #interrupt-cells = <2>; 253 interrupt-controller; 254 255 /* placeholder */ 256 }; 257 258 gpio1: gpio@e6051000 { 259 reg = <0 0xe6051000 0 0x50>; 260 #gpio-cells = <2>; 261 gpio-controller; 262 #interrupt-cells = <2>; 263 interrupt-controller; 264 265 /* placeholder */ 266 }; 267 268 gpio2: gpio@e6052000 { 269 reg = <0 0xe6052000 0 0x50>; 270 #gpio-cells = <2>; 271 gpio-controller; 272 #interrupt-cells = <2>; 273 interrupt-controller; 274 275 /* placeholder */ 276 }; 277 278 gpio3: gpio@e6053000 { 279 /* placeholder */ 280 reg = <0 0xe6053000 0 0x50>; 281 #gpio-cells = <2>; 282 gpio-controller; 283 #interrupt-cells = <2>; 284 interrupt-controller; 285 286 /* placeholder */ 287 }; 288 289 gpio4: gpio@e6054000 { 290 reg = <0 0xe6054000 0 0x50>; 291 #gpio-cells = <2>; 292 gpio-controller; 293 #interrupt-cells = <2>; 294 interrupt-controller; 295 296 /* placeholder */ 297 }; 298 299 gpio5: gpio@e6055000 { 300 reg = <0 0xe6055000 0 0x50>; 301 #gpio-cells = <2>; 302 gpio-controller; 303 #interrupt-cells = <2>; 304 interrupt-controller; 305 306 /* placeholder */ 307 }; 308 309 gpio6: gpio@e6055400 { 310 reg = <0 0xe6055400 0 0x50>; 311 #gpio-cells = <2>; 312 gpio-controller; 313 #interrupt-cells = <2>; 314 interrupt-controller; 315 316 /* placeholder */ 317 }; 318 319 gpio7: gpio@e6055800 { 320 reg = <0 0xe6055800 0 0x50>; 321 #gpio-cells = <2>; 322 gpio-controller; 323 #interrupt-cells = <2>; 324 interrupt-controller; 325 326 /* placeholder */ 327 }; 328 329 pfc: pin-controller@e6060000 { 330 compatible = "renesas,pfc-r8a774e1"; 331 reg = <0 0xe6060000 0 0x50c>; 332 }; 333 334 cpg: clock-controller@e6150000 { 335 compatible = "renesas,r8a774e1-cpg-mssr"; 336 reg = <0 0xe6150000 0 0x1000>; 337 clocks = <&extal_clk>, <&extalr_clk>; 338 clock-names = "extal", "extalr"; 339 #clock-cells = <2>; 340 #power-domain-cells = <0>; 341 #reset-cells = <1>; 342 }; 343 344 rst: reset-controller@e6160000 { 345 compatible = "renesas,r8a774e1-rst"; 346 reg = <0 0xe6160000 0 0x0200>; 347 }; 348 349 sysc: system-controller@e6180000 { 350 compatible = "renesas,r8a774e1-sysc"; 351 reg = <0 0xe6180000 0 0x0400>; 352 #power-domain-cells = <1>; 353 }; 354 355 intc_ex: interrupt-controller@e61c0000 { 356 compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc"; 357 #interrupt-cells = <2>; 358 interrupt-controller; 359 reg = <0 0xe61c0000 0 0x200>; 360 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&cpg CPG_MOD 407>; 367 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 368 resets = <&cpg 407>; 369 }; 370 371 i2c2: i2c@e6510000 { 372 reg = <0 0xe6510000 0 0x40>; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 status = "disabled"; 376 377 /* placeholder */ 378 }; 379 380 i2c4: i2c@e66d8000 { 381 #address-cells = <1>; 382 #size-cells = <0>; 383 reg = <0 0xe66d8000 0 0x40>; 384 status = "disabled"; 385 386 /* placeholder */ 387 }; 388 389 hscif0: serial@e6540000 { 390 reg = <0 0xe6540000 0 0x60>; 391 status = "disabled"; 392 393 /* placeholder */ 394 }; 395 396 hsusb: usb@e6590000 { 397 reg = <0 0xe6590000 0 0x200>; 398 status = "disabled"; 399 400 /* placeholder */ 401 }; 402 403 usb3_phy0: usb-phy@e65ee000 { 404 reg = <0 0xe65ee000 0 0x90>; 405 #phy-cells = <0>; 406 status = "disabled"; 407 408 /* placeholder */ 409 }; 410 411 dmac0: dma-controller@e6700000 { 412 compatible = "renesas,dmac-r8a774e1", 413 "renesas,rcar-dmac"; 414 reg = <0 0xe6700000 0 0x10000>; 415 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 432 interrupt-names = "error", 433 "ch0", "ch1", "ch2", "ch3", 434 "ch4", "ch5", "ch6", "ch7", 435 "ch8", "ch9", "ch10", "ch11", 436 "ch12", "ch13", "ch14", "ch15"; 437 clocks = <&cpg CPG_MOD 219>; 438 clock-names = "fck"; 439 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 440 resets = <&cpg 219>; 441 #dma-cells = <1>; 442 dma-channels = <16>; 443 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 444 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 445 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 446 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 447 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 448 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 449 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 450 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 451 }; 452 453 dmac1: dma-controller@e7300000 { 454 compatible = "renesas,dmac-r8a774e1", 455 "renesas,rcar-dmac"; 456 reg = <0 0xe7300000 0 0x10000>; 457 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 474 interrupt-names = "error", 475 "ch0", "ch1", "ch2", "ch3", 476 "ch4", "ch5", "ch6", "ch7", 477 "ch8", "ch9", "ch10", "ch11", 478 "ch12", "ch13", "ch14", "ch15"; 479 clocks = <&cpg CPG_MOD 218>; 480 clock-names = "fck"; 481 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 482 resets = <&cpg 218>; 483 #dma-cells = <1>; 484 dma-channels = <16>; 485 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 486 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 487 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 488 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 489 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 490 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 491 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 492 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 493 }; 494 495 dmac2: dma-controller@e7310000 { 496 compatible = "renesas,dmac-r8a774e1", 497 "renesas,rcar-dmac"; 498 reg = <0 0xe7310000 0 0x10000>; 499 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 516 interrupt-names = "error", 517 "ch0", "ch1", "ch2", "ch3", 518 "ch4", "ch5", "ch6", "ch7", 519 "ch8", "ch9", "ch10", "ch11", 520 "ch12", "ch13", "ch14", "ch15"; 521 clocks = <&cpg CPG_MOD 217>; 522 clock-names = "fck"; 523 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 524 resets = <&cpg 217>; 525 #dma-cells = <1>; 526 dma-channels = <16>; 527 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 528 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 529 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 530 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 531 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 532 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 533 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 534 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 535 }; 536 537 ipmmu_ds0: iommu@e6740000 { 538 compatible = "renesas,ipmmu-r8a774e1"; 539 reg = <0 0xe6740000 0 0x1000>; 540 renesas,ipmmu-main = <&ipmmu_mm 0>; 541 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 542 #iommu-cells = <1>; 543 }; 544 545 ipmmu_ds1: iommu@e7740000 { 546 compatible = "renesas,ipmmu-r8a774e1"; 547 reg = <0 0xe7740000 0 0x1000>; 548 renesas,ipmmu-main = <&ipmmu_mm 1>; 549 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 550 #iommu-cells = <1>; 551 }; 552 553 ipmmu_hc: iommu@e6570000 { 554 compatible = "renesas,ipmmu-r8a774e1"; 555 reg = <0 0xe6570000 0 0x1000>; 556 renesas,ipmmu-main = <&ipmmu_mm 2>; 557 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 558 #iommu-cells = <1>; 559 }; 560 561 ipmmu_mm: iommu@e67b0000 { 562 compatible = "renesas,ipmmu-r8a774e1"; 563 reg = <0 0xe67b0000 0 0x1000>; 564 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 566 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 567 #iommu-cells = <1>; 568 }; 569 570 ipmmu_mp0: iommu@ec670000 { 571 compatible = "renesas,ipmmu-r8a774e1"; 572 reg = <0 0xec670000 0 0x1000>; 573 renesas,ipmmu-main = <&ipmmu_mm 4>; 574 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 575 #iommu-cells = <1>; 576 }; 577 578 ipmmu_pv0: iommu@fd800000 { 579 compatible = "renesas,ipmmu-r8a774e1"; 580 reg = <0 0xfd800000 0 0x1000>; 581 renesas,ipmmu-main = <&ipmmu_mm 6>; 582 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 583 #iommu-cells = <1>; 584 }; 585 586 ipmmu_pv1: iommu@fd950000 { 587 compatible = "renesas,ipmmu-r8a774e1"; 588 reg = <0 0xfd950000 0 0x1000>; 589 renesas,ipmmu-main = <&ipmmu_mm 7>; 590 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 591 #iommu-cells = <1>; 592 }; 593 594 ipmmu_pv2: iommu@fd960000 { 595 compatible = "renesas,ipmmu-r8a774e1"; 596 reg = <0 0xfd960000 0 0x1000>; 597 renesas,ipmmu-main = <&ipmmu_mm 8>; 598 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 599 #iommu-cells = <1>; 600 }; 601 602 ipmmu_pv3: iommu@fd970000 { 603 compatible = "renesas,ipmmu-r8a774e1"; 604 reg = <0 0xfd970000 0 0x1000>; 605 renesas,ipmmu-main = <&ipmmu_mm 9>; 606 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 607 #iommu-cells = <1>; 608 }; 609 610 ipmmu_vc0: iommu@fe6b0000 { 611 compatible = "renesas,ipmmu-r8a774e1"; 612 reg = <0 0xfe6b0000 0 0x1000>; 613 renesas,ipmmu-main = <&ipmmu_mm 12>; 614 power-domains = <&sysc R8A774E1_PD_A3VC>; 615 #iommu-cells = <1>; 616 }; 617 618 ipmmu_vc1: iommu@fe6f0000 { 619 compatible = "renesas,ipmmu-r8a774e1"; 620 reg = <0 0xfe6f0000 0 0x1000>; 621 renesas,ipmmu-main = <&ipmmu_mm 13>; 622 power-domains = <&sysc R8A774E1_PD_A3VC>; 623 #iommu-cells = <1>; 624 }; 625 626 ipmmu_vi0: iommu@febd0000 { 627 compatible = "renesas,ipmmu-r8a774e1"; 628 reg = <0 0xfebd0000 0 0x1000>; 629 renesas,ipmmu-main = <&ipmmu_mm 14>; 630 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 631 #iommu-cells = <1>; 632 }; 633 634 ipmmu_vi1: iommu@febe0000 { 635 compatible = "renesas,ipmmu-r8a774e1"; 636 reg = <0 0xfebe0000 0 0x1000>; 637 renesas,ipmmu-main = <&ipmmu_mm 15>; 638 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 639 #iommu-cells = <1>; 640 }; 641 642 ipmmu_vp0: iommu@fe990000 { 643 compatible = "renesas,ipmmu-r8a774e1"; 644 reg = <0 0xfe990000 0 0x1000>; 645 renesas,ipmmu-main = <&ipmmu_mm 16>; 646 power-domains = <&sysc R8A774E1_PD_A3VP>; 647 #iommu-cells = <1>; 648 }; 649 650 ipmmu_vp1: iommu@fe980000 { 651 compatible = "renesas,ipmmu-r8a774e1"; 652 reg = <0 0xfe980000 0 0x1000>; 653 renesas,ipmmu-main = <&ipmmu_mm 17>; 654 power-domains = <&sysc R8A774E1_PD_A3VP>; 655 #iommu-cells = <1>; 656 }; 657 658 avb: ethernet@e6800000 { 659 reg = <0 0xe6800000 0 0x800>; 660 #address-cells = <1>; 661 #size-cells = <0>; 662 status = "disabled"; 663 664 /* placeholder */ 665 }; 666 667 can0: can@e6c30000 { 668 reg = <0 0xe6c30000 0 0x1000>; 669 status = "disabled"; 670 671 /* placeholder */ 672 }; 673 674 can1: can@e6c38000 { 675 reg = <0 0xe6c38000 0 0x1000>; 676 status = "disabled"; 677 678 /* placeholder */ 679 }; 680 681 pwm0: pwm@e6e30000 { 682 reg = <0 0xe6e30000 0 0x8>; 683 #pwm-cells = <2>; 684 status = "disabled"; 685 686 /* placeholder */ 687 }; 688 689 scif2: serial@e6e88000 { 690 compatible = "renesas,scif-r8a774e1", 691 "renesas,rcar-gen3-scif", "renesas,scif"; 692 reg = <0 0xe6e88000 0 0x40>; 693 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 694 clocks = <&cpg CPG_MOD 310>, 695 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 696 <&scif_clk>; 697 clock-names = "fck", "brg_int", "scif_clk"; 698 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 699 resets = <&cpg 310>; 700 status = "disabled"; 701 }; 702 703 rcar_sound: sound@ec500000 { 704 reg = <0 0xec500000 0 0x1000>, /* SCU */ 705 <0 0xec5a0000 0 0x100>, /* ADG */ 706 <0 0xec540000 0 0x1000>, /* SSIU */ 707 <0 0xec541000 0 0x280>, /* SSI */ 708 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 709 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 710 711 status = "disabled"; 712 713 /* placeholder */ 714 715 rcar_sound,ssi { 716 ssi2: ssi-2 { 717 /* placeholder */ 718 }; 719 }; 720 }; 721 722 xhci0: usb@ee000000 { 723 reg = <0 0xee000000 0 0xc00>; 724 status = "disabled"; 725 726 /* placeholder */ 727 }; 728 729 usb3_peri0: usb@ee020000 { 730 reg = <0 0xee020000 0 0x400>; 731 status = "disabled"; 732 733 /* placeholder */ 734 }; 735 736 ohci0: usb@ee080000 { 737 reg = <0 0xee080000 0 0x100>; 738 status = "disabled"; 739 740 /* placeholder */ 741 }; 742 743 ohci1: usb@ee0a0000 { 744 reg = <0 0xee0a0000 0 0x100>; 745 status = "disabled"; 746 747 /* placeholder */ 748 }; 749 750 ehci0: usb@ee080100 { 751 reg = <0 0xee080100 0 0x100>; 752 status = "disabled"; 753 754 /* placeholder */ 755 }; 756 757 ehci1: usb@ee0a0100 { 758 reg = <0 0xee0a0100 0 0x100>; 759 status = "disabled"; 760 761 /* placeholder */ 762 }; 763 764 usb2_phy0: usb-phy@ee080200 { 765 reg = <0 0xee080200 0 0x700>; 766 status = "disabled"; 767 768 /* placeholder */ 769 }; 770 771 usb2_phy1: usb-phy@ee0a0200 { 772 reg = <0 0xee0a0200 0 0x700>; 773 status = "disabled"; 774 775 /* placeholder */ 776 }; 777 778 sdhi0: mmc@ee100000 { 779 reg = <0 0xee100000 0 0x2000>; 780 status = "disabled"; 781 782 /* placeholder */ 783 }; 784 785 sdhi2: mmc@ee140000 { 786 reg = <0 0xee140000 0 0x2000>; 787 status = "disabled"; 788 789 /* placeholder */ 790 }; 791 792 sdhi3: mmc@ee160000 { 793 compatible = "renesas,sdhi-r8a774e1", 794 "renesas,rcar-gen3-sdhi"; 795 reg = <0 0xee160000 0 0x2000>; 796 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 797 clocks = <&cpg CPG_MOD 311>; 798 max-frequency = <200000000>; 799 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 800 resets = <&cpg 311>; 801 status = "disabled"; 802 }; 803 804 gic: interrupt-controller@f1010000 { 805 compatible = "arm,gic-400"; 806 #interrupt-cells = <3>; 807 #address-cells = <0>; 808 interrupt-controller; 809 reg = <0x0 0xf1010000 0 0x1000>, 810 <0x0 0xf1020000 0 0x20000>, 811 <0x0 0xf1040000 0 0x20000>, 812 <0x0 0xf1060000 0 0x20000>; 813 interrupts = <GIC_PPI 9 814 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 815 clocks = <&cpg CPG_MOD 408>; 816 clock-names = "clk"; 817 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 818 resets = <&cpg 408>; 819 }; 820 821 pciec0: pcie@fe000000 { 822 reg = <0 0xfe000000 0 0x80000>; 823 #address-cells = <3>; 824 #size-cells = <2>; 825 status = "disabled"; 826 827 /* placeholder */ 828 }; 829 830 hdmi0: hdmi@fead0000 { 831 reg = <0 0xfead0000 0 0x10000>; 832 status = "disabled"; 833 834 /* placeholder */ 835 836 ports { 837 #address-cells = <1>; 838 #size-cells = <0>; 839 840 port@0 { 841 reg = <0>; 842 }; 843 port@1 { 844 reg = <1>; 845 }; 846 port@2 { 847 reg = <2>; 848 }; 849 }; 850 }; 851 852 du: display@feb00000 { 853 reg = <0 0xfeb00000 0 0x80000>; 854 status = "disabled"; 855 856 /* placeholder */ 857 ports { 858 #address-cells = <1>; 859 #size-cells = <0>; 860 861 port@0 { 862 reg = <0>; 863 }; 864 port@1 { 865 reg = <1>; 866 }; 867 port@2 { 868 reg = <2>; 869 }; 870 }; 871 }; 872 873 prr: chipid@fff00044 { 874 compatible = "renesas,prr"; 875 reg = <0 0xfff00044 0 4>; 876 }; 877 }; 878 879 timer { 880 compatible = "arm,armv8-timer"; 881 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 882 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 883 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 884 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 885 }; 886 887 /* External USB clocks - can be overridden by the board */ 888 usb3s0_clk: usb3s0 { 889 compatible = "fixed-clock"; 890 #clock-cells = <0>; 891 clock-frequency = <0>; 892 }; 893 894 usb_extal_clk: usb_extal { 895 compatible = "fixed-clock"; 896 #clock-cells = <0>; 897 clock-frequency = <0>; 898 }; 899}; 900