1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774e1 SoC 4 * 5 * Copyright (C) 2020 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r8a774e1-cpg-mssr.h> 11#include <dt-bindings/power/r8a774e1-sysc.h> 12 13#define CPG_AUDIO_CLK_I R8A774E1_CLK_S0D4 14 15/ { 16 compatible = "renesas,r8a774e1"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 /* 21 * The external audio clocks are configured as 0 Hz fixed frequency 22 * clocks by default. 23 * Boards that provide audio clocks should override them. 24 */ 25 audio_clk_a: audio_clk_a { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <0>; 29 }; 30 31 audio_clk_c: audio_clk_c { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 /* External CAN clock - to be overridden by boards that provide it */ 38 can_clk: can { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <0>; 42 }; 43 44 cluster0_opp: opp_table0 { 45 compatible = "operating-points-v2"; 46 opp-shared; 47 48 opp-500000000 { 49 opp-hz = /bits/ 64 <500000000>; 50 opp-microvolt = <820000>; 51 clock-latency-ns = <300000>; 52 }; 53 opp-1000000000 { 54 opp-hz = /bits/ 64 <1000000000>; 55 opp-microvolt = <820000>; 56 clock-latency-ns = <300000>; 57 }; 58 opp-1500000000 { 59 opp-hz = /bits/ 64 <1500000000>; 60 opp-microvolt = <820000>; 61 clock-latency-ns = <300000>; 62 opp-suspend; 63 }; 64 }; 65 66 cluster1_opp: opp_table1 { 67 compatible = "operating-points-v2"; 68 opp-shared; 69 70 opp-800000000 { 71 opp-hz = /bits/ 64 <800000000>; 72 opp-microvolt = <820000>; 73 clock-latency-ns = <300000>; 74 }; 75 opp-1000000000 { 76 opp-hz = /bits/ 64 <1000000000>; 77 opp-microvolt = <820000>; 78 clock-latency-ns = <300000>; 79 }; 80 opp-1200000000 { 81 opp-hz = /bits/ 64 <1200000000>; 82 opp-microvolt = <820000>; 83 clock-latency-ns = <300000>; 84 }; 85 }; 86 87 cpus { 88 #address-cells = <1>; 89 #size-cells = <0>; 90 91 cpu-map { 92 cluster0 { 93 core0 { 94 cpu = <&a57_0>; 95 }; 96 core1 { 97 cpu = <&a57_1>; 98 }; 99 core2 { 100 cpu = <&a57_2>; 101 }; 102 core3 { 103 cpu = <&a57_3>; 104 }; 105 }; 106 107 cluster1 { 108 core0 { 109 cpu = <&a53_0>; 110 }; 111 core1 { 112 cpu = <&a53_1>; 113 }; 114 core2 { 115 cpu = <&a53_2>; 116 }; 117 core3 { 118 cpu = <&a53_3>; 119 }; 120 }; 121 }; 122 123 a57_0: cpu@0 { 124 compatible = "arm,cortex-a57"; 125 reg = <0x0>; 126 device_type = "cpu"; 127 power-domains = <&sysc R8A774E1_PD_CA57_CPU0>; 128 next-level-cache = <&L2_CA57>; 129 enable-method = "psci"; 130 dynamic-power-coefficient = <854>; 131 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 132 operating-points-v2 = <&cluster0_opp>; 133 capacity-dmips-mhz = <1024>; 134 #cooling-cells = <2>; 135 }; 136 137 a57_1: cpu@1 { 138 compatible = "arm,cortex-a57"; 139 reg = <0x1>; 140 device_type = "cpu"; 141 power-domains = <&sysc R8A774E1_PD_CA57_CPU1>; 142 next-level-cache = <&L2_CA57>; 143 enable-method = "psci"; 144 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 145 operating-points-v2 = <&cluster0_opp>; 146 capacity-dmips-mhz = <1024>; 147 #cooling-cells = <2>; 148 }; 149 150 a57_2: cpu@2 { 151 compatible = "arm,cortex-a57"; 152 reg = <0x2>; 153 device_type = "cpu"; 154 power-domains = <&sysc R8A774E1_PD_CA57_CPU2>; 155 next-level-cache = <&L2_CA57>; 156 enable-method = "psci"; 157 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 158 operating-points-v2 = <&cluster0_opp>; 159 capacity-dmips-mhz = <1024>; 160 #cooling-cells = <2>; 161 }; 162 163 a57_3: cpu@3 { 164 compatible = "arm,cortex-a57"; 165 reg = <0x3>; 166 device_type = "cpu"; 167 power-domains = <&sysc R8A774E1_PD_CA57_CPU3>; 168 next-level-cache = <&L2_CA57>; 169 enable-method = "psci"; 170 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 171 operating-points-v2 = <&cluster0_opp>; 172 capacity-dmips-mhz = <1024>; 173 #cooling-cells = <2>; 174 }; 175 176 a53_0: cpu@100 { 177 compatible = "arm,cortex-a53"; 178 reg = <0x100>; 179 device_type = "cpu"; 180 power-domains = <&sysc R8A774E1_PD_CA53_CPU0>; 181 next-level-cache = <&L2_CA53>; 182 enable-method = "psci"; 183 #cooling-cells = <2>; 184 dynamic-power-coefficient = <277>; 185 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 186 operating-points-v2 = <&cluster1_opp>; 187 capacity-dmips-mhz = <535>; 188 }; 189 190 a53_1: cpu@101 { 191 compatible = "arm,cortex-a53"; 192 reg = <0x101>; 193 device_type = "cpu"; 194 power-domains = <&sysc R8A774E1_PD_CA53_CPU1>; 195 next-level-cache = <&L2_CA53>; 196 enable-method = "psci"; 197 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 198 operating-points-v2 = <&cluster1_opp>; 199 capacity-dmips-mhz = <535>; 200 }; 201 202 a53_2: cpu@102 { 203 compatible = "arm,cortex-a53"; 204 reg = <0x102>; 205 device_type = "cpu"; 206 power-domains = <&sysc R8A774E1_PD_CA53_CPU2>; 207 next-level-cache = <&L2_CA53>; 208 enable-method = "psci"; 209 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 210 operating-points-v2 = <&cluster1_opp>; 211 capacity-dmips-mhz = <535>; 212 }; 213 214 a53_3: cpu@103 { 215 compatible = "arm,cortex-a53"; 216 reg = <0x103>; 217 device_type = "cpu"; 218 power-domains = <&sysc R8A774E1_PD_CA53_CPU3>; 219 next-level-cache = <&L2_CA53>; 220 enable-method = "psci"; 221 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 222 operating-points-v2 = <&cluster1_opp>; 223 capacity-dmips-mhz = <535>; 224 }; 225 226 L2_CA57: cache-controller-0 { 227 compatible = "cache"; 228 power-domains = <&sysc R8A774E1_PD_CA57_SCU>; 229 cache-unified; 230 cache-level = <2>; 231 }; 232 233 L2_CA53: cache-controller-1 { 234 compatible = "cache"; 235 power-domains = <&sysc R8A774E1_PD_CA53_SCU>; 236 cache-unified; 237 cache-level = <2>; 238 }; 239 }; 240 241 extal_clk: extal { 242 compatible = "fixed-clock"; 243 #clock-cells = <0>; 244 /* This value must be overridden by the board */ 245 clock-frequency = <0>; 246 }; 247 248 extalr_clk: extalr { 249 compatible = "fixed-clock"; 250 #clock-cells = <0>; 251 /* This value must be overridden by the board */ 252 clock-frequency = <0>; 253 }; 254 255 /* External PCIe clock - can be overridden by the board */ 256 pcie_bus_clk: pcie_bus { 257 compatible = "fixed-clock"; 258 #clock-cells = <0>; 259 clock-frequency = <0>; 260 }; 261 262 pmu_a53 { 263 compatible = "arm,cortex-a53-pmu"; 264 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 265 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 266 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 267 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 268 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 269 }; 270 271 pmu_a57 { 272 compatible = "arm,cortex-a57-pmu"; 273 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 274 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 275 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 276 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 277 interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>; 278 }; 279 280 psci { 281 compatible = "arm,psci-1.0", "arm,psci-0.2"; 282 method = "smc"; 283 }; 284 285 /* External SCIF clock - to be overridden by boards that provide it */ 286 scif_clk: scif { 287 compatible = "fixed-clock"; 288 #clock-cells = <0>; 289 clock-frequency = <0>; 290 }; 291 292 soc { 293 compatible = "simple-bus"; 294 interrupt-parent = <&gic>; 295 #address-cells = <2>; 296 #size-cells = <2>; 297 ranges; 298 299 rwdt: watchdog@e6020000 { 300 compatible = "renesas,r8a774e1-wdt", 301 "renesas,rcar-gen3-wdt"; 302 reg = <0 0xe6020000 0 0x0c>; 303 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&cpg CPG_MOD 402>; 305 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 306 resets = <&cpg 402>; 307 status = "disabled"; 308 }; 309 310 gpio0: gpio@e6050000 { 311 compatible = "renesas,gpio-r8a774e1", 312 "renesas,rcar-gen3-gpio"; 313 reg = <0 0xe6050000 0 0x50>; 314 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 315 #gpio-cells = <2>; 316 gpio-controller; 317 gpio-ranges = <&pfc 0 0 16>; 318 #interrupt-cells = <2>; 319 interrupt-controller; 320 clocks = <&cpg CPG_MOD 912>; 321 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 322 resets = <&cpg 912>; 323 }; 324 325 gpio1: gpio@e6051000 { 326 compatible = "renesas,gpio-r8a774e1", 327 "renesas,rcar-gen3-gpio"; 328 reg = <0 0xe6051000 0 0x50>; 329 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 330 #gpio-cells = <2>; 331 gpio-controller; 332 gpio-ranges = <&pfc 0 32 29>; 333 #interrupt-cells = <2>; 334 interrupt-controller; 335 clocks = <&cpg CPG_MOD 911>; 336 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 337 resets = <&cpg 911>; 338 }; 339 340 gpio2: gpio@e6052000 { 341 compatible = "renesas,gpio-r8a774e1", 342 "renesas,rcar-gen3-gpio"; 343 reg = <0 0xe6052000 0 0x50>; 344 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 345 #gpio-cells = <2>; 346 gpio-controller; 347 gpio-ranges = <&pfc 0 64 15>; 348 #interrupt-cells = <2>; 349 interrupt-controller; 350 clocks = <&cpg CPG_MOD 910>; 351 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 352 resets = <&cpg 910>; 353 }; 354 355 gpio3: gpio@e6053000 { 356 compatible = "renesas,gpio-r8a774e1", 357 "renesas,rcar-gen3-gpio"; 358 reg = <0 0xe6053000 0 0x50>; 359 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 360 #gpio-cells = <2>; 361 gpio-controller; 362 gpio-ranges = <&pfc 0 96 16>; 363 #interrupt-cells = <2>; 364 interrupt-controller; 365 clocks = <&cpg CPG_MOD 909>; 366 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 367 resets = <&cpg 909>; 368 }; 369 370 gpio4: gpio@e6054000 { 371 compatible = "renesas,gpio-r8a774e1", 372 "renesas,rcar-gen3-gpio"; 373 reg = <0 0xe6054000 0 0x50>; 374 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 375 #gpio-cells = <2>; 376 gpio-controller; 377 gpio-ranges = <&pfc 0 128 18>; 378 #interrupt-cells = <2>; 379 interrupt-controller; 380 clocks = <&cpg CPG_MOD 908>; 381 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 382 resets = <&cpg 908>; 383 }; 384 385 gpio5: gpio@e6055000 { 386 compatible = "renesas,gpio-r8a774e1", 387 "renesas,rcar-gen3-gpio"; 388 reg = <0 0xe6055000 0 0x50>; 389 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 390 #gpio-cells = <2>; 391 gpio-controller; 392 gpio-ranges = <&pfc 0 160 26>; 393 #interrupt-cells = <2>; 394 interrupt-controller; 395 clocks = <&cpg CPG_MOD 907>; 396 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 397 resets = <&cpg 907>; 398 }; 399 400 gpio6: gpio@e6055400 { 401 compatible = "renesas,gpio-r8a774e1", 402 "renesas,rcar-gen3-gpio"; 403 reg = <0 0xe6055400 0 0x50>; 404 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 405 #gpio-cells = <2>; 406 gpio-controller; 407 gpio-ranges = <&pfc 0 192 32>; 408 #interrupt-cells = <2>; 409 interrupt-controller; 410 clocks = <&cpg CPG_MOD 906>; 411 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 412 resets = <&cpg 906>; 413 }; 414 415 gpio7: gpio@e6055800 { 416 compatible = "renesas,gpio-r8a774e1", 417 "renesas,rcar-gen3-gpio"; 418 reg = <0 0xe6055800 0 0x50>; 419 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 420 #gpio-cells = <2>; 421 gpio-controller; 422 gpio-ranges = <&pfc 0 224 4>; 423 #interrupt-cells = <2>; 424 interrupt-controller; 425 clocks = <&cpg CPG_MOD 905>; 426 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 427 resets = <&cpg 905>; 428 }; 429 430 pfc: pin-controller@e6060000 { 431 compatible = "renesas,pfc-r8a774e1"; 432 reg = <0 0xe6060000 0 0x50c>; 433 }; 434 435 cmt0: timer@e60f0000 { 436 compatible = "renesas,r8a774e1-cmt0", 437 "renesas,rcar-gen3-cmt0"; 438 reg = <0 0xe60f0000 0 0x1004>; 439 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&cpg CPG_MOD 303>; 442 clock-names = "fck"; 443 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 444 resets = <&cpg 303>; 445 status = "disabled"; 446 }; 447 448 cmt1: timer@e6130000 { 449 compatible = "renesas,r8a774e1-cmt1", 450 "renesas,rcar-gen3-cmt1"; 451 reg = <0 0xe6130000 0 0x1004>; 452 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&cpg CPG_MOD 302>; 461 clock-names = "fck"; 462 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 463 resets = <&cpg 302>; 464 status = "disabled"; 465 }; 466 467 cmt2: timer@e6140000 { 468 compatible = "renesas,r8a774e1-cmt1", 469 "renesas,rcar-gen3-cmt1"; 470 reg = <0 0xe6140000 0 0x1004>; 471 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&cpg CPG_MOD 301>; 480 clock-names = "fck"; 481 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 482 resets = <&cpg 301>; 483 status = "disabled"; 484 }; 485 486 cmt3: timer@e6148000 { 487 compatible = "renesas,r8a774e1-cmt1", 488 "renesas,rcar-gen3-cmt1"; 489 reg = <0 0xe6148000 0 0x1004>; 490 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&cpg CPG_MOD 300>; 499 clock-names = "fck"; 500 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 501 resets = <&cpg 300>; 502 status = "disabled"; 503 }; 504 505 cpg: clock-controller@e6150000 { 506 compatible = "renesas,r8a774e1-cpg-mssr"; 507 reg = <0 0xe6150000 0 0x1000>; 508 clocks = <&extal_clk>, <&extalr_clk>; 509 clock-names = "extal", "extalr"; 510 #clock-cells = <2>; 511 #power-domain-cells = <0>; 512 #reset-cells = <1>; 513 }; 514 515 rst: reset-controller@e6160000 { 516 compatible = "renesas,r8a774e1-rst"; 517 reg = <0 0xe6160000 0 0x0200>; 518 }; 519 520 sysc: system-controller@e6180000 { 521 compatible = "renesas,r8a774e1-sysc"; 522 reg = <0 0xe6180000 0 0x0400>; 523 #power-domain-cells = <1>; 524 }; 525 526 tsc: thermal@e6198000 { 527 compatible = "renesas,r8a774e1-thermal"; 528 reg = <0 0xe6198000 0 0x100>, 529 <0 0xe61a0000 0 0x100>, 530 <0 0xe61a8000 0 0x100>; 531 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&cpg CPG_MOD 522>; 535 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 536 resets = <&cpg 522>; 537 #thermal-sensor-cells = <1>; 538 }; 539 540 intc_ex: interrupt-controller@e61c0000 { 541 compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc"; 542 #interrupt-cells = <2>; 543 interrupt-controller; 544 reg = <0 0xe61c0000 0 0x200>; 545 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&cpg CPG_MOD 407>; 552 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 553 resets = <&cpg 407>; 554 }; 555 556 tmu0: timer@e61e0000 { 557 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 558 reg = <0 0xe61e0000 0 0x30>; 559 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&cpg CPG_MOD 125>; 563 clock-names = "fck"; 564 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 565 resets = <&cpg 125>; 566 status = "disabled"; 567 }; 568 569 tmu1: timer@e6fc0000 { 570 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 571 reg = <0 0xe6fc0000 0 0x30>; 572 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&cpg CPG_MOD 124>; 576 clock-names = "fck"; 577 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 578 resets = <&cpg 124>; 579 status = "disabled"; 580 }; 581 582 tmu2: timer@e6fd0000 { 583 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 584 reg = <0 0xe6fd0000 0 0x30>; 585 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&cpg CPG_MOD 123>; 589 clock-names = "fck"; 590 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 591 resets = <&cpg 123>; 592 status = "disabled"; 593 }; 594 595 tmu3: timer@e6fe0000 { 596 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 597 reg = <0 0xe6fe0000 0 0x30>; 598 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&cpg CPG_MOD 122>; 602 clock-names = "fck"; 603 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 604 resets = <&cpg 122>; 605 status = "disabled"; 606 }; 607 608 tmu4: timer@ffc00000 { 609 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 610 reg = <0 0xffc00000 0 0x30>; 611 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 614 clocks = <&cpg CPG_MOD 121>; 615 clock-names = "fck"; 616 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 617 resets = <&cpg 121>; 618 status = "disabled"; 619 }; 620 621 i2c0: i2c@e6500000 { 622 #address-cells = <1>; 623 #size-cells = <0>; 624 compatible = "renesas,i2c-r8a774e1", 625 "renesas,rcar-gen3-i2c"; 626 reg = <0 0xe6500000 0 0x40>; 627 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&cpg CPG_MOD 931>; 629 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 630 resets = <&cpg 931>; 631 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 632 <&dmac2 0x91>, <&dmac2 0x90>; 633 dma-names = "tx", "rx", "tx", "rx"; 634 i2c-scl-internal-delay-ns = <110>; 635 status = "disabled"; 636 }; 637 638 i2c1: i2c@e6508000 { 639 #address-cells = <1>; 640 #size-cells = <0>; 641 compatible = "renesas,i2c-r8a774e1", 642 "renesas,rcar-gen3-i2c"; 643 reg = <0 0xe6508000 0 0x40>; 644 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 645 clocks = <&cpg CPG_MOD 930>; 646 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 647 resets = <&cpg 930>; 648 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 649 <&dmac2 0x93>, <&dmac2 0x92>; 650 dma-names = "tx", "rx", "tx", "rx"; 651 i2c-scl-internal-delay-ns = <6>; 652 status = "disabled"; 653 }; 654 655 i2c2: i2c@e6510000 { 656 #address-cells = <1>; 657 #size-cells = <0>; 658 compatible = "renesas,i2c-r8a774e1", 659 "renesas,rcar-gen3-i2c"; 660 reg = <0 0xe6510000 0 0x40>; 661 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&cpg CPG_MOD 929>; 663 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 664 resets = <&cpg 929>; 665 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 666 <&dmac2 0x95>, <&dmac2 0x94>; 667 dma-names = "tx", "rx", "tx", "rx"; 668 i2c-scl-internal-delay-ns = <6>; 669 status = "disabled"; 670 }; 671 672 i2c3: i2c@e66d0000 { 673 #address-cells = <1>; 674 #size-cells = <0>; 675 compatible = "renesas,i2c-r8a774e1", 676 "renesas,rcar-gen3-i2c"; 677 reg = <0 0xe66d0000 0 0x40>; 678 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 679 clocks = <&cpg CPG_MOD 928>; 680 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 681 resets = <&cpg 928>; 682 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 683 dma-names = "tx", "rx"; 684 i2c-scl-internal-delay-ns = <110>; 685 status = "disabled"; 686 }; 687 688 i2c4: i2c@e66d8000 { 689 #address-cells = <1>; 690 #size-cells = <0>; 691 compatible = "renesas,i2c-r8a774e1", 692 "renesas,rcar-gen3-i2c"; 693 reg = <0 0xe66d8000 0 0x40>; 694 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 695 clocks = <&cpg CPG_MOD 927>; 696 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 697 resets = <&cpg 927>; 698 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 699 dma-names = "tx", "rx"; 700 i2c-scl-internal-delay-ns = <110>; 701 status = "disabled"; 702 }; 703 704 i2c5: i2c@e66e0000 { 705 #address-cells = <1>; 706 #size-cells = <0>; 707 compatible = "renesas,i2c-r8a774e1", 708 "renesas,rcar-gen3-i2c"; 709 reg = <0 0xe66e0000 0 0x40>; 710 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&cpg CPG_MOD 919>; 712 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 713 resets = <&cpg 919>; 714 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 715 dma-names = "tx", "rx"; 716 i2c-scl-internal-delay-ns = <110>; 717 status = "disabled"; 718 }; 719 720 i2c6: i2c@e66e8000 { 721 #address-cells = <1>; 722 #size-cells = <0>; 723 compatible = "renesas,i2c-r8a774e1", 724 "renesas,rcar-gen3-i2c"; 725 reg = <0 0xe66e8000 0 0x40>; 726 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&cpg CPG_MOD 918>; 728 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 729 resets = <&cpg 918>; 730 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 731 dma-names = "tx", "rx"; 732 i2c-scl-internal-delay-ns = <6>; 733 status = "disabled"; 734 }; 735 736 i2c_dvfs: i2c@e60b0000 { 737 #address-cells = <1>; 738 #size-cells = <0>; 739 compatible = "renesas,iic-r8a774e1", 740 "renesas,rcar-gen3-iic", 741 "renesas,rmobile-iic"; 742 reg = <0 0xe60b0000 0 0x425>; 743 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&cpg CPG_MOD 926>; 745 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 746 resets = <&cpg 926>; 747 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 748 dma-names = "tx", "rx"; 749 status = "disabled"; 750 }; 751 752 hscif0: serial@e6540000 { 753 compatible = "renesas,hscif-r8a774e1", 754 "renesas,rcar-gen3-hscif", 755 "renesas,hscif"; 756 reg = <0 0xe6540000 0 0x60>; 757 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&cpg CPG_MOD 520>, 759 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 760 <&scif_clk>; 761 clock-names = "fck", "brg_int", "scif_clk"; 762 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 763 <&dmac2 0x31>, <&dmac2 0x30>; 764 dma-names = "tx", "rx", "tx", "rx"; 765 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 766 resets = <&cpg 520>; 767 status = "disabled"; 768 }; 769 770 hscif1: serial@e6550000 { 771 compatible = "renesas,hscif-r8a774e1", 772 "renesas,rcar-gen3-hscif", 773 "renesas,hscif"; 774 reg = <0 0xe6550000 0 0x60>; 775 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 776 clocks = <&cpg CPG_MOD 519>, 777 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 778 <&scif_clk>; 779 clock-names = "fck", "brg_int", "scif_clk"; 780 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 781 <&dmac2 0x33>, <&dmac2 0x32>; 782 dma-names = "tx", "rx", "tx", "rx"; 783 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 784 resets = <&cpg 519>; 785 status = "disabled"; 786 }; 787 788 hscif2: serial@e6560000 { 789 compatible = "renesas,hscif-r8a774e1", 790 "renesas,rcar-gen3-hscif", 791 "renesas,hscif"; 792 reg = <0 0xe6560000 0 0x60>; 793 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 794 clocks = <&cpg CPG_MOD 518>, 795 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 796 <&scif_clk>; 797 clock-names = "fck", "brg_int", "scif_clk"; 798 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 799 <&dmac2 0x35>, <&dmac2 0x34>; 800 dma-names = "tx", "rx", "tx", "rx"; 801 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 802 resets = <&cpg 518>; 803 status = "disabled"; 804 }; 805 806 hscif3: serial@e66a0000 { 807 compatible = "renesas,hscif-r8a774e1", 808 "renesas,rcar-gen3-hscif", 809 "renesas,hscif"; 810 reg = <0 0xe66a0000 0 0x60>; 811 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&cpg CPG_MOD 517>, 813 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 814 <&scif_clk>; 815 clock-names = "fck", "brg_int", "scif_clk"; 816 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 817 dma-names = "tx", "rx"; 818 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 819 resets = <&cpg 517>; 820 status = "disabled"; 821 }; 822 823 hscif4: serial@e66b0000 { 824 compatible = "renesas,hscif-r8a774e1", 825 "renesas,rcar-gen3-hscif", 826 "renesas,hscif"; 827 reg = <0 0xe66b0000 0 0x60>; 828 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 829 clocks = <&cpg CPG_MOD 516>, 830 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 831 <&scif_clk>; 832 clock-names = "fck", "brg_int", "scif_clk"; 833 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 834 dma-names = "tx", "rx"; 835 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 836 resets = <&cpg 516>; 837 status = "disabled"; 838 }; 839 840 hsusb: usb@e6590000 { 841 compatible = "renesas,usbhs-r8a774e1", 842 "renesas,rcar-gen3-usbhs"; 843 reg = <0 0xe6590000 0 0x200>; 844 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 845 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 846 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 847 <&usb_dmac1 0>, <&usb_dmac1 1>; 848 dma-names = "ch0", "ch1", "ch2", "ch3"; 849 renesas,buswait = <11>; 850 phys = <&usb2_phy0 3>; 851 phy-names = "usb"; 852 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 853 resets = <&cpg 704>, <&cpg 703>; 854 status = "disabled"; 855 }; 856 857 usb_dmac0: dma-controller@e65a0000 { 858 compatible = "renesas,r8a774e1-usb-dmac", 859 "renesas,usb-dmac"; 860 reg = <0 0xe65a0000 0 0x100>; 861 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 863 interrupt-names = "ch0", "ch1"; 864 clocks = <&cpg CPG_MOD 330>; 865 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 866 resets = <&cpg 330>; 867 #dma-cells = <1>; 868 dma-channels = <2>; 869 }; 870 871 usb_dmac1: dma-controller@e65b0000 { 872 compatible = "renesas,r8a774e1-usb-dmac", 873 "renesas,usb-dmac"; 874 reg = <0 0xe65b0000 0 0x100>; 875 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 877 interrupt-names = "ch0", "ch1"; 878 clocks = <&cpg CPG_MOD 331>; 879 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 880 resets = <&cpg 331>; 881 #dma-cells = <1>; 882 dma-channels = <2>; 883 }; 884 885 usb3_phy0: usb-phy@e65ee000 { 886 compatible = "renesas,r8a774e1-usb3-phy", 887 "renesas,rcar-gen3-usb3-phy"; 888 reg = <0 0xe65ee000 0 0x90>; 889 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 890 <&usb_extal_clk>; 891 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 892 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 893 resets = <&cpg 328>; 894 #phy-cells = <0>; 895 status = "disabled"; 896 }; 897 898 dmac0: dma-controller@e6700000 { 899 compatible = "renesas,dmac-r8a774e1", 900 "renesas,rcar-dmac"; 901 reg = <0 0xe6700000 0 0x10000>; 902 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 918 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 919 interrupt-names = "error", 920 "ch0", "ch1", "ch2", "ch3", 921 "ch4", "ch5", "ch6", "ch7", 922 "ch8", "ch9", "ch10", "ch11", 923 "ch12", "ch13", "ch14", "ch15"; 924 clocks = <&cpg CPG_MOD 219>; 925 clock-names = "fck"; 926 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 927 resets = <&cpg 219>; 928 #dma-cells = <1>; 929 dma-channels = <16>; 930 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 931 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 932 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 933 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 934 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 935 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 936 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 937 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 938 }; 939 940 dmac1: dma-controller@e7300000 { 941 compatible = "renesas,dmac-r8a774e1", 942 "renesas,rcar-dmac"; 943 reg = <0 0xe7300000 0 0x10000>; 944 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 961 interrupt-names = "error", 962 "ch0", "ch1", "ch2", "ch3", 963 "ch4", "ch5", "ch6", "ch7", 964 "ch8", "ch9", "ch10", "ch11", 965 "ch12", "ch13", "ch14", "ch15"; 966 clocks = <&cpg CPG_MOD 218>; 967 clock-names = "fck"; 968 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 969 resets = <&cpg 218>; 970 #dma-cells = <1>; 971 dma-channels = <16>; 972 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 973 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 974 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 975 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 976 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 977 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 978 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 979 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 980 }; 981 982 dmac2: dma-controller@e7310000 { 983 compatible = "renesas,dmac-r8a774e1", 984 "renesas,rcar-dmac"; 985 reg = <0 0xe7310000 0 0x10000>; 986 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 1001 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 1002 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 1003 interrupt-names = "error", 1004 "ch0", "ch1", "ch2", "ch3", 1005 "ch4", "ch5", "ch6", "ch7", 1006 "ch8", "ch9", "ch10", "ch11", 1007 "ch12", "ch13", "ch14", "ch15"; 1008 clocks = <&cpg CPG_MOD 217>; 1009 clock-names = "fck"; 1010 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1011 resets = <&cpg 217>; 1012 #dma-cells = <1>; 1013 dma-channels = <16>; 1014 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 1015 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 1016 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 1017 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 1018 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 1019 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 1020 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 1021 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 1022 }; 1023 1024 ipmmu_ds0: iommu@e6740000 { 1025 compatible = "renesas,ipmmu-r8a774e1"; 1026 reg = <0 0xe6740000 0 0x1000>; 1027 renesas,ipmmu-main = <&ipmmu_mm 0>; 1028 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1029 #iommu-cells = <1>; 1030 }; 1031 1032 ipmmu_ds1: iommu@e7740000 { 1033 compatible = "renesas,ipmmu-r8a774e1"; 1034 reg = <0 0xe7740000 0 0x1000>; 1035 renesas,ipmmu-main = <&ipmmu_mm 1>; 1036 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1037 #iommu-cells = <1>; 1038 }; 1039 1040 ipmmu_hc: iommu@e6570000 { 1041 compatible = "renesas,ipmmu-r8a774e1"; 1042 reg = <0 0xe6570000 0 0x1000>; 1043 renesas,ipmmu-main = <&ipmmu_mm 2>; 1044 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1045 #iommu-cells = <1>; 1046 }; 1047 1048 ipmmu_mm: iommu@e67b0000 { 1049 compatible = "renesas,ipmmu-r8a774e1"; 1050 reg = <0 0xe67b0000 0 0x1000>; 1051 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1053 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1054 #iommu-cells = <1>; 1055 }; 1056 1057 ipmmu_mp0: iommu@ec670000 { 1058 compatible = "renesas,ipmmu-r8a774e1"; 1059 reg = <0 0xec670000 0 0x1000>; 1060 renesas,ipmmu-main = <&ipmmu_mm 4>; 1061 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1062 #iommu-cells = <1>; 1063 }; 1064 1065 ipmmu_pv0: iommu@fd800000 { 1066 compatible = "renesas,ipmmu-r8a774e1"; 1067 reg = <0 0xfd800000 0 0x1000>; 1068 renesas,ipmmu-main = <&ipmmu_mm 6>; 1069 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1070 #iommu-cells = <1>; 1071 }; 1072 1073 ipmmu_pv1: iommu@fd950000 { 1074 compatible = "renesas,ipmmu-r8a774e1"; 1075 reg = <0 0xfd950000 0 0x1000>; 1076 renesas,ipmmu-main = <&ipmmu_mm 7>; 1077 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1078 #iommu-cells = <1>; 1079 }; 1080 1081 ipmmu_pv2: iommu@fd960000 { 1082 compatible = "renesas,ipmmu-r8a774e1"; 1083 reg = <0 0xfd960000 0 0x1000>; 1084 renesas,ipmmu-main = <&ipmmu_mm 8>; 1085 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1086 #iommu-cells = <1>; 1087 }; 1088 1089 ipmmu_pv3: iommu@fd970000 { 1090 compatible = "renesas,ipmmu-r8a774e1"; 1091 reg = <0 0xfd970000 0 0x1000>; 1092 renesas,ipmmu-main = <&ipmmu_mm 9>; 1093 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1094 #iommu-cells = <1>; 1095 }; 1096 1097 ipmmu_vc0: iommu@fe6b0000 { 1098 compatible = "renesas,ipmmu-r8a774e1"; 1099 reg = <0 0xfe6b0000 0 0x1000>; 1100 renesas,ipmmu-main = <&ipmmu_mm 12>; 1101 power-domains = <&sysc R8A774E1_PD_A3VC>; 1102 #iommu-cells = <1>; 1103 }; 1104 1105 ipmmu_vc1: iommu@fe6f0000 { 1106 compatible = "renesas,ipmmu-r8a774e1"; 1107 reg = <0 0xfe6f0000 0 0x1000>; 1108 renesas,ipmmu-main = <&ipmmu_mm 13>; 1109 power-domains = <&sysc R8A774E1_PD_A3VC>; 1110 #iommu-cells = <1>; 1111 }; 1112 1113 ipmmu_vi0: iommu@febd0000 { 1114 compatible = "renesas,ipmmu-r8a774e1"; 1115 reg = <0 0xfebd0000 0 0x1000>; 1116 renesas,ipmmu-main = <&ipmmu_mm 14>; 1117 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1118 #iommu-cells = <1>; 1119 }; 1120 1121 ipmmu_vi1: iommu@febe0000 { 1122 compatible = "renesas,ipmmu-r8a774e1"; 1123 reg = <0 0xfebe0000 0 0x1000>; 1124 renesas,ipmmu-main = <&ipmmu_mm 15>; 1125 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1126 #iommu-cells = <1>; 1127 }; 1128 1129 ipmmu_vp0: iommu@fe990000 { 1130 compatible = "renesas,ipmmu-r8a774e1"; 1131 reg = <0 0xfe990000 0 0x1000>; 1132 renesas,ipmmu-main = <&ipmmu_mm 16>; 1133 power-domains = <&sysc R8A774E1_PD_A3VP>; 1134 #iommu-cells = <1>; 1135 }; 1136 1137 ipmmu_vp1: iommu@fe980000 { 1138 compatible = "renesas,ipmmu-r8a774e1"; 1139 reg = <0 0xfe980000 0 0x1000>; 1140 renesas,ipmmu-main = <&ipmmu_mm 17>; 1141 power-domains = <&sysc R8A774E1_PD_A3VP>; 1142 #iommu-cells = <1>; 1143 }; 1144 1145 avb: ethernet@e6800000 { 1146 compatible = "renesas,etheravb-r8a774e1", 1147 "renesas,etheravb-rcar-gen3"; 1148 reg = <0 0xe6800000 0 0x800>; 1149 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1174 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1175 "ch4", "ch5", "ch6", "ch7", 1176 "ch8", "ch9", "ch10", "ch11", 1177 "ch12", "ch13", "ch14", "ch15", 1178 "ch16", "ch17", "ch18", "ch19", 1179 "ch20", "ch21", "ch22", "ch23", 1180 "ch24"; 1181 clocks = <&cpg CPG_MOD 812>; 1182 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1183 resets = <&cpg 812>; 1184 phy-mode = "rgmii"; 1185 iommus = <&ipmmu_ds0 16>; 1186 #address-cells = <1>; 1187 #size-cells = <0>; 1188 status = "disabled"; 1189 }; 1190 1191 can0: can@e6c30000 { 1192 compatible = "renesas,can-r8a774e1", 1193 "renesas,rcar-gen3-can"; 1194 reg = <0 0xe6c30000 0 0x1000>; 1195 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1196 clocks = <&cpg CPG_MOD 916>, 1197 <&cpg CPG_CORE R8A774E1_CLK_CANFD>, 1198 <&can_clk>; 1199 clock-names = "clkp1", "clkp2", "can_clk"; 1200 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; 1201 assigned-clock-rates = <40000000>; 1202 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1203 resets = <&cpg 916>; 1204 status = "disabled"; 1205 }; 1206 1207 can1: can@e6c38000 { 1208 compatible = "renesas,can-r8a774e1", 1209 "renesas,rcar-gen3-can"; 1210 reg = <0 0xe6c38000 0 0x1000>; 1211 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1212 clocks = <&cpg CPG_MOD 915>, 1213 <&cpg CPG_CORE R8A774E1_CLK_CANFD>, 1214 <&can_clk>; 1215 clock-names = "clkp1", "clkp2", "can_clk"; 1216 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; 1217 assigned-clock-rates = <40000000>; 1218 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1219 resets = <&cpg 915>; 1220 status = "disabled"; 1221 }; 1222 1223 canfd: can@e66c0000 { 1224 compatible = "renesas,r8a774e1-canfd", 1225 "renesas,rcar-gen3-canfd"; 1226 reg = <0 0xe66c0000 0 0x8000>; 1227 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1229 clocks = <&cpg CPG_MOD 914>, 1230 <&cpg CPG_CORE R8A774E1_CLK_CANFD>, 1231 <&can_clk>; 1232 clock-names = "fck", "canfd", "can_clk"; 1233 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; 1234 assigned-clock-rates = <40000000>; 1235 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1236 resets = <&cpg 914>; 1237 status = "disabled"; 1238 1239 channel0 { 1240 status = "disabled"; 1241 }; 1242 1243 channel1 { 1244 status = "disabled"; 1245 }; 1246 }; 1247 1248 pwm0: pwm@e6e30000 { 1249 reg = <0 0xe6e30000 0 0x8>; 1250 #pwm-cells = <2>; 1251 status = "disabled"; 1252 1253 /* placeholder */ 1254 }; 1255 1256 scif0: serial@e6e60000 { 1257 compatible = "renesas,scif-r8a774e1", 1258 "renesas,rcar-gen3-scif", "renesas,scif"; 1259 reg = <0 0xe6e60000 0 0x40>; 1260 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1261 clocks = <&cpg CPG_MOD 207>, 1262 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1263 <&scif_clk>; 1264 clock-names = "fck", "brg_int", "scif_clk"; 1265 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1266 <&dmac2 0x51>, <&dmac2 0x50>; 1267 dma-names = "tx", "rx", "tx", "rx"; 1268 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1269 resets = <&cpg 207>; 1270 status = "disabled"; 1271 }; 1272 1273 scif1: serial@e6e68000 { 1274 compatible = "renesas,scif-r8a774e1", 1275 "renesas,rcar-gen3-scif", "renesas,scif"; 1276 reg = <0 0xe6e68000 0 0x40>; 1277 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1278 clocks = <&cpg CPG_MOD 206>, 1279 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1280 <&scif_clk>; 1281 clock-names = "fck", "brg_int", "scif_clk"; 1282 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1283 <&dmac2 0x53>, <&dmac2 0x52>; 1284 dma-names = "tx", "rx", "tx", "rx"; 1285 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1286 resets = <&cpg 206>; 1287 status = "disabled"; 1288 }; 1289 1290 scif2: serial@e6e88000 { 1291 compatible = "renesas,scif-r8a774e1", 1292 "renesas,rcar-gen3-scif", "renesas,scif"; 1293 reg = <0 0xe6e88000 0 0x40>; 1294 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1295 clocks = <&cpg CPG_MOD 310>, 1296 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1297 <&scif_clk>; 1298 clock-names = "fck", "brg_int", "scif_clk"; 1299 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1300 <&dmac2 0x13>, <&dmac2 0x12>; 1301 dma-names = "tx", "rx", "tx", "rx"; 1302 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1303 resets = <&cpg 310>; 1304 status = "disabled"; 1305 }; 1306 1307 scif3: serial@e6c50000 { 1308 compatible = "renesas,scif-r8a774e1", 1309 "renesas,rcar-gen3-scif", "renesas,scif"; 1310 reg = <0 0xe6c50000 0 0x40>; 1311 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1312 clocks = <&cpg CPG_MOD 204>, 1313 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1314 <&scif_clk>; 1315 clock-names = "fck", "brg_int", "scif_clk"; 1316 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1317 dma-names = "tx", "rx"; 1318 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1319 resets = <&cpg 204>; 1320 status = "disabled"; 1321 }; 1322 1323 scif4: serial@e6c40000 { 1324 compatible = "renesas,scif-r8a774e1", 1325 "renesas,rcar-gen3-scif", "renesas,scif"; 1326 reg = <0 0xe6c40000 0 0x40>; 1327 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1328 clocks = <&cpg CPG_MOD 203>, 1329 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1330 <&scif_clk>; 1331 clock-names = "fck", "brg_int", "scif_clk"; 1332 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1333 dma-names = "tx", "rx"; 1334 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1335 resets = <&cpg 203>; 1336 status = "disabled"; 1337 }; 1338 1339 scif5: serial@e6f30000 { 1340 compatible = "renesas,scif-r8a774e1", 1341 "renesas,rcar-gen3-scif", "renesas,scif"; 1342 reg = <0 0xe6f30000 0 0x40>; 1343 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1344 clocks = <&cpg CPG_MOD 202>, 1345 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1346 <&scif_clk>; 1347 clock-names = "fck", "brg_int", "scif_clk"; 1348 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1349 <&dmac2 0x5b>, <&dmac2 0x5a>; 1350 dma-names = "tx", "rx", "tx", "rx"; 1351 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1352 resets = <&cpg 202>; 1353 status = "disabled"; 1354 }; 1355 1356 msiof0: spi@e6e90000 { 1357 compatible = "renesas,msiof-r8a774e1", 1358 "renesas,rcar-gen3-msiof"; 1359 reg = <0 0xe6e90000 0 0x0064>; 1360 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1361 clocks = <&cpg CPG_MOD 211>; 1362 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1363 <&dmac2 0x41>, <&dmac2 0x40>; 1364 dma-names = "tx", "rx", "tx", "rx"; 1365 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1366 resets = <&cpg 211>; 1367 #address-cells = <1>; 1368 #size-cells = <0>; 1369 status = "disabled"; 1370 }; 1371 1372 msiof1: spi@e6ea0000 { 1373 compatible = "renesas,msiof-r8a774e1", 1374 "renesas,rcar-gen3-msiof"; 1375 reg = <0 0xe6ea0000 0 0x0064>; 1376 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1377 clocks = <&cpg CPG_MOD 210>; 1378 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1379 <&dmac2 0x43>, <&dmac2 0x42>; 1380 dma-names = "tx", "rx", "tx", "rx"; 1381 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1382 resets = <&cpg 210>; 1383 #address-cells = <1>; 1384 #size-cells = <0>; 1385 status = "disabled"; 1386 }; 1387 1388 msiof2: spi@e6c00000 { 1389 compatible = "renesas,msiof-r8a774e1", 1390 "renesas,rcar-gen3-msiof"; 1391 reg = <0 0xe6c00000 0 0x0064>; 1392 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1393 clocks = <&cpg CPG_MOD 209>; 1394 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1395 dma-names = "tx", "rx"; 1396 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1397 resets = <&cpg 209>; 1398 #address-cells = <1>; 1399 #size-cells = <0>; 1400 status = "disabled"; 1401 }; 1402 1403 msiof3: spi@e6c10000 { 1404 compatible = "renesas,msiof-r8a774e1", 1405 "renesas,rcar-gen3-msiof"; 1406 reg = <0 0xe6c10000 0 0x0064>; 1407 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1408 clocks = <&cpg CPG_MOD 208>; 1409 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1410 dma-names = "tx", "rx"; 1411 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1412 resets = <&cpg 208>; 1413 #address-cells = <1>; 1414 #size-cells = <0>; 1415 status = "disabled"; 1416 }; 1417 1418 vin0: video@e6ef0000 { 1419 compatible = "renesas,vin-r8a774e1"; 1420 reg = <0 0xe6ef0000 0 0x1000>; 1421 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1422 clocks = <&cpg CPG_MOD 811>; 1423 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1424 resets = <&cpg 811>; 1425 renesas,id = <0>; 1426 status = "disabled"; 1427 1428 ports { 1429 #address-cells = <1>; 1430 #size-cells = <0>; 1431 1432 port@1 { 1433 #address-cells = <1>; 1434 #size-cells = <0>; 1435 1436 reg = <1>; 1437 1438 vin0csi20: endpoint@0 { 1439 reg = <0>; 1440 remote-endpoint = <&csi20vin0>; 1441 }; 1442 vin0csi40: endpoint@2 { 1443 reg = <2>; 1444 remote-endpoint = <&csi40vin0>; 1445 }; 1446 }; 1447 }; 1448 }; 1449 1450 vin1: video@e6ef1000 { 1451 compatible = "renesas,vin-r8a774e1"; 1452 reg = <0 0xe6ef1000 0 0x1000>; 1453 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1454 clocks = <&cpg CPG_MOD 810>; 1455 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1456 resets = <&cpg 810>; 1457 renesas,id = <1>; 1458 status = "disabled"; 1459 1460 ports { 1461 #address-cells = <1>; 1462 #size-cells = <0>; 1463 1464 port@1 { 1465 #address-cells = <1>; 1466 #size-cells = <0>; 1467 1468 reg = <1>; 1469 1470 vin1csi20: endpoint@0 { 1471 reg = <0>; 1472 remote-endpoint = <&csi20vin1>; 1473 }; 1474 vin1csi40: endpoint@2 { 1475 reg = <2>; 1476 remote-endpoint = <&csi40vin1>; 1477 }; 1478 }; 1479 }; 1480 }; 1481 1482 vin2: video@e6ef2000 { 1483 compatible = "renesas,vin-r8a774e1"; 1484 reg = <0 0xe6ef2000 0 0x1000>; 1485 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1486 clocks = <&cpg CPG_MOD 809>; 1487 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1488 resets = <&cpg 809>; 1489 renesas,id = <2>; 1490 status = "disabled"; 1491 1492 ports { 1493 #address-cells = <1>; 1494 #size-cells = <0>; 1495 1496 port@1 { 1497 #address-cells = <1>; 1498 #size-cells = <0>; 1499 1500 reg = <1>; 1501 1502 vin2csi20: endpoint@0 { 1503 reg = <0>; 1504 remote-endpoint = <&csi20vin2>; 1505 }; 1506 vin2csi40: endpoint@2 { 1507 reg = <2>; 1508 remote-endpoint = <&csi40vin2>; 1509 }; 1510 }; 1511 }; 1512 }; 1513 1514 vin3: video@e6ef3000 { 1515 compatible = "renesas,vin-r8a774e1"; 1516 reg = <0 0xe6ef3000 0 0x1000>; 1517 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1518 clocks = <&cpg CPG_MOD 808>; 1519 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1520 resets = <&cpg 808>; 1521 renesas,id = <3>; 1522 status = "disabled"; 1523 1524 ports { 1525 #address-cells = <1>; 1526 #size-cells = <0>; 1527 1528 port@1 { 1529 #address-cells = <1>; 1530 #size-cells = <0>; 1531 1532 reg = <1>; 1533 1534 vin3csi20: endpoint@0 { 1535 reg = <0>; 1536 remote-endpoint = <&csi20vin3>; 1537 }; 1538 vin3csi40: endpoint@2 { 1539 reg = <2>; 1540 remote-endpoint = <&csi40vin3>; 1541 }; 1542 }; 1543 }; 1544 }; 1545 1546 vin4: video@e6ef4000 { 1547 compatible = "renesas,vin-r8a774e1"; 1548 reg = <0 0xe6ef4000 0 0x1000>; 1549 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1550 clocks = <&cpg CPG_MOD 807>; 1551 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1552 resets = <&cpg 807>; 1553 renesas,id = <4>; 1554 status = "disabled"; 1555 1556 ports { 1557 #address-cells = <1>; 1558 #size-cells = <0>; 1559 1560 port@1 { 1561 #address-cells = <1>; 1562 #size-cells = <0>; 1563 1564 reg = <1>; 1565 1566 vin4csi20: endpoint@0 { 1567 reg = <0>; 1568 remote-endpoint = <&csi20vin4>; 1569 }; 1570 }; 1571 }; 1572 }; 1573 1574 vin5: video@e6ef5000 { 1575 compatible = "renesas,vin-r8a774e1"; 1576 reg = <0 0xe6ef5000 0 0x1000>; 1577 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1578 clocks = <&cpg CPG_MOD 806>; 1579 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1580 resets = <&cpg 806>; 1581 renesas,id = <5>; 1582 status = "disabled"; 1583 1584 ports { 1585 #address-cells = <1>; 1586 #size-cells = <0>; 1587 1588 port@1 { 1589 #address-cells = <1>; 1590 #size-cells = <0>; 1591 1592 reg = <1>; 1593 1594 vin5csi20: endpoint@0 { 1595 reg = <0>; 1596 remote-endpoint = <&csi20vin5>; 1597 }; 1598 }; 1599 }; 1600 }; 1601 1602 vin6: video@e6ef6000 { 1603 compatible = "renesas,vin-r8a774e1"; 1604 reg = <0 0xe6ef6000 0 0x1000>; 1605 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1606 clocks = <&cpg CPG_MOD 805>; 1607 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1608 resets = <&cpg 805>; 1609 renesas,id = <6>; 1610 status = "disabled"; 1611 1612 ports { 1613 #address-cells = <1>; 1614 #size-cells = <0>; 1615 1616 port@1 { 1617 #address-cells = <1>; 1618 #size-cells = <0>; 1619 1620 reg = <1>; 1621 1622 vin6csi20: endpoint@0 { 1623 reg = <0>; 1624 remote-endpoint = <&csi20vin6>; 1625 }; 1626 }; 1627 }; 1628 }; 1629 1630 vin7: video@e6ef7000 { 1631 compatible = "renesas,vin-r8a774e1"; 1632 reg = <0 0xe6ef7000 0 0x1000>; 1633 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 1634 clocks = <&cpg CPG_MOD 804>; 1635 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1636 resets = <&cpg 804>; 1637 renesas,id = <7>; 1638 status = "disabled"; 1639 1640 ports { 1641 #address-cells = <1>; 1642 #size-cells = <0>; 1643 1644 port@1 { 1645 #address-cells = <1>; 1646 #size-cells = <0>; 1647 1648 reg = <1>; 1649 1650 vin7csi20: endpoint@0 { 1651 reg = <0>; 1652 remote-endpoint = <&csi20vin7>; 1653 }; 1654 }; 1655 }; 1656 }; 1657 1658 rcar_sound: sound@ec500000 { 1659 /* 1660 * #sound-dai-cells is required 1661 * 1662 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1663 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1664 */ 1665 /* 1666 * #clock-cells is required for audio_clkout0/1/2/3 1667 * 1668 * clkout : #clock-cells = <0>; <&rcar_sound>; 1669 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1670 */ 1671 compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3"; 1672 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1673 <0 0xec5a0000 0 0x100>, /* ADG */ 1674 <0 0xec540000 0 0x1000>, /* SSIU */ 1675 <0 0xec541000 0 0x280>, /* SSI */ 1676 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1677 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1678 1679 clocks = <&cpg CPG_MOD 1005>, 1680 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1681 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1682 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1683 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1684 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1685 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1686 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1687 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1688 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1689 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1690 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1691 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1692 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1693 <&audio_clk_a>, <&audio_clk_b>, 1694 <&audio_clk_c>, 1695 <&cpg CPG_CORE R8A774E1_CLK_S0D4>; 1696 clock-names = "ssi-all", 1697 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1698 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1699 "ssi.1", "ssi.0", 1700 "src.9", "src.8", "src.7", "src.6", 1701 "src.5", "src.4", "src.3", "src.2", 1702 "src.1", "src.0", 1703 "mix.1", "mix.0", 1704 "ctu.1", "ctu.0", 1705 "dvc.0", "dvc.1", 1706 "clk_a", "clk_b", "clk_c", "clk_i"; 1707 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1708 resets = <&cpg 1005>, 1709 <&cpg 1006>, <&cpg 1007>, 1710 <&cpg 1008>, <&cpg 1009>, 1711 <&cpg 1010>, <&cpg 1011>, 1712 <&cpg 1012>, <&cpg 1013>, 1713 <&cpg 1014>, <&cpg 1015>; 1714 reset-names = "ssi-all", 1715 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1716 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1717 "ssi.1", "ssi.0"; 1718 status = "disabled"; 1719 1720 rcar_sound,dvc { 1721 dvc0: dvc-0 { 1722 dmas = <&audma1 0xbc>; 1723 dma-names = "tx"; 1724 }; 1725 dvc1: dvc-1 { 1726 dmas = <&audma1 0xbe>; 1727 dma-names = "tx"; 1728 }; 1729 }; 1730 1731 rcar_sound,mix { 1732 mix0: mix-0 { }; 1733 mix1: mix-1 { }; 1734 }; 1735 1736 rcar_sound,ctu { 1737 ctu00: ctu-0 { }; 1738 ctu01: ctu-1 { }; 1739 ctu02: ctu-2 { }; 1740 ctu03: ctu-3 { }; 1741 ctu10: ctu-4 { }; 1742 ctu11: ctu-5 { }; 1743 ctu12: ctu-6 { }; 1744 ctu13: ctu-7 { }; 1745 }; 1746 1747 rcar_sound,src { 1748 src0: src-0 { 1749 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1750 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1751 dma-names = "rx", "tx"; 1752 }; 1753 src1: src-1 { 1754 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1755 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1756 dma-names = "rx", "tx"; 1757 }; 1758 src2: src-2 { 1759 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1760 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1761 dma-names = "rx", "tx"; 1762 }; 1763 src3: src-3 { 1764 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1765 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1766 dma-names = "rx", "tx"; 1767 }; 1768 src4: src-4 { 1769 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1770 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1771 dma-names = "rx", "tx"; 1772 }; 1773 src5: src-5 { 1774 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1775 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1776 dma-names = "rx", "tx"; 1777 }; 1778 src6: src-6 { 1779 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1780 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1781 dma-names = "rx", "tx"; 1782 }; 1783 src7: src-7 { 1784 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1785 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1786 dma-names = "rx", "tx"; 1787 }; 1788 src8: src-8 { 1789 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1790 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1791 dma-names = "rx", "tx"; 1792 }; 1793 src9: src-9 { 1794 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1795 dmas = <&audma0 0x97>, <&audma1 0xba>; 1796 dma-names = "rx", "tx"; 1797 }; 1798 }; 1799 1800 rcar_sound,ssiu { 1801 ssiu00: ssiu-0 { 1802 dmas = <&audma0 0x15>, <&audma1 0x16>; 1803 dma-names = "rx", "tx"; 1804 }; 1805 ssiu01: ssiu-1 { 1806 dmas = <&audma0 0x35>, <&audma1 0x36>; 1807 dma-names = "rx", "tx"; 1808 }; 1809 ssiu02: ssiu-2 { 1810 dmas = <&audma0 0x37>, <&audma1 0x38>; 1811 dma-names = "rx", "tx"; 1812 }; 1813 ssiu03: ssiu-3 { 1814 dmas = <&audma0 0x47>, <&audma1 0x48>; 1815 dma-names = "rx", "tx"; 1816 }; 1817 ssiu04: ssiu-4 { 1818 dmas = <&audma0 0x3F>, <&audma1 0x40>; 1819 dma-names = "rx", "tx"; 1820 }; 1821 ssiu05: ssiu-5 { 1822 dmas = <&audma0 0x43>, <&audma1 0x44>; 1823 dma-names = "rx", "tx"; 1824 }; 1825 ssiu06: ssiu-6 { 1826 dmas = <&audma0 0x4F>, <&audma1 0x50>; 1827 dma-names = "rx", "tx"; 1828 }; 1829 ssiu07: ssiu-7 { 1830 dmas = <&audma0 0x53>, <&audma1 0x54>; 1831 dma-names = "rx", "tx"; 1832 }; 1833 ssiu10: ssiu-8 { 1834 dmas = <&audma0 0x49>, <&audma1 0x4a>; 1835 dma-names = "rx", "tx"; 1836 }; 1837 ssiu11: ssiu-9 { 1838 dmas = <&audma0 0x4B>, <&audma1 0x4C>; 1839 dma-names = "rx", "tx"; 1840 }; 1841 ssiu12: ssiu-10 { 1842 dmas = <&audma0 0x57>, <&audma1 0x58>; 1843 dma-names = "rx", "tx"; 1844 }; 1845 ssiu13: ssiu-11 { 1846 dmas = <&audma0 0x59>, <&audma1 0x5A>; 1847 dma-names = "rx", "tx"; 1848 }; 1849 ssiu14: ssiu-12 { 1850 dmas = <&audma0 0x5F>, <&audma1 0x60>; 1851 dma-names = "rx", "tx"; 1852 }; 1853 ssiu15: ssiu-13 { 1854 dmas = <&audma0 0xC3>, <&audma1 0xC4>; 1855 dma-names = "rx", "tx"; 1856 }; 1857 ssiu16: ssiu-14 { 1858 dmas = <&audma0 0xC7>, <&audma1 0xC8>; 1859 dma-names = "rx", "tx"; 1860 }; 1861 ssiu17: ssiu-15 { 1862 dmas = <&audma0 0xCB>, <&audma1 0xCC>; 1863 dma-names = "rx", "tx"; 1864 }; 1865 ssiu20: ssiu-16 { 1866 dmas = <&audma0 0x63>, <&audma1 0x64>; 1867 dma-names = "rx", "tx"; 1868 }; 1869 ssiu21: ssiu-17 { 1870 dmas = <&audma0 0x67>, <&audma1 0x68>; 1871 dma-names = "rx", "tx"; 1872 }; 1873 ssiu22: ssiu-18 { 1874 dmas = <&audma0 0x6B>, <&audma1 0x6C>; 1875 dma-names = "rx", "tx"; 1876 }; 1877 ssiu23: ssiu-19 { 1878 dmas = <&audma0 0x6D>, <&audma1 0x6E>; 1879 dma-names = "rx", "tx"; 1880 }; 1881 ssiu24: ssiu-20 { 1882 dmas = <&audma0 0xCF>, <&audma1 0xCE>; 1883 dma-names = "rx", "tx"; 1884 }; 1885 ssiu25: ssiu-21 { 1886 dmas = <&audma0 0xEB>, <&audma1 0xEC>; 1887 dma-names = "rx", "tx"; 1888 }; 1889 ssiu26: ssiu-22 { 1890 dmas = <&audma0 0xED>, <&audma1 0xEE>; 1891 dma-names = "rx", "tx"; 1892 }; 1893 ssiu27: ssiu-23 { 1894 dmas = <&audma0 0xEF>, <&audma1 0xF0>; 1895 dma-names = "rx", "tx"; 1896 }; 1897 ssiu30: ssiu-24 { 1898 dmas = <&audma0 0x6f>, <&audma1 0x70>; 1899 dma-names = "rx", "tx"; 1900 }; 1901 ssiu31: ssiu-25 { 1902 dmas = <&audma0 0x21>, <&audma1 0x22>; 1903 dma-names = "rx", "tx"; 1904 }; 1905 ssiu32: ssiu-26 { 1906 dmas = <&audma0 0x23>, <&audma1 0x24>; 1907 dma-names = "rx", "tx"; 1908 }; 1909 ssiu33: ssiu-27 { 1910 dmas = <&audma0 0x25>, <&audma1 0x26>; 1911 dma-names = "rx", "tx"; 1912 }; 1913 ssiu34: ssiu-28 { 1914 dmas = <&audma0 0x27>, <&audma1 0x28>; 1915 dma-names = "rx", "tx"; 1916 }; 1917 ssiu35: ssiu-29 { 1918 dmas = <&audma0 0x29>, <&audma1 0x2A>; 1919 dma-names = "rx", "tx"; 1920 }; 1921 ssiu36: ssiu-30 { 1922 dmas = <&audma0 0x2B>, <&audma1 0x2C>; 1923 dma-names = "rx", "tx"; 1924 }; 1925 ssiu37: ssiu-31 { 1926 dmas = <&audma0 0x2D>, <&audma1 0x2E>; 1927 dma-names = "rx", "tx"; 1928 }; 1929 ssiu40: ssiu-32 { 1930 dmas = <&audma0 0x71>, <&audma1 0x72>; 1931 dma-names = "rx", "tx"; 1932 }; 1933 ssiu41: ssiu-33 { 1934 dmas = <&audma0 0x17>, <&audma1 0x18>; 1935 dma-names = "rx", "tx"; 1936 }; 1937 ssiu42: ssiu-34 { 1938 dmas = <&audma0 0x19>, <&audma1 0x1A>; 1939 dma-names = "rx", "tx"; 1940 }; 1941 ssiu43: ssiu-35 { 1942 dmas = <&audma0 0x1B>, <&audma1 0x1C>; 1943 dma-names = "rx", "tx"; 1944 }; 1945 ssiu44: ssiu-36 { 1946 dmas = <&audma0 0x1D>, <&audma1 0x1E>; 1947 dma-names = "rx", "tx"; 1948 }; 1949 ssiu45: ssiu-37 { 1950 dmas = <&audma0 0x1F>, <&audma1 0x20>; 1951 dma-names = "rx", "tx"; 1952 }; 1953 ssiu46: ssiu-38 { 1954 dmas = <&audma0 0x31>, <&audma1 0x32>; 1955 dma-names = "rx", "tx"; 1956 }; 1957 ssiu47: ssiu-39 { 1958 dmas = <&audma0 0x33>, <&audma1 0x34>; 1959 dma-names = "rx", "tx"; 1960 }; 1961 ssiu50: ssiu-40 { 1962 dmas = <&audma0 0x73>, <&audma1 0x74>; 1963 dma-names = "rx", "tx"; 1964 }; 1965 ssiu60: ssiu-41 { 1966 dmas = <&audma0 0x75>, <&audma1 0x76>; 1967 dma-names = "rx", "tx"; 1968 }; 1969 ssiu70: ssiu-42 { 1970 dmas = <&audma0 0x79>, <&audma1 0x7a>; 1971 dma-names = "rx", "tx"; 1972 }; 1973 ssiu80: ssiu-43 { 1974 dmas = <&audma0 0x7b>, <&audma1 0x7c>; 1975 dma-names = "rx", "tx"; 1976 }; 1977 ssiu90: ssiu-44 { 1978 dmas = <&audma0 0x7d>, <&audma1 0x7e>; 1979 dma-names = "rx", "tx"; 1980 }; 1981 ssiu91: ssiu-45 { 1982 dmas = <&audma0 0x7F>, <&audma1 0x80>; 1983 dma-names = "rx", "tx"; 1984 }; 1985 ssiu92: ssiu-46 { 1986 dmas = <&audma0 0x81>, <&audma1 0x82>; 1987 dma-names = "rx", "tx"; 1988 }; 1989 ssiu93: ssiu-47 { 1990 dmas = <&audma0 0x83>, <&audma1 0x84>; 1991 dma-names = "rx", "tx"; 1992 }; 1993 ssiu94: ssiu-48 { 1994 dmas = <&audma0 0xA3>, <&audma1 0xA4>; 1995 dma-names = "rx", "tx"; 1996 }; 1997 ssiu95: ssiu-49 { 1998 dmas = <&audma0 0xA5>, <&audma1 0xA6>; 1999 dma-names = "rx", "tx"; 2000 }; 2001 ssiu96: ssiu-50 { 2002 dmas = <&audma0 0xA7>, <&audma1 0xA8>; 2003 dma-names = "rx", "tx"; 2004 }; 2005 ssiu97: ssiu-51 { 2006 dmas = <&audma0 0xA9>, <&audma1 0xAA>; 2007 dma-names = "rx", "tx"; 2008 }; 2009 }; 2010 2011 rcar_sound,ssi { 2012 ssi0: ssi-0 { 2013 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 2014 dmas = <&audma0 0x01>, <&audma1 0x02>; 2015 dma-names = "rx", "tx"; 2016 }; 2017 ssi1: ssi-1 { 2018 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 2019 dmas = <&audma0 0x03>, <&audma1 0x04>; 2020 dma-names = "rx", "tx"; 2021 }; 2022 ssi2: ssi-2 { 2023 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 2024 dmas = <&audma0 0x05>, <&audma1 0x06>; 2025 dma-names = "rx", "tx"; 2026 }; 2027 ssi3: ssi-3 { 2028 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2029 dmas = <&audma0 0x07>, <&audma1 0x08>; 2030 dma-names = "rx", "tx"; 2031 }; 2032 ssi4: ssi-4 { 2033 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 2034 dmas = <&audma0 0x09>, <&audma1 0x0a>; 2035 dma-names = "rx", "tx"; 2036 }; 2037 ssi5: ssi-5 { 2038 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 2039 dmas = <&audma0 0x0b>, <&audma1 0x0c>; 2040 dma-names = "rx", "tx"; 2041 }; 2042 ssi6: ssi-6 { 2043 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 2044 dmas = <&audma0 0x0d>, <&audma1 0x0e>; 2045 dma-names = "rx", "tx"; 2046 }; 2047 ssi7: ssi-7 { 2048 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 2049 dmas = <&audma0 0x0f>, <&audma1 0x10>; 2050 dma-names = "rx", "tx"; 2051 }; 2052 ssi8: ssi-8 { 2053 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 2054 dmas = <&audma0 0x11>, <&audma1 0x12>; 2055 dma-names = "rx", "tx"; 2056 }; 2057 ssi9: ssi-9 { 2058 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 2059 dmas = <&audma0 0x13>, <&audma1 0x14>; 2060 dma-names = "rx", "tx"; 2061 }; 2062 }; 2063 }; 2064 2065 audma0: dma-controller@ec700000 { 2066 compatible = "renesas,dmac-r8a774e1", 2067 "renesas,rcar-dmac"; 2068 reg = <0 0xec700000 0 0x10000>; 2069 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 2070 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2071 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2072 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2073 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2074 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2075 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2076 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2077 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2078 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2079 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2080 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2081 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2082 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2083 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2084 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2085 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 2086 interrupt-names = "error", 2087 "ch0", "ch1", "ch2", "ch3", 2088 "ch4", "ch5", "ch6", "ch7", 2089 "ch8", "ch9", "ch10", "ch11", 2090 "ch12", "ch13", "ch14", "ch15"; 2091 clocks = <&cpg CPG_MOD 502>; 2092 clock-names = "fck"; 2093 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2094 resets = <&cpg 502>; 2095 #dma-cells = <1>; 2096 dma-channels = <16>; 2097 iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, 2098 <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, 2099 <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, 2100 <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, 2101 <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, 2102 <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, 2103 <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, 2104 <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; 2105 }; 2106 2107 audma1: dma-controller@ec720000 { 2108 compatible = "renesas,dmac-r8a774e1", 2109 "renesas,rcar-dmac"; 2110 reg = <0 0xec720000 0 0x10000>; 2111 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 2112 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2113 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2114 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2115 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2116 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2117 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2118 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2119 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2120 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2121 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2122 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 2123 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2124 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 2125 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 2126 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 2127 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 2128 interrupt-names = "error", 2129 "ch0", "ch1", "ch2", "ch3", 2130 "ch4", "ch5", "ch6", "ch7", 2131 "ch8", "ch9", "ch10", "ch11", 2132 "ch12", "ch13", "ch14", "ch15"; 2133 clocks = <&cpg CPG_MOD 501>; 2134 clock-names = "fck"; 2135 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2136 resets = <&cpg 501>; 2137 #dma-cells = <1>; 2138 dma-channels = <16>; 2139 iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, 2140 <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, 2141 <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, 2142 <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, 2143 <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, 2144 <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, 2145 <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, 2146 <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; 2147 }; 2148 2149 xhci0: usb@ee000000 { 2150 compatible = "renesas,xhci-r8a774e1", 2151 "renesas,rcar-gen3-xhci"; 2152 reg = <0 0xee000000 0 0xc00>; 2153 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2154 clocks = <&cpg CPG_MOD 328>; 2155 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2156 resets = <&cpg 328>; 2157 status = "disabled"; 2158 }; 2159 2160 usb3_peri0: usb@ee020000 { 2161 compatible = "renesas,r8a774e1-usb3-peri", 2162 "renesas,rcar-gen3-usb3-peri"; 2163 reg = <0 0xee020000 0 0x400>; 2164 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2165 clocks = <&cpg CPG_MOD 328>; 2166 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2167 resets = <&cpg 328>; 2168 status = "disabled"; 2169 }; 2170 2171 ohci0: usb@ee080000 { 2172 compatible = "generic-ohci"; 2173 reg = <0 0xee080000 0 0x100>; 2174 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2175 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2176 phys = <&usb2_phy0 1>; 2177 phy-names = "usb"; 2178 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2179 resets = <&cpg 703>, <&cpg 704>; 2180 status = "disabled"; 2181 }; 2182 2183 ohci1: usb@ee0a0000 { 2184 compatible = "generic-ohci"; 2185 reg = <0 0xee0a0000 0 0x100>; 2186 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2187 clocks = <&cpg CPG_MOD 702>; 2188 phys = <&usb2_phy1 1>; 2189 phy-names = "usb"; 2190 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2191 resets = <&cpg 702>; 2192 status = "disabled"; 2193 }; 2194 2195 ehci0: usb@ee080100 { 2196 compatible = "generic-ehci"; 2197 reg = <0 0xee080100 0 0x100>; 2198 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2199 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2200 phys = <&usb2_phy0 2>; 2201 phy-names = "usb"; 2202 companion = <&ohci0>; 2203 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2204 resets = <&cpg 703>, <&cpg 704>; 2205 status = "disabled"; 2206 }; 2207 2208 ehci1: usb@ee0a0100 { 2209 compatible = "generic-ehci"; 2210 reg = <0 0xee0a0100 0 0x100>; 2211 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2212 clocks = <&cpg CPG_MOD 702>; 2213 phys = <&usb2_phy1 2>; 2214 phy-names = "usb"; 2215 companion = <&ohci1>; 2216 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2217 resets = <&cpg 702>; 2218 status = "disabled"; 2219 }; 2220 2221 usb2_phy0: usb-phy@ee080200 { 2222 compatible = "renesas,usb2-phy-r8a774e1", 2223 "renesas,rcar-gen3-usb2-phy"; 2224 reg = <0 0xee080200 0 0x700>; 2225 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2226 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2227 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2228 resets = <&cpg 703>, <&cpg 704>; 2229 #phy-cells = <1>; 2230 status = "disabled"; 2231 }; 2232 2233 usb2_phy1: usb-phy@ee0a0200 { 2234 compatible = "renesas,usb2-phy-r8a774e1", 2235 "renesas,rcar-gen3-usb2-phy"; 2236 reg = <0 0xee0a0200 0 0x700>; 2237 clocks = <&cpg CPG_MOD 702>; 2238 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2239 resets = <&cpg 702>; 2240 #phy-cells = <1>; 2241 status = "disabled"; 2242 }; 2243 2244 sdhi0: mmc@ee100000 { 2245 compatible = "renesas,sdhi-r8a774e1", 2246 "renesas,rcar-gen3-sdhi"; 2247 reg = <0 0xee100000 0 0x2000>; 2248 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 2249 clocks = <&cpg CPG_MOD 314>; 2250 max-frequency = <200000000>; 2251 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2252 resets = <&cpg 314>; 2253 iommus = <&ipmmu_ds1 32>; 2254 status = "disabled"; 2255 }; 2256 2257 sdhi1: mmc@ee120000 { 2258 compatible = "renesas,sdhi-r8a774e1", 2259 "renesas,rcar-gen3-sdhi"; 2260 reg = <0 0xee120000 0 0x2000>; 2261 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 2262 clocks = <&cpg CPG_MOD 313>; 2263 max-frequency = <200000000>; 2264 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2265 resets = <&cpg 313>; 2266 iommus = <&ipmmu_ds1 33>; 2267 status = "disabled"; 2268 }; 2269 2270 sdhi2: mmc@ee140000 { 2271 compatible = "renesas,sdhi-r8a774e1", 2272 "renesas,rcar-gen3-sdhi"; 2273 reg = <0 0xee140000 0 0x2000>; 2274 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 2275 clocks = <&cpg CPG_MOD 312>; 2276 max-frequency = <200000000>; 2277 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2278 resets = <&cpg 312>; 2279 iommus = <&ipmmu_ds1 34>; 2280 status = "disabled"; 2281 }; 2282 2283 sdhi3: mmc@ee160000 { 2284 compatible = "renesas,sdhi-r8a774e1", 2285 "renesas,rcar-gen3-sdhi"; 2286 reg = <0 0xee160000 0 0x2000>; 2287 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 2288 clocks = <&cpg CPG_MOD 311>; 2289 max-frequency = <200000000>; 2290 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2291 resets = <&cpg 311>; 2292 iommus = <&ipmmu_ds1 35>; 2293 status = "disabled"; 2294 }; 2295 2296 sata: sata@ee300000 { 2297 compatible = "renesas,sata-r8a774e1", 2298 "renesas,rcar-gen3-sata"; 2299 reg = <0 0xee300000 0 0x200000>; 2300 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2301 clocks = <&cpg CPG_MOD 815>; 2302 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2303 resets = <&cpg 815>; 2304 iommus = <&ipmmu_hc 2>; 2305 status = "disabled"; 2306 }; 2307 2308 gic: interrupt-controller@f1010000 { 2309 compatible = "arm,gic-400"; 2310 #interrupt-cells = <3>; 2311 #address-cells = <0>; 2312 interrupt-controller; 2313 reg = <0x0 0xf1010000 0 0x1000>, 2314 <0x0 0xf1020000 0 0x20000>, 2315 <0x0 0xf1040000 0 0x20000>, 2316 <0x0 0xf1060000 0 0x20000>; 2317 interrupts = <GIC_PPI 9 2318 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2319 clocks = <&cpg CPG_MOD 408>; 2320 clock-names = "clk"; 2321 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2322 resets = <&cpg 408>; 2323 }; 2324 2325 pciec0: pcie@fe000000 { 2326 compatible = "renesas,pcie-r8a774e1", 2327 "renesas,pcie-rcar-gen3"; 2328 reg = <0 0xfe000000 0 0x80000>; 2329 #address-cells = <3>; 2330 #size-cells = <2>; 2331 bus-range = <0x00 0xff>; 2332 device_type = "pci"; 2333 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 2334 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 2335 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 2336 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 2337 /* Map all possible DDR as inbound ranges */ 2338 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2339 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2340 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2341 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2342 #interrupt-cells = <1>; 2343 interrupt-map-mask = <0 0 0 0>; 2344 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2345 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 2346 clock-names = "pcie", "pcie_bus"; 2347 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2348 resets = <&cpg 319>; 2349 status = "disabled"; 2350 }; 2351 2352 pciec1: pcie@ee800000 { 2353 compatible = "renesas,pcie-r8a774e1", 2354 "renesas,pcie-rcar-gen3"; 2355 reg = <0 0xee800000 0 0x80000>; 2356 #address-cells = <3>; 2357 #size-cells = <2>; 2358 bus-range = <0x00 0xff>; 2359 device_type = "pci"; 2360 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, 2361 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, 2362 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, 2363 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 2364 /* Map all possible DDR as inbound ranges */ 2365 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2366 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2367 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2368 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2369 #interrupt-cells = <1>; 2370 interrupt-map-mask = <0 0 0 0>; 2371 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2372 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 2373 clock-names = "pcie", "pcie_bus"; 2374 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2375 resets = <&cpg 318>; 2376 status = "disabled"; 2377 }; 2378 2379 csi20: csi2@fea80000 { 2380 compatible = "renesas,r8a774e1-csi2"; 2381 reg = <0 0xfea80000 0 0x10000>; 2382 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2383 clocks = <&cpg CPG_MOD 714>; 2384 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2385 resets = <&cpg 714>; 2386 status = "disabled"; 2387 2388 ports { 2389 #address-cells = <1>; 2390 #size-cells = <0>; 2391 2392 port@1 { 2393 #address-cells = <1>; 2394 #size-cells = <0>; 2395 2396 reg = <1>; 2397 2398 csi20vin0: endpoint@0 { 2399 reg = <0>; 2400 remote-endpoint = <&vin0csi20>; 2401 }; 2402 csi20vin1: endpoint@1 { 2403 reg = <1>; 2404 remote-endpoint = <&vin1csi20>; 2405 }; 2406 csi20vin2: endpoint@2 { 2407 reg = <2>; 2408 remote-endpoint = <&vin2csi20>; 2409 }; 2410 csi20vin3: endpoint@3 { 2411 reg = <3>; 2412 remote-endpoint = <&vin3csi20>; 2413 }; 2414 csi20vin4: endpoint@4 { 2415 reg = <4>; 2416 remote-endpoint = <&vin4csi20>; 2417 }; 2418 csi20vin5: endpoint@5 { 2419 reg = <5>; 2420 remote-endpoint = <&vin5csi20>; 2421 }; 2422 csi20vin6: endpoint@6 { 2423 reg = <6>; 2424 remote-endpoint = <&vin6csi20>; 2425 }; 2426 csi20vin7: endpoint@7 { 2427 reg = <7>; 2428 remote-endpoint = <&vin7csi20>; 2429 }; 2430 }; 2431 }; 2432 }; 2433 2434 csi40: csi2@feaa0000 { 2435 compatible = "renesas,r8a774e1-csi2"; 2436 reg = <0 0xfeaa0000 0 0x10000>; 2437 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2438 clocks = <&cpg CPG_MOD 716>; 2439 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2440 resets = <&cpg 716>; 2441 status = "disabled"; 2442 2443 ports { 2444 #address-cells = <1>; 2445 #size-cells = <0>; 2446 2447 port@1 { 2448 #address-cells = <1>; 2449 #size-cells = <0>; 2450 2451 reg = <1>; 2452 2453 csi40vin0: endpoint@0 { 2454 reg = <0>; 2455 remote-endpoint = <&vin0csi40>; 2456 }; 2457 csi40vin1: endpoint@1 { 2458 reg = <1>; 2459 remote-endpoint = <&vin1csi40>; 2460 }; 2461 csi40vin2: endpoint@2 { 2462 reg = <2>; 2463 remote-endpoint = <&vin2csi40>; 2464 }; 2465 csi40vin3: endpoint@3 { 2466 reg = <3>; 2467 remote-endpoint = <&vin3csi40>; 2468 }; 2469 }; 2470 }; 2471 }; 2472 2473 hdmi0: hdmi@fead0000 { 2474 reg = <0 0xfead0000 0 0x10000>; 2475 status = "disabled"; 2476 2477 /* placeholder */ 2478 2479 ports { 2480 #address-cells = <1>; 2481 #size-cells = <0>; 2482 2483 port@0 { 2484 reg = <0>; 2485 }; 2486 port@1 { 2487 reg = <1>; 2488 }; 2489 port@2 { 2490 reg = <2>; 2491 }; 2492 }; 2493 }; 2494 2495 du: display@feb00000 { 2496 reg = <0 0xfeb00000 0 0x80000>; 2497 status = "disabled"; 2498 2499 /* placeholder */ 2500 ports { 2501 #address-cells = <1>; 2502 #size-cells = <0>; 2503 2504 port@0 { 2505 reg = <0>; 2506 }; 2507 port@1 { 2508 reg = <1>; 2509 }; 2510 port@2 { 2511 reg = <2>; 2512 }; 2513 }; 2514 }; 2515 2516 prr: chipid@fff00044 { 2517 compatible = "renesas,prr"; 2518 reg = <0 0xfff00044 0 4>; 2519 }; 2520 }; 2521 2522 thermal-zones { 2523 sensor_thermal1: sensor-thermal1 { 2524 polling-delay-passive = <250>; 2525 polling-delay = <1000>; 2526 thermal-sensors = <&tsc 0>; 2527 sustainable-power = <6313>; 2528 2529 trips { 2530 sensor1_crit: sensor1-crit { 2531 temperature = <120000>; 2532 hysteresis = <1000>; 2533 type = "critical"; 2534 }; 2535 }; 2536 }; 2537 2538 sensor_thermal2: sensor-thermal2 { 2539 polling-delay-passive = <250>; 2540 polling-delay = <1000>; 2541 thermal-sensors = <&tsc 1>; 2542 sustainable-power = <6313>; 2543 2544 trips { 2545 sensor2_crit: sensor2-crit { 2546 temperature = <120000>; 2547 hysteresis = <1000>; 2548 type = "critical"; 2549 }; 2550 }; 2551 }; 2552 2553 sensor_thermal3: sensor-thermal3 { 2554 polling-delay-passive = <250>; 2555 polling-delay = <1000>; 2556 thermal-sensors = <&tsc 2>; 2557 sustainable-power = <6313>; 2558 2559 trips { 2560 target: trip-point1 { 2561 temperature = <100000>; 2562 hysteresis = <1000>; 2563 type = "passive"; 2564 }; 2565 2566 sensor3_crit: sensor3-crit { 2567 temperature = <120000>; 2568 hysteresis = <1000>; 2569 type = "critical"; 2570 }; 2571 }; 2572 2573 cooling-maps { 2574 map0 { 2575 trip = <&target>; 2576 cooling-device = <&a57_0 0 2>; 2577 contribution = <1024>; 2578 }; 2579 2580 map1 { 2581 trip = <&target>; 2582 cooling-device = <&a53_0 0 2>; 2583 contribution = <1024>; 2584 }; 2585 }; 2586 }; 2587 }; 2588 2589 timer { 2590 compatible = "arm,armv8-timer"; 2591 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2592 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2593 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2594 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2595 }; 2596 2597 /* External USB clocks - can be overridden by the board */ 2598 usb3s0_clk: usb3s0 { 2599 compatible = "fixed-clock"; 2600 #clock-cells = <0>; 2601 clock-frequency = <0>; 2602 }; 2603 2604 usb_extal_clk: usb_extal { 2605 compatible = "fixed-clock"; 2606 #clock-cells = <0>; 2607 clock-frequency = <0>; 2608 }; 2609}; 2610