1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774e1 SoC 4 * 5 * Copyright (C) 2020 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r8a774e1-cpg-mssr.h> 11#include <dt-bindings/power/r8a774e1-sysc.h> 12 13#define CPG_AUDIO_CLK_I R8A774E1_CLK_S0D4 14 15/ { 16 compatible = "renesas,r8a774e1"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 /* 21 * The external audio clocks are configured as 0 Hz fixed frequency 22 * clocks by default. 23 * Boards that provide audio clocks should override them. 24 */ 25 audio_clk_a: audio_clk_a { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <0>; 29 }; 30 31 audio_clk_c: audio_clk_c { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 cluster0_opp: opp_table0 { 38 compatible = "operating-points-v2"; 39 opp-shared; 40 41 opp-500000000 { 42 opp-hz = /bits/ 64 <500000000>; 43 opp-microvolt = <820000>; 44 clock-latency-ns = <300000>; 45 }; 46 opp-1000000000 { 47 opp-hz = /bits/ 64 <1000000000>; 48 opp-microvolt = <820000>; 49 clock-latency-ns = <300000>; 50 }; 51 opp-1500000000 { 52 opp-hz = /bits/ 64 <1500000000>; 53 opp-microvolt = <820000>; 54 clock-latency-ns = <300000>; 55 opp-suspend; 56 }; 57 }; 58 59 cluster1_opp: opp_table1 { 60 compatible = "operating-points-v2"; 61 opp-shared; 62 63 opp-800000000 { 64 opp-hz = /bits/ 64 <800000000>; 65 opp-microvolt = <820000>; 66 clock-latency-ns = <300000>; 67 }; 68 opp-1000000000 { 69 opp-hz = /bits/ 64 <1000000000>; 70 opp-microvolt = <820000>; 71 clock-latency-ns = <300000>; 72 }; 73 opp-1200000000 { 74 opp-hz = /bits/ 64 <1200000000>; 75 opp-microvolt = <820000>; 76 clock-latency-ns = <300000>; 77 }; 78 }; 79 80 cpus { 81 #address-cells = <1>; 82 #size-cells = <0>; 83 84 cpu-map { 85 cluster0 { 86 core0 { 87 cpu = <&a57_0>; 88 }; 89 core1 { 90 cpu = <&a57_1>; 91 }; 92 core2 { 93 cpu = <&a57_2>; 94 }; 95 core3 { 96 cpu = <&a57_3>; 97 }; 98 }; 99 100 cluster1 { 101 core0 { 102 cpu = <&a53_0>; 103 }; 104 core1 { 105 cpu = <&a53_1>; 106 }; 107 core2 { 108 cpu = <&a53_2>; 109 }; 110 core3 { 111 cpu = <&a53_3>; 112 }; 113 }; 114 }; 115 116 a57_0: cpu@0 { 117 compatible = "arm,cortex-a57"; 118 reg = <0x0>; 119 device_type = "cpu"; 120 power-domains = <&sysc R8A774E1_PD_CA57_CPU0>; 121 next-level-cache = <&L2_CA57>; 122 enable-method = "psci"; 123 dynamic-power-coefficient = <854>; 124 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 125 operating-points-v2 = <&cluster0_opp>; 126 capacity-dmips-mhz = <1024>; 127 #cooling-cells = <2>; 128 }; 129 130 a57_1: cpu@1 { 131 compatible = "arm,cortex-a57"; 132 reg = <0x1>; 133 device_type = "cpu"; 134 power-domains = <&sysc R8A774E1_PD_CA57_CPU1>; 135 next-level-cache = <&L2_CA57>; 136 enable-method = "psci"; 137 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 138 operating-points-v2 = <&cluster0_opp>; 139 capacity-dmips-mhz = <1024>; 140 #cooling-cells = <2>; 141 }; 142 143 a57_2: cpu@2 { 144 compatible = "arm,cortex-a57"; 145 reg = <0x2>; 146 device_type = "cpu"; 147 power-domains = <&sysc R8A774E1_PD_CA57_CPU2>; 148 next-level-cache = <&L2_CA57>; 149 enable-method = "psci"; 150 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 151 operating-points-v2 = <&cluster0_opp>; 152 capacity-dmips-mhz = <1024>; 153 #cooling-cells = <2>; 154 }; 155 156 a57_3: cpu@3 { 157 compatible = "arm,cortex-a57"; 158 reg = <0x3>; 159 device_type = "cpu"; 160 power-domains = <&sysc R8A774E1_PD_CA57_CPU3>; 161 next-level-cache = <&L2_CA57>; 162 enable-method = "psci"; 163 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 164 operating-points-v2 = <&cluster0_opp>; 165 capacity-dmips-mhz = <1024>; 166 #cooling-cells = <2>; 167 }; 168 169 a53_0: cpu@100 { 170 compatible = "arm,cortex-a53"; 171 reg = <0x100>; 172 device_type = "cpu"; 173 power-domains = <&sysc R8A774E1_PD_CA53_CPU0>; 174 next-level-cache = <&L2_CA53>; 175 enable-method = "psci"; 176 #cooling-cells = <2>; 177 dynamic-power-coefficient = <277>; 178 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 179 operating-points-v2 = <&cluster1_opp>; 180 capacity-dmips-mhz = <535>; 181 }; 182 183 a53_1: cpu@101 { 184 compatible = "arm,cortex-a53"; 185 reg = <0x101>; 186 device_type = "cpu"; 187 power-domains = <&sysc R8A774E1_PD_CA53_CPU1>; 188 next-level-cache = <&L2_CA53>; 189 enable-method = "psci"; 190 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 191 operating-points-v2 = <&cluster1_opp>; 192 capacity-dmips-mhz = <535>; 193 }; 194 195 a53_2: cpu@102 { 196 compatible = "arm,cortex-a53"; 197 reg = <0x102>; 198 device_type = "cpu"; 199 power-domains = <&sysc R8A774E1_PD_CA53_CPU2>; 200 next-level-cache = <&L2_CA53>; 201 enable-method = "psci"; 202 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 203 operating-points-v2 = <&cluster1_opp>; 204 capacity-dmips-mhz = <535>; 205 }; 206 207 a53_3: cpu@103 { 208 compatible = "arm,cortex-a53"; 209 reg = <0x103>; 210 device_type = "cpu"; 211 power-domains = <&sysc R8A774E1_PD_CA53_CPU3>; 212 next-level-cache = <&L2_CA53>; 213 enable-method = "psci"; 214 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 215 operating-points-v2 = <&cluster1_opp>; 216 capacity-dmips-mhz = <535>; 217 }; 218 219 L2_CA57: cache-controller-0 { 220 compatible = "cache"; 221 power-domains = <&sysc R8A774E1_PD_CA57_SCU>; 222 cache-unified; 223 cache-level = <2>; 224 }; 225 226 L2_CA53: cache-controller-1 { 227 compatible = "cache"; 228 power-domains = <&sysc R8A774E1_PD_CA53_SCU>; 229 cache-unified; 230 cache-level = <2>; 231 }; 232 }; 233 234 extal_clk: extal { 235 compatible = "fixed-clock"; 236 #clock-cells = <0>; 237 /* This value must be overridden by the board */ 238 clock-frequency = <0>; 239 }; 240 241 extalr_clk: extalr { 242 compatible = "fixed-clock"; 243 #clock-cells = <0>; 244 /* This value must be overridden by the board */ 245 clock-frequency = <0>; 246 }; 247 248 /* External PCIe clock - can be overridden by the board */ 249 pcie_bus_clk: pcie_bus { 250 compatible = "fixed-clock"; 251 #clock-cells = <0>; 252 clock-frequency = <0>; 253 }; 254 255 pmu_a53 { 256 compatible = "arm,cortex-a53-pmu"; 257 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 258 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 259 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 260 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 261 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 262 }; 263 264 pmu_a57 { 265 compatible = "arm,cortex-a57-pmu"; 266 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 267 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 268 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 269 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 270 interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>; 271 }; 272 273 psci { 274 compatible = "arm,psci-1.0", "arm,psci-0.2"; 275 method = "smc"; 276 }; 277 278 /* External SCIF clock - to be overridden by boards that provide it */ 279 scif_clk: scif { 280 compatible = "fixed-clock"; 281 #clock-cells = <0>; 282 clock-frequency = <0>; 283 }; 284 285 soc { 286 compatible = "simple-bus"; 287 interrupt-parent = <&gic>; 288 #address-cells = <2>; 289 #size-cells = <2>; 290 ranges; 291 292 rwdt: watchdog@e6020000 { 293 reg = <0 0xe6020000 0 0x0c>; 294 status = "disabled"; 295 296 /* placeholder */ 297 }; 298 299 gpio0: gpio@e6050000 { 300 compatible = "renesas,gpio-r8a774e1", 301 "renesas,rcar-gen3-gpio"; 302 reg = <0 0xe6050000 0 0x50>; 303 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 304 #gpio-cells = <2>; 305 gpio-controller; 306 gpio-ranges = <&pfc 0 0 16>; 307 #interrupt-cells = <2>; 308 interrupt-controller; 309 clocks = <&cpg CPG_MOD 912>; 310 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 311 resets = <&cpg 912>; 312 }; 313 314 gpio1: gpio@e6051000 { 315 compatible = "renesas,gpio-r8a774e1", 316 "renesas,rcar-gen3-gpio"; 317 reg = <0 0xe6051000 0 0x50>; 318 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 319 #gpio-cells = <2>; 320 gpio-controller; 321 gpio-ranges = <&pfc 0 32 29>; 322 #interrupt-cells = <2>; 323 interrupt-controller; 324 clocks = <&cpg CPG_MOD 911>; 325 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 326 resets = <&cpg 911>; 327 }; 328 329 gpio2: gpio@e6052000 { 330 compatible = "renesas,gpio-r8a774e1", 331 "renesas,rcar-gen3-gpio"; 332 reg = <0 0xe6052000 0 0x50>; 333 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 334 #gpio-cells = <2>; 335 gpio-controller; 336 gpio-ranges = <&pfc 0 64 15>; 337 #interrupt-cells = <2>; 338 interrupt-controller; 339 clocks = <&cpg CPG_MOD 910>; 340 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 341 resets = <&cpg 910>; 342 }; 343 344 gpio3: gpio@e6053000 { 345 compatible = "renesas,gpio-r8a774e1", 346 "renesas,rcar-gen3-gpio"; 347 reg = <0 0xe6053000 0 0x50>; 348 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 349 #gpio-cells = <2>; 350 gpio-controller; 351 gpio-ranges = <&pfc 0 96 16>; 352 #interrupt-cells = <2>; 353 interrupt-controller; 354 clocks = <&cpg CPG_MOD 909>; 355 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 356 resets = <&cpg 909>; 357 }; 358 359 gpio4: gpio@e6054000 { 360 compatible = "renesas,gpio-r8a774e1", 361 "renesas,rcar-gen3-gpio"; 362 reg = <0 0xe6054000 0 0x50>; 363 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 364 #gpio-cells = <2>; 365 gpio-controller; 366 gpio-ranges = <&pfc 0 128 18>; 367 #interrupt-cells = <2>; 368 interrupt-controller; 369 clocks = <&cpg CPG_MOD 908>; 370 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 371 resets = <&cpg 908>; 372 }; 373 374 gpio5: gpio@e6055000 { 375 compatible = "renesas,gpio-r8a774e1", 376 "renesas,rcar-gen3-gpio"; 377 reg = <0 0xe6055000 0 0x50>; 378 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 379 #gpio-cells = <2>; 380 gpio-controller; 381 gpio-ranges = <&pfc 0 160 26>; 382 #interrupt-cells = <2>; 383 interrupt-controller; 384 clocks = <&cpg CPG_MOD 907>; 385 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 386 resets = <&cpg 907>; 387 }; 388 389 gpio6: gpio@e6055400 { 390 compatible = "renesas,gpio-r8a774e1", 391 "renesas,rcar-gen3-gpio"; 392 reg = <0 0xe6055400 0 0x50>; 393 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 394 #gpio-cells = <2>; 395 gpio-controller; 396 gpio-ranges = <&pfc 0 192 32>; 397 #interrupt-cells = <2>; 398 interrupt-controller; 399 clocks = <&cpg CPG_MOD 906>; 400 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 401 resets = <&cpg 906>; 402 }; 403 404 gpio7: gpio@e6055800 { 405 compatible = "renesas,gpio-r8a774e1", 406 "renesas,rcar-gen3-gpio"; 407 reg = <0 0xe6055800 0 0x50>; 408 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 409 #gpio-cells = <2>; 410 gpio-controller; 411 gpio-ranges = <&pfc 0 224 4>; 412 #interrupt-cells = <2>; 413 interrupt-controller; 414 clocks = <&cpg CPG_MOD 905>; 415 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 416 resets = <&cpg 905>; 417 }; 418 419 pfc: pin-controller@e6060000 { 420 compatible = "renesas,pfc-r8a774e1"; 421 reg = <0 0xe6060000 0 0x50c>; 422 }; 423 424 cmt0: timer@e60f0000 { 425 compatible = "renesas,r8a774e1-cmt0", 426 "renesas,rcar-gen3-cmt0"; 427 reg = <0 0xe60f0000 0 0x1004>; 428 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&cpg CPG_MOD 303>; 431 clock-names = "fck"; 432 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 433 resets = <&cpg 303>; 434 status = "disabled"; 435 }; 436 437 cmt1: timer@e6130000 { 438 compatible = "renesas,r8a774e1-cmt1", 439 "renesas,rcar-gen3-cmt1"; 440 reg = <0 0xe6130000 0 0x1004>; 441 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&cpg CPG_MOD 302>; 450 clock-names = "fck"; 451 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 452 resets = <&cpg 302>; 453 status = "disabled"; 454 }; 455 456 cmt2: timer@e6140000 { 457 compatible = "renesas,r8a774e1-cmt1", 458 "renesas,rcar-gen3-cmt1"; 459 reg = <0 0xe6140000 0 0x1004>; 460 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 468 clocks = <&cpg CPG_MOD 301>; 469 clock-names = "fck"; 470 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 471 resets = <&cpg 301>; 472 status = "disabled"; 473 }; 474 475 cmt3: timer@e6148000 { 476 compatible = "renesas,r8a774e1-cmt1", 477 "renesas,rcar-gen3-cmt1"; 478 reg = <0 0xe6148000 0 0x1004>; 479 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&cpg CPG_MOD 300>; 488 clock-names = "fck"; 489 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 490 resets = <&cpg 300>; 491 status = "disabled"; 492 }; 493 494 cpg: clock-controller@e6150000 { 495 compatible = "renesas,r8a774e1-cpg-mssr"; 496 reg = <0 0xe6150000 0 0x1000>; 497 clocks = <&extal_clk>, <&extalr_clk>; 498 clock-names = "extal", "extalr"; 499 #clock-cells = <2>; 500 #power-domain-cells = <0>; 501 #reset-cells = <1>; 502 }; 503 504 rst: reset-controller@e6160000 { 505 compatible = "renesas,r8a774e1-rst"; 506 reg = <0 0xe6160000 0 0x0200>; 507 }; 508 509 sysc: system-controller@e6180000 { 510 compatible = "renesas,r8a774e1-sysc"; 511 reg = <0 0xe6180000 0 0x0400>; 512 #power-domain-cells = <1>; 513 }; 514 515 tsc: thermal@e6198000 { 516 compatible = "renesas,r8a774e1-thermal"; 517 reg = <0 0xe6198000 0 0x100>, 518 <0 0xe61a0000 0 0x100>, 519 <0 0xe61a8000 0 0x100>; 520 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&cpg CPG_MOD 522>; 524 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 525 resets = <&cpg 522>; 526 #thermal-sensor-cells = <1>; 527 }; 528 529 intc_ex: interrupt-controller@e61c0000 { 530 compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc"; 531 #interrupt-cells = <2>; 532 interrupt-controller; 533 reg = <0 0xe61c0000 0 0x200>; 534 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&cpg CPG_MOD 407>; 541 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 542 resets = <&cpg 407>; 543 }; 544 545 i2c2: i2c@e6510000 { 546 reg = <0 0xe6510000 0 0x40>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 status = "disabled"; 550 551 /* placeholder */ 552 }; 553 554 i2c4: i2c@e66d8000 { 555 #address-cells = <1>; 556 #size-cells = <0>; 557 reg = <0 0xe66d8000 0 0x40>; 558 status = "disabled"; 559 560 /* placeholder */ 561 }; 562 563 hscif0: serial@e6540000 { 564 reg = <0 0xe6540000 0 0x60>; 565 status = "disabled"; 566 567 /* placeholder */ 568 }; 569 570 hsusb: usb@e6590000 { 571 reg = <0 0xe6590000 0 0x200>; 572 status = "disabled"; 573 574 /* placeholder */ 575 }; 576 577 usb3_phy0: usb-phy@e65ee000 { 578 reg = <0 0xe65ee000 0 0x90>; 579 #phy-cells = <0>; 580 status = "disabled"; 581 582 /* placeholder */ 583 }; 584 585 dmac0: dma-controller@e6700000 { 586 compatible = "renesas,dmac-r8a774e1", 587 "renesas,rcar-dmac"; 588 reg = <0 0xe6700000 0 0x10000>; 589 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 606 interrupt-names = "error", 607 "ch0", "ch1", "ch2", "ch3", 608 "ch4", "ch5", "ch6", "ch7", 609 "ch8", "ch9", "ch10", "ch11", 610 "ch12", "ch13", "ch14", "ch15"; 611 clocks = <&cpg CPG_MOD 219>; 612 clock-names = "fck"; 613 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 614 resets = <&cpg 219>; 615 #dma-cells = <1>; 616 dma-channels = <16>; 617 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 618 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 619 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 620 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 621 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 622 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 623 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 624 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 625 }; 626 627 dmac1: dma-controller@e7300000 { 628 compatible = "renesas,dmac-r8a774e1", 629 "renesas,rcar-dmac"; 630 reg = <0 0xe7300000 0 0x10000>; 631 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 648 interrupt-names = "error", 649 "ch0", "ch1", "ch2", "ch3", 650 "ch4", "ch5", "ch6", "ch7", 651 "ch8", "ch9", "ch10", "ch11", 652 "ch12", "ch13", "ch14", "ch15"; 653 clocks = <&cpg CPG_MOD 218>; 654 clock-names = "fck"; 655 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 656 resets = <&cpg 218>; 657 #dma-cells = <1>; 658 dma-channels = <16>; 659 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 660 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 661 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 662 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 663 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 664 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 665 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 666 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 667 }; 668 669 dmac2: dma-controller@e7310000 { 670 compatible = "renesas,dmac-r8a774e1", 671 "renesas,rcar-dmac"; 672 reg = <0 0xe7310000 0 0x10000>; 673 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 690 interrupt-names = "error", 691 "ch0", "ch1", "ch2", "ch3", 692 "ch4", "ch5", "ch6", "ch7", 693 "ch8", "ch9", "ch10", "ch11", 694 "ch12", "ch13", "ch14", "ch15"; 695 clocks = <&cpg CPG_MOD 217>; 696 clock-names = "fck"; 697 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 698 resets = <&cpg 217>; 699 #dma-cells = <1>; 700 dma-channels = <16>; 701 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 702 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 703 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 704 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 705 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 706 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 707 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 708 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 709 }; 710 711 ipmmu_ds0: iommu@e6740000 { 712 compatible = "renesas,ipmmu-r8a774e1"; 713 reg = <0 0xe6740000 0 0x1000>; 714 renesas,ipmmu-main = <&ipmmu_mm 0>; 715 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 716 #iommu-cells = <1>; 717 }; 718 719 ipmmu_ds1: iommu@e7740000 { 720 compatible = "renesas,ipmmu-r8a774e1"; 721 reg = <0 0xe7740000 0 0x1000>; 722 renesas,ipmmu-main = <&ipmmu_mm 1>; 723 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 724 #iommu-cells = <1>; 725 }; 726 727 ipmmu_hc: iommu@e6570000 { 728 compatible = "renesas,ipmmu-r8a774e1"; 729 reg = <0 0xe6570000 0 0x1000>; 730 renesas,ipmmu-main = <&ipmmu_mm 2>; 731 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 732 #iommu-cells = <1>; 733 }; 734 735 ipmmu_mm: iommu@e67b0000 { 736 compatible = "renesas,ipmmu-r8a774e1"; 737 reg = <0 0xe67b0000 0 0x1000>; 738 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 740 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 741 #iommu-cells = <1>; 742 }; 743 744 ipmmu_mp0: iommu@ec670000 { 745 compatible = "renesas,ipmmu-r8a774e1"; 746 reg = <0 0xec670000 0 0x1000>; 747 renesas,ipmmu-main = <&ipmmu_mm 4>; 748 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 749 #iommu-cells = <1>; 750 }; 751 752 ipmmu_pv0: iommu@fd800000 { 753 compatible = "renesas,ipmmu-r8a774e1"; 754 reg = <0 0xfd800000 0 0x1000>; 755 renesas,ipmmu-main = <&ipmmu_mm 6>; 756 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 757 #iommu-cells = <1>; 758 }; 759 760 ipmmu_pv1: iommu@fd950000 { 761 compatible = "renesas,ipmmu-r8a774e1"; 762 reg = <0 0xfd950000 0 0x1000>; 763 renesas,ipmmu-main = <&ipmmu_mm 7>; 764 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 765 #iommu-cells = <1>; 766 }; 767 768 ipmmu_pv2: iommu@fd960000 { 769 compatible = "renesas,ipmmu-r8a774e1"; 770 reg = <0 0xfd960000 0 0x1000>; 771 renesas,ipmmu-main = <&ipmmu_mm 8>; 772 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 773 #iommu-cells = <1>; 774 }; 775 776 ipmmu_pv3: iommu@fd970000 { 777 compatible = "renesas,ipmmu-r8a774e1"; 778 reg = <0 0xfd970000 0 0x1000>; 779 renesas,ipmmu-main = <&ipmmu_mm 9>; 780 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 781 #iommu-cells = <1>; 782 }; 783 784 ipmmu_vc0: iommu@fe6b0000 { 785 compatible = "renesas,ipmmu-r8a774e1"; 786 reg = <0 0xfe6b0000 0 0x1000>; 787 renesas,ipmmu-main = <&ipmmu_mm 12>; 788 power-domains = <&sysc R8A774E1_PD_A3VC>; 789 #iommu-cells = <1>; 790 }; 791 792 ipmmu_vc1: iommu@fe6f0000 { 793 compatible = "renesas,ipmmu-r8a774e1"; 794 reg = <0 0xfe6f0000 0 0x1000>; 795 renesas,ipmmu-main = <&ipmmu_mm 13>; 796 power-domains = <&sysc R8A774E1_PD_A3VC>; 797 #iommu-cells = <1>; 798 }; 799 800 ipmmu_vi0: iommu@febd0000 { 801 compatible = "renesas,ipmmu-r8a774e1"; 802 reg = <0 0xfebd0000 0 0x1000>; 803 renesas,ipmmu-main = <&ipmmu_mm 14>; 804 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 805 #iommu-cells = <1>; 806 }; 807 808 ipmmu_vi1: iommu@febe0000 { 809 compatible = "renesas,ipmmu-r8a774e1"; 810 reg = <0 0xfebe0000 0 0x1000>; 811 renesas,ipmmu-main = <&ipmmu_mm 15>; 812 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 813 #iommu-cells = <1>; 814 }; 815 816 ipmmu_vp0: iommu@fe990000 { 817 compatible = "renesas,ipmmu-r8a774e1"; 818 reg = <0 0xfe990000 0 0x1000>; 819 renesas,ipmmu-main = <&ipmmu_mm 16>; 820 power-domains = <&sysc R8A774E1_PD_A3VP>; 821 #iommu-cells = <1>; 822 }; 823 824 ipmmu_vp1: iommu@fe980000 { 825 compatible = "renesas,ipmmu-r8a774e1"; 826 reg = <0 0xfe980000 0 0x1000>; 827 renesas,ipmmu-main = <&ipmmu_mm 17>; 828 power-domains = <&sysc R8A774E1_PD_A3VP>; 829 #iommu-cells = <1>; 830 }; 831 832 avb: ethernet@e6800000 { 833 compatible = "renesas,etheravb-r8a774e1", 834 "renesas,etheravb-rcar-gen3"; 835 reg = <0 0xe6800000 0 0x800>; 836 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 846 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 847 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 848 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 849 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 850 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 851 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 852 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 853 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 855 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 861 interrupt-names = "ch0", "ch1", "ch2", "ch3", 862 "ch4", "ch5", "ch6", "ch7", 863 "ch8", "ch9", "ch10", "ch11", 864 "ch12", "ch13", "ch14", "ch15", 865 "ch16", "ch17", "ch18", "ch19", 866 "ch20", "ch21", "ch22", "ch23", 867 "ch24"; 868 clocks = <&cpg CPG_MOD 812>; 869 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 870 resets = <&cpg 812>; 871 phy-mode = "rgmii"; 872 iommus = <&ipmmu_ds0 16>; 873 #address-cells = <1>; 874 #size-cells = <0>; 875 status = "disabled"; 876 }; 877 878 can0: can@e6c30000 { 879 reg = <0 0xe6c30000 0 0x1000>; 880 status = "disabled"; 881 882 /* placeholder */ 883 }; 884 885 can1: can@e6c38000 { 886 reg = <0 0xe6c38000 0 0x1000>; 887 status = "disabled"; 888 889 /* placeholder */ 890 }; 891 892 pwm0: pwm@e6e30000 { 893 reg = <0 0xe6e30000 0 0x8>; 894 #pwm-cells = <2>; 895 status = "disabled"; 896 897 /* placeholder */ 898 }; 899 900 scif2: serial@e6e88000 { 901 compatible = "renesas,scif-r8a774e1", 902 "renesas,rcar-gen3-scif", "renesas,scif"; 903 reg = <0 0xe6e88000 0 0x40>; 904 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 905 clocks = <&cpg CPG_MOD 310>, 906 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 907 <&scif_clk>; 908 clock-names = "fck", "brg_int", "scif_clk"; 909 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 910 resets = <&cpg 310>; 911 status = "disabled"; 912 }; 913 914 rcar_sound: sound@ec500000 { 915 reg = <0 0xec500000 0 0x1000>, /* SCU */ 916 <0 0xec5a0000 0 0x100>, /* ADG */ 917 <0 0xec540000 0 0x1000>, /* SSIU */ 918 <0 0xec541000 0 0x280>, /* SSI */ 919 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 920 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 921 922 status = "disabled"; 923 924 /* placeholder */ 925 926 rcar_sound,ssi { 927 ssi2: ssi-2 { 928 /* placeholder */ 929 }; 930 }; 931 }; 932 933 xhci0: usb@ee000000 { 934 reg = <0 0xee000000 0 0xc00>; 935 status = "disabled"; 936 937 /* placeholder */ 938 }; 939 940 usb3_peri0: usb@ee020000 { 941 reg = <0 0xee020000 0 0x400>; 942 status = "disabled"; 943 944 /* placeholder */ 945 }; 946 947 ohci0: usb@ee080000 { 948 reg = <0 0xee080000 0 0x100>; 949 status = "disabled"; 950 951 /* placeholder */ 952 }; 953 954 ohci1: usb@ee0a0000 { 955 reg = <0 0xee0a0000 0 0x100>; 956 status = "disabled"; 957 958 /* placeholder */ 959 }; 960 961 ehci0: usb@ee080100 { 962 reg = <0 0xee080100 0 0x100>; 963 status = "disabled"; 964 965 /* placeholder */ 966 }; 967 968 ehci1: usb@ee0a0100 { 969 reg = <0 0xee0a0100 0 0x100>; 970 status = "disabled"; 971 972 /* placeholder */ 973 }; 974 975 usb2_phy0: usb-phy@ee080200 { 976 reg = <0 0xee080200 0 0x700>; 977 status = "disabled"; 978 979 /* placeholder */ 980 }; 981 982 usb2_phy1: usb-phy@ee0a0200 { 983 reg = <0 0xee0a0200 0 0x700>; 984 status = "disabled"; 985 986 /* placeholder */ 987 }; 988 989 sdhi0: mmc@ee100000 { 990 reg = <0 0xee100000 0 0x2000>; 991 status = "disabled"; 992 993 /* placeholder */ 994 }; 995 996 sdhi2: mmc@ee140000 { 997 reg = <0 0xee140000 0 0x2000>; 998 status = "disabled"; 999 1000 /* placeholder */ 1001 }; 1002 1003 sdhi3: mmc@ee160000 { 1004 compatible = "renesas,sdhi-r8a774e1", 1005 "renesas,rcar-gen3-sdhi"; 1006 reg = <0 0xee160000 0 0x2000>; 1007 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1008 clocks = <&cpg CPG_MOD 311>; 1009 max-frequency = <200000000>; 1010 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1011 resets = <&cpg 311>; 1012 status = "disabled"; 1013 }; 1014 1015 gic: interrupt-controller@f1010000 { 1016 compatible = "arm,gic-400"; 1017 #interrupt-cells = <3>; 1018 #address-cells = <0>; 1019 interrupt-controller; 1020 reg = <0x0 0xf1010000 0 0x1000>, 1021 <0x0 0xf1020000 0 0x20000>, 1022 <0x0 0xf1040000 0 0x20000>, 1023 <0x0 0xf1060000 0 0x20000>; 1024 interrupts = <GIC_PPI 9 1025 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1026 clocks = <&cpg CPG_MOD 408>; 1027 clock-names = "clk"; 1028 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1029 resets = <&cpg 408>; 1030 }; 1031 1032 pciec0: pcie@fe000000 { 1033 reg = <0 0xfe000000 0 0x80000>; 1034 #address-cells = <3>; 1035 #size-cells = <2>; 1036 status = "disabled"; 1037 1038 /* placeholder */ 1039 }; 1040 1041 hdmi0: hdmi@fead0000 { 1042 reg = <0 0xfead0000 0 0x10000>; 1043 status = "disabled"; 1044 1045 /* placeholder */ 1046 1047 ports { 1048 #address-cells = <1>; 1049 #size-cells = <0>; 1050 1051 port@0 { 1052 reg = <0>; 1053 }; 1054 port@1 { 1055 reg = <1>; 1056 }; 1057 port@2 { 1058 reg = <2>; 1059 }; 1060 }; 1061 }; 1062 1063 du: display@feb00000 { 1064 reg = <0 0xfeb00000 0 0x80000>; 1065 status = "disabled"; 1066 1067 /* placeholder */ 1068 ports { 1069 #address-cells = <1>; 1070 #size-cells = <0>; 1071 1072 port@0 { 1073 reg = <0>; 1074 }; 1075 port@1 { 1076 reg = <1>; 1077 }; 1078 port@2 { 1079 reg = <2>; 1080 }; 1081 }; 1082 }; 1083 1084 prr: chipid@fff00044 { 1085 compatible = "renesas,prr"; 1086 reg = <0 0xfff00044 0 4>; 1087 }; 1088 }; 1089 1090 thermal-zones { 1091 sensor_thermal1: sensor-thermal1 { 1092 polling-delay-passive = <250>; 1093 polling-delay = <1000>; 1094 thermal-sensors = <&tsc 0>; 1095 sustainable-power = <6313>; 1096 1097 trips { 1098 sensor1_crit: sensor1-crit { 1099 temperature = <120000>; 1100 hysteresis = <1000>; 1101 type = "critical"; 1102 }; 1103 }; 1104 }; 1105 1106 sensor_thermal2: sensor-thermal2 { 1107 polling-delay-passive = <250>; 1108 polling-delay = <1000>; 1109 thermal-sensors = <&tsc 1>; 1110 sustainable-power = <6313>; 1111 1112 trips { 1113 sensor2_crit: sensor2-crit { 1114 temperature = <120000>; 1115 hysteresis = <1000>; 1116 type = "critical"; 1117 }; 1118 }; 1119 }; 1120 1121 sensor_thermal3: sensor-thermal3 { 1122 polling-delay-passive = <250>; 1123 polling-delay = <1000>; 1124 thermal-sensors = <&tsc 2>; 1125 sustainable-power = <6313>; 1126 1127 trips { 1128 target: trip-point1 { 1129 temperature = <100000>; 1130 hysteresis = <1000>; 1131 type = "passive"; 1132 }; 1133 1134 sensor3_crit: sensor3-crit { 1135 temperature = <120000>; 1136 hysteresis = <1000>; 1137 type = "critical"; 1138 }; 1139 }; 1140 1141 cooling-maps { 1142 map0 { 1143 trip = <&target>; 1144 cooling-device = <&a57_0 0 2>; 1145 contribution = <1024>; 1146 }; 1147 1148 map1 { 1149 trip = <&target>; 1150 cooling-device = <&a53_0 0 2>; 1151 contribution = <1024>; 1152 }; 1153 }; 1154 }; 1155 }; 1156 1157 timer { 1158 compatible = "arm,armv8-timer"; 1159 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1160 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1161 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1162 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1163 }; 1164 1165 /* External USB clocks - can be overridden by the board */ 1166 usb3s0_clk: usb3s0 { 1167 compatible = "fixed-clock"; 1168 #clock-cells = <0>; 1169 clock-frequency = <0>; 1170 }; 1171 1172 usb_extal_clk: usb_extal { 1173 compatible = "fixed-clock"; 1174 #clock-cells = <0>; 1175 clock-frequency = <0>; 1176 }; 1177}; 1178