1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774e1 SoC 4 * 5 * Copyright (C) 2020 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r8a774e1-cpg-mssr.h> 11#include <dt-bindings/power/r8a774e1-sysc.h> 12 13#define CPG_AUDIO_CLK_I R8A774E1_CLK_S0D4 14 15/ { 16 compatible = "renesas,r8a774e1"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 /* 21 * The external audio clocks are configured as 0 Hz fixed frequency 22 * clocks by default. 23 * Boards that provide audio clocks should override them. 24 */ 25 audio_clk_a: audio_clk_a { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <0>; 29 }; 30 31 audio_clk_b: audio_clk_b { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 audio_clk_c: audio_clk_c { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <0>; 41 }; 42 43 /* External CAN clock - to be overridden by boards that provide it */ 44 can_clk: can { 45 compatible = "fixed-clock"; 46 #clock-cells = <0>; 47 clock-frequency = <0>; 48 }; 49 50 cluster0_opp: opp_table0 { 51 compatible = "operating-points-v2"; 52 opp-shared; 53 54 opp-500000000 { 55 opp-hz = /bits/ 64 <500000000>; 56 opp-microvolt = <820000>; 57 clock-latency-ns = <300000>; 58 }; 59 opp-1000000000 { 60 opp-hz = /bits/ 64 <1000000000>; 61 opp-microvolt = <820000>; 62 clock-latency-ns = <300000>; 63 }; 64 opp-1500000000 { 65 opp-hz = /bits/ 64 <1500000000>; 66 opp-microvolt = <820000>; 67 clock-latency-ns = <300000>; 68 opp-suspend; 69 }; 70 }; 71 72 cluster1_opp: opp_table1 { 73 compatible = "operating-points-v2"; 74 opp-shared; 75 76 opp-800000000 { 77 opp-hz = /bits/ 64 <800000000>; 78 opp-microvolt = <820000>; 79 clock-latency-ns = <300000>; 80 }; 81 opp-1000000000 { 82 opp-hz = /bits/ 64 <1000000000>; 83 opp-microvolt = <820000>; 84 clock-latency-ns = <300000>; 85 }; 86 opp-1200000000 { 87 opp-hz = /bits/ 64 <1200000000>; 88 opp-microvolt = <820000>; 89 clock-latency-ns = <300000>; 90 }; 91 }; 92 93 cpus { 94 #address-cells = <1>; 95 #size-cells = <0>; 96 97 cpu-map { 98 cluster0 { 99 core0 { 100 cpu = <&a57_0>; 101 }; 102 core1 { 103 cpu = <&a57_1>; 104 }; 105 core2 { 106 cpu = <&a57_2>; 107 }; 108 core3 { 109 cpu = <&a57_3>; 110 }; 111 }; 112 113 cluster1 { 114 core0 { 115 cpu = <&a53_0>; 116 }; 117 core1 { 118 cpu = <&a53_1>; 119 }; 120 core2 { 121 cpu = <&a53_2>; 122 }; 123 core3 { 124 cpu = <&a53_3>; 125 }; 126 }; 127 }; 128 129 a57_0: cpu@0 { 130 compatible = "arm,cortex-a57"; 131 reg = <0x0>; 132 device_type = "cpu"; 133 power-domains = <&sysc R8A774E1_PD_CA57_CPU0>; 134 next-level-cache = <&L2_CA57>; 135 enable-method = "psci"; 136 cpu-idle-states = <&CPU_SLEEP_0>; 137 dynamic-power-coefficient = <854>; 138 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 139 operating-points-v2 = <&cluster0_opp>; 140 capacity-dmips-mhz = <1024>; 141 #cooling-cells = <2>; 142 }; 143 144 a57_1: cpu@1 { 145 compatible = "arm,cortex-a57"; 146 reg = <0x1>; 147 device_type = "cpu"; 148 power-domains = <&sysc R8A774E1_PD_CA57_CPU1>; 149 next-level-cache = <&L2_CA57>; 150 enable-method = "psci"; 151 cpu-idle-states = <&CPU_SLEEP_0>; 152 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 153 operating-points-v2 = <&cluster0_opp>; 154 capacity-dmips-mhz = <1024>; 155 #cooling-cells = <2>; 156 }; 157 158 a57_2: cpu@2 { 159 compatible = "arm,cortex-a57"; 160 reg = <0x2>; 161 device_type = "cpu"; 162 power-domains = <&sysc R8A774E1_PD_CA57_CPU2>; 163 next-level-cache = <&L2_CA57>; 164 enable-method = "psci"; 165 cpu-idle-states = <&CPU_SLEEP_0>; 166 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 167 operating-points-v2 = <&cluster0_opp>; 168 capacity-dmips-mhz = <1024>; 169 #cooling-cells = <2>; 170 }; 171 172 a57_3: cpu@3 { 173 compatible = "arm,cortex-a57"; 174 reg = <0x3>; 175 device_type = "cpu"; 176 power-domains = <&sysc R8A774E1_PD_CA57_CPU3>; 177 next-level-cache = <&L2_CA57>; 178 enable-method = "psci"; 179 cpu-idle-states = <&CPU_SLEEP_0>; 180 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 181 operating-points-v2 = <&cluster0_opp>; 182 capacity-dmips-mhz = <1024>; 183 #cooling-cells = <2>; 184 }; 185 186 a53_0: cpu@100 { 187 compatible = "arm,cortex-a53"; 188 reg = <0x100>; 189 device_type = "cpu"; 190 power-domains = <&sysc R8A774E1_PD_CA53_CPU0>; 191 next-level-cache = <&L2_CA53>; 192 enable-method = "psci"; 193 cpu-idle-states = <&CPU_SLEEP_1>; 194 #cooling-cells = <2>; 195 dynamic-power-coefficient = <277>; 196 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 197 operating-points-v2 = <&cluster1_opp>; 198 capacity-dmips-mhz = <535>; 199 }; 200 201 a53_1: cpu@101 { 202 compatible = "arm,cortex-a53"; 203 reg = <0x101>; 204 device_type = "cpu"; 205 power-domains = <&sysc R8A774E1_PD_CA53_CPU1>; 206 next-level-cache = <&L2_CA53>; 207 enable-method = "psci"; 208 cpu-idle-states = <&CPU_SLEEP_1>; 209 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 210 operating-points-v2 = <&cluster1_opp>; 211 capacity-dmips-mhz = <535>; 212 }; 213 214 a53_2: cpu@102 { 215 compatible = "arm,cortex-a53"; 216 reg = <0x102>; 217 device_type = "cpu"; 218 power-domains = <&sysc R8A774E1_PD_CA53_CPU2>; 219 next-level-cache = <&L2_CA53>; 220 enable-method = "psci"; 221 cpu-idle-states = <&CPU_SLEEP_1>; 222 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 223 operating-points-v2 = <&cluster1_opp>; 224 capacity-dmips-mhz = <535>; 225 }; 226 227 a53_3: cpu@103 { 228 compatible = "arm,cortex-a53"; 229 reg = <0x103>; 230 device_type = "cpu"; 231 power-domains = <&sysc R8A774E1_PD_CA53_CPU3>; 232 next-level-cache = <&L2_CA53>; 233 enable-method = "psci"; 234 cpu-idle-states = <&CPU_SLEEP_1>; 235 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 236 operating-points-v2 = <&cluster1_opp>; 237 capacity-dmips-mhz = <535>; 238 }; 239 240 L2_CA57: cache-controller-0 { 241 compatible = "cache"; 242 power-domains = <&sysc R8A774E1_PD_CA57_SCU>; 243 cache-unified; 244 cache-level = <2>; 245 }; 246 247 L2_CA53: cache-controller-1 { 248 compatible = "cache"; 249 power-domains = <&sysc R8A774E1_PD_CA53_SCU>; 250 cache-unified; 251 cache-level = <2>; 252 }; 253 254 idle-states { 255 entry-method = "psci"; 256 257 CPU_SLEEP_0: cpu-sleep-0 { 258 compatible = "arm,idle-state"; 259 arm,psci-suspend-param = <0x0010000>; 260 local-timer-stop; 261 entry-latency-us = <400>; 262 exit-latency-us = <500>; 263 min-residency-us = <4000>; 264 }; 265 266 CPU_SLEEP_1: cpu-sleep-1 { 267 compatible = "arm,idle-state"; 268 arm,psci-suspend-param = <0x0010000>; 269 local-timer-stop; 270 entry-latency-us = <700>; 271 exit-latency-us = <700>; 272 min-residency-us = <5000>; 273 }; 274 }; 275 }; 276 277 extal_clk: extal { 278 compatible = "fixed-clock"; 279 #clock-cells = <0>; 280 /* This value must be overridden by the board */ 281 clock-frequency = <0>; 282 }; 283 284 extalr_clk: extalr { 285 compatible = "fixed-clock"; 286 #clock-cells = <0>; 287 /* This value must be overridden by the board */ 288 clock-frequency = <0>; 289 }; 290 291 /* External PCIe clock - can be overridden by the board */ 292 pcie_bus_clk: pcie_bus { 293 compatible = "fixed-clock"; 294 #clock-cells = <0>; 295 clock-frequency = <0>; 296 }; 297 298 pmu_a53 { 299 compatible = "arm,cortex-a53-pmu"; 300 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 301 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 302 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 303 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 304 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 305 }; 306 307 pmu_a57 { 308 compatible = "arm,cortex-a57-pmu"; 309 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 310 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 311 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 312 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 313 interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>; 314 }; 315 316 psci { 317 compatible = "arm,psci-1.0", "arm,psci-0.2"; 318 method = "smc"; 319 }; 320 321 /* External SCIF clock - to be overridden by boards that provide it */ 322 scif_clk: scif { 323 compatible = "fixed-clock"; 324 #clock-cells = <0>; 325 clock-frequency = <0>; 326 }; 327 328 soc { 329 compatible = "simple-bus"; 330 interrupt-parent = <&gic>; 331 #address-cells = <2>; 332 #size-cells = <2>; 333 ranges; 334 335 rwdt: watchdog@e6020000 { 336 compatible = "renesas,r8a774e1-wdt", 337 "renesas,rcar-gen3-wdt"; 338 reg = <0 0xe6020000 0 0x0c>; 339 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&cpg CPG_MOD 402>; 341 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 342 resets = <&cpg 402>; 343 status = "disabled"; 344 }; 345 346 gpio0: gpio@e6050000 { 347 compatible = "renesas,gpio-r8a774e1", 348 "renesas,rcar-gen3-gpio"; 349 reg = <0 0xe6050000 0 0x50>; 350 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 351 #gpio-cells = <2>; 352 gpio-controller; 353 gpio-ranges = <&pfc 0 0 16>; 354 #interrupt-cells = <2>; 355 interrupt-controller; 356 clocks = <&cpg CPG_MOD 912>; 357 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 358 resets = <&cpg 912>; 359 }; 360 361 gpio1: gpio@e6051000 { 362 compatible = "renesas,gpio-r8a774e1", 363 "renesas,rcar-gen3-gpio"; 364 reg = <0 0xe6051000 0 0x50>; 365 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 366 #gpio-cells = <2>; 367 gpio-controller; 368 gpio-ranges = <&pfc 0 32 29>; 369 #interrupt-cells = <2>; 370 interrupt-controller; 371 clocks = <&cpg CPG_MOD 911>; 372 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 373 resets = <&cpg 911>; 374 }; 375 376 gpio2: gpio@e6052000 { 377 compatible = "renesas,gpio-r8a774e1", 378 "renesas,rcar-gen3-gpio"; 379 reg = <0 0xe6052000 0 0x50>; 380 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 381 #gpio-cells = <2>; 382 gpio-controller; 383 gpio-ranges = <&pfc 0 64 15>; 384 #interrupt-cells = <2>; 385 interrupt-controller; 386 clocks = <&cpg CPG_MOD 910>; 387 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 388 resets = <&cpg 910>; 389 }; 390 391 gpio3: gpio@e6053000 { 392 compatible = "renesas,gpio-r8a774e1", 393 "renesas,rcar-gen3-gpio"; 394 reg = <0 0xe6053000 0 0x50>; 395 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 396 #gpio-cells = <2>; 397 gpio-controller; 398 gpio-ranges = <&pfc 0 96 16>; 399 #interrupt-cells = <2>; 400 interrupt-controller; 401 clocks = <&cpg CPG_MOD 909>; 402 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 403 resets = <&cpg 909>; 404 }; 405 406 gpio4: gpio@e6054000 { 407 compatible = "renesas,gpio-r8a774e1", 408 "renesas,rcar-gen3-gpio"; 409 reg = <0 0xe6054000 0 0x50>; 410 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 411 #gpio-cells = <2>; 412 gpio-controller; 413 gpio-ranges = <&pfc 0 128 18>; 414 #interrupt-cells = <2>; 415 interrupt-controller; 416 clocks = <&cpg CPG_MOD 908>; 417 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 418 resets = <&cpg 908>; 419 }; 420 421 gpio5: gpio@e6055000 { 422 compatible = "renesas,gpio-r8a774e1", 423 "renesas,rcar-gen3-gpio"; 424 reg = <0 0xe6055000 0 0x50>; 425 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 426 #gpio-cells = <2>; 427 gpio-controller; 428 gpio-ranges = <&pfc 0 160 26>; 429 #interrupt-cells = <2>; 430 interrupt-controller; 431 clocks = <&cpg CPG_MOD 907>; 432 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 433 resets = <&cpg 907>; 434 }; 435 436 gpio6: gpio@e6055400 { 437 compatible = "renesas,gpio-r8a774e1", 438 "renesas,rcar-gen3-gpio"; 439 reg = <0 0xe6055400 0 0x50>; 440 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 441 #gpio-cells = <2>; 442 gpio-controller; 443 gpio-ranges = <&pfc 0 192 32>; 444 #interrupt-cells = <2>; 445 interrupt-controller; 446 clocks = <&cpg CPG_MOD 906>; 447 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 448 resets = <&cpg 906>; 449 }; 450 451 gpio7: gpio@e6055800 { 452 compatible = "renesas,gpio-r8a774e1", 453 "renesas,rcar-gen3-gpio"; 454 reg = <0 0xe6055800 0 0x50>; 455 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 456 #gpio-cells = <2>; 457 gpio-controller; 458 gpio-ranges = <&pfc 0 224 4>; 459 #interrupt-cells = <2>; 460 interrupt-controller; 461 clocks = <&cpg CPG_MOD 905>; 462 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 463 resets = <&cpg 905>; 464 }; 465 466 pfc: pinctrl@e6060000 { 467 compatible = "renesas,pfc-r8a774e1"; 468 reg = <0 0xe6060000 0 0x50c>; 469 }; 470 471 cmt0: timer@e60f0000 { 472 compatible = "renesas,r8a774e1-cmt0", 473 "renesas,rcar-gen3-cmt0"; 474 reg = <0 0xe60f0000 0 0x1004>; 475 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&cpg CPG_MOD 303>; 478 clock-names = "fck"; 479 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 480 resets = <&cpg 303>; 481 status = "disabled"; 482 }; 483 484 cmt1: timer@e6130000 { 485 compatible = "renesas,r8a774e1-cmt1", 486 "renesas,rcar-gen3-cmt1"; 487 reg = <0 0xe6130000 0 0x1004>; 488 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&cpg CPG_MOD 302>; 497 clock-names = "fck"; 498 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 499 resets = <&cpg 302>; 500 status = "disabled"; 501 }; 502 503 cmt2: timer@e6140000 { 504 compatible = "renesas,r8a774e1-cmt1", 505 "renesas,rcar-gen3-cmt1"; 506 reg = <0 0xe6140000 0 0x1004>; 507 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 515 clocks = <&cpg CPG_MOD 301>; 516 clock-names = "fck"; 517 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 518 resets = <&cpg 301>; 519 status = "disabled"; 520 }; 521 522 cmt3: timer@e6148000 { 523 compatible = "renesas,r8a774e1-cmt1", 524 "renesas,rcar-gen3-cmt1"; 525 reg = <0 0xe6148000 0 0x1004>; 526 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&cpg CPG_MOD 300>; 535 clock-names = "fck"; 536 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 537 resets = <&cpg 300>; 538 status = "disabled"; 539 }; 540 541 cpg: clock-controller@e6150000 { 542 compatible = "renesas,r8a774e1-cpg-mssr"; 543 reg = <0 0xe6150000 0 0x1000>; 544 clocks = <&extal_clk>, <&extalr_clk>; 545 clock-names = "extal", "extalr"; 546 #clock-cells = <2>; 547 #power-domain-cells = <0>; 548 #reset-cells = <1>; 549 }; 550 551 rst: reset-controller@e6160000 { 552 compatible = "renesas,r8a774e1-rst"; 553 reg = <0 0xe6160000 0 0x0200>; 554 }; 555 556 sysc: system-controller@e6180000 { 557 compatible = "renesas,r8a774e1-sysc"; 558 reg = <0 0xe6180000 0 0x0400>; 559 #power-domain-cells = <1>; 560 }; 561 562 tsc: thermal@e6198000 { 563 compatible = "renesas,r8a774e1-thermal"; 564 reg = <0 0xe6198000 0 0x100>, 565 <0 0xe61a0000 0 0x100>, 566 <0 0xe61a8000 0 0x100>; 567 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&cpg CPG_MOD 522>; 571 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 572 resets = <&cpg 522>; 573 #thermal-sensor-cells = <1>; 574 }; 575 576 intc_ex: interrupt-controller@e61c0000 { 577 compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc"; 578 #interrupt-cells = <2>; 579 interrupt-controller; 580 reg = <0 0xe61c0000 0 0x200>; 581 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&cpg CPG_MOD 407>; 588 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 589 resets = <&cpg 407>; 590 }; 591 592 tmu0: timer@e61e0000 { 593 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 594 reg = <0 0xe61e0000 0 0x30>; 595 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&cpg CPG_MOD 125>; 599 clock-names = "fck"; 600 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 601 resets = <&cpg 125>; 602 status = "disabled"; 603 }; 604 605 tmu1: timer@e6fc0000 { 606 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 607 reg = <0 0xe6fc0000 0 0x30>; 608 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&cpg CPG_MOD 124>; 612 clock-names = "fck"; 613 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 614 resets = <&cpg 124>; 615 status = "disabled"; 616 }; 617 618 tmu2: timer@e6fd0000 { 619 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 620 reg = <0 0xe6fd0000 0 0x30>; 621 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&cpg CPG_MOD 123>; 625 clock-names = "fck"; 626 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 627 resets = <&cpg 123>; 628 status = "disabled"; 629 }; 630 631 tmu3: timer@e6fe0000 { 632 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 633 reg = <0 0xe6fe0000 0 0x30>; 634 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 637 clocks = <&cpg CPG_MOD 122>; 638 clock-names = "fck"; 639 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 640 resets = <&cpg 122>; 641 status = "disabled"; 642 }; 643 644 tmu4: timer@ffc00000 { 645 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 646 reg = <0 0xffc00000 0 0x30>; 647 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&cpg CPG_MOD 121>; 651 clock-names = "fck"; 652 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 653 resets = <&cpg 121>; 654 status = "disabled"; 655 }; 656 657 i2c0: i2c@e6500000 { 658 #address-cells = <1>; 659 #size-cells = <0>; 660 compatible = "renesas,i2c-r8a774e1", 661 "renesas,rcar-gen3-i2c"; 662 reg = <0 0xe6500000 0 0x40>; 663 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 664 clocks = <&cpg CPG_MOD 931>; 665 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 666 resets = <&cpg 931>; 667 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 668 <&dmac2 0x91>, <&dmac2 0x90>; 669 dma-names = "tx", "rx", "tx", "rx"; 670 i2c-scl-internal-delay-ns = <110>; 671 status = "disabled"; 672 }; 673 674 i2c1: i2c@e6508000 { 675 #address-cells = <1>; 676 #size-cells = <0>; 677 compatible = "renesas,i2c-r8a774e1", 678 "renesas,rcar-gen3-i2c"; 679 reg = <0 0xe6508000 0 0x40>; 680 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 681 clocks = <&cpg CPG_MOD 930>; 682 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 683 resets = <&cpg 930>; 684 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 685 <&dmac2 0x93>, <&dmac2 0x92>; 686 dma-names = "tx", "rx", "tx", "rx"; 687 i2c-scl-internal-delay-ns = <6>; 688 status = "disabled"; 689 }; 690 691 i2c2: i2c@e6510000 { 692 #address-cells = <1>; 693 #size-cells = <0>; 694 compatible = "renesas,i2c-r8a774e1", 695 "renesas,rcar-gen3-i2c"; 696 reg = <0 0xe6510000 0 0x40>; 697 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&cpg CPG_MOD 929>; 699 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 700 resets = <&cpg 929>; 701 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 702 <&dmac2 0x95>, <&dmac2 0x94>; 703 dma-names = "tx", "rx", "tx", "rx"; 704 i2c-scl-internal-delay-ns = <6>; 705 status = "disabled"; 706 }; 707 708 i2c3: i2c@e66d0000 { 709 #address-cells = <1>; 710 #size-cells = <0>; 711 compatible = "renesas,i2c-r8a774e1", 712 "renesas,rcar-gen3-i2c"; 713 reg = <0 0xe66d0000 0 0x40>; 714 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 715 clocks = <&cpg CPG_MOD 928>; 716 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 717 resets = <&cpg 928>; 718 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 719 dma-names = "tx", "rx"; 720 i2c-scl-internal-delay-ns = <110>; 721 status = "disabled"; 722 }; 723 724 i2c4: i2c@e66d8000 { 725 #address-cells = <1>; 726 #size-cells = <0>; 727 compatible = "renesas,i2c-r8a774e1", 728 "renesas,rcar-gen3-i2c"; 729 reg = <0 0xe66d8000 0 0x40>; 730 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&cpg CPG_MOD 927>; 732 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 733 resets = <&cpg 927>; 734 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 735 dma-names = "tx", "rx"; 736 i2c-scl-internal-delay-ns = <110>; 737 status = "disabled"; 738 }; 739 740 i2c5: i2c@e66e0000 { 741 #address-cells = <1>; 742 #size-cells = <0>; 743 compatible = "renesas,i2c-r8a774e1", 744 "renesas,rcar-gen3-i2c"; 745 reg = <0 0xe66e0000 0 0x40>; 746 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&cpg CPG_MOD 919>; 748 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 749 resets = <&cpg 919>; 750 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 751 dma-names = "tx", "rx"; 752 i2c-scl-internal-delay-ns = <110>; 753 status = "disabled"; 754 }; 755 756 i2c6: i2c@e66e8000 { 757 #address-cells = <1>; 758 #size-cells = <0>; 759 compatible = "renesas,i2c-r8a774e1", 760 "renesas,rcar-gen3-i2c"; 761 reg = <0 0xe66e8000 0 0x40>; 762 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 763 clocks = <&cpg CPG_MOD 918>; 764 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 765 resets = <&cpg 918>; 766 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 767 dma-names = "tx", "rx"; 768 i2c-scl-internal-delay-ns = <6>; 769 status = "disabled"; 770 }; 771 772 i2c_dvfs: i2c@e60b0000 { 773 #address-cells = <1>; 774 #size-cells = <0>; 775 compatible = "renesas,iic-r8a774e1", 776 "renesas,rcar-gen3-iic", 777 "renesas,rmobile-iic"; 778 reg = <0 0xe60b0000 0 0x425>; 779 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&cpg CPG_MOD 926>; 781 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 782 resets = <&cpg 926>; 783 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 784 dma-names = "tx", "rx"; 785 status = "disabled"; 786 }; 787 788 hscif0: serial@e6540000 { 789 compatible = "renesas,hscif-r8a774e1", 790 "renesas,rcar-gen3-hscif", 791 "renesas,hscif"; 792 reg = <0 0xe6540000 0 0x60>; 793 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 794 clocks = <&cpg CPG_MOD 520>, 795 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 796 <&scif_clk>; 797 clock-names = "fck", "brg_int", "scif_clk"; 798 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 799 <&dmac2 0x31>, <&dmac2 0x30>; 800 dma-names = "tx", "rx", "tx", "rx"; 801 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 802 resets = <&cpg 520>; 803 status = "disabled"; 804 }; 805 806 hscif1: serial@e6550000 { 807 compatible = "renesas,hscif-r8a774e1", 808 "renesas,rcar-gen3-hscif", 809 "renesas,hscif"; 810 reg = <0 0xe6550000 0 0x60>; 811 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&cpg CPG_MOD 519>, 813 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 814 <&scif_clk>; 815 clock-names = "fck", "brg_int", "scif_clk"; 816 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 817 <&dmac2 0x33>, <&dmac2 0x32>; 818 dma-names = "tx", "rx", "tx", "rx"; 819 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 820 resets = <&cpg 519>; 821 status = "disabled"; 822 }; 823 824 hscif2: serial@e6560000 { 825 compatible = "renesas,hscif-r8a774e1", 826 "renesas,rcar-gen3-hscif", 827 "renesas,hscif"; 828 reg = <0 0xe6560000 0 0x60>; 829 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 830 clocks = <&cpg CPG_MOD 518>, 831 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 832 <&scif_clk>; 833 clock-names = "fck", "brg_int", "scif_clk"; 834 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 835 <&dmac2 0x35>, <&dmac2 0x34>; 836 dma-names = "tx", "rx", "tx", "rx"; 837 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 838 resets = <&cpg 518>; 839 status = "disabled"; 840 }; 841 842 hscif3: serial@e66a0000 { 843 compatible = "renesas,hscif-r8a774e1", 844 "renesas,rcar-gen3-hscif", 845 "renesas,hscif"; 846 reg = <0 0xe66a0000 0 0x60>; 847 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 848 clocks = <&cpg CPG_MOD 517>, 849 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 850 <&scif_clk>; 851 clock-names = "fck", "brg_int", "scif_clk"; 852 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 853 dma-names = "tx", "rx"; 854 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 855 resets = <&cpg 517>; 856 status = "disabled"; 857 }; 858 859 hscif4: serial@e66b0000 { 860 compatible = "renesas,hscif-r8a774e1", 861 "renesas,rcar-gen3-hscif", 862 "renesas,hscif"; 863 reg = <0 0xe66b0000 0 0x60>; 864 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 865 clocks = <&cpg CPG_MOD 516>, 866 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 867 <&scif_clk>; 868 clock-names = "fck", "brg_int", "scif_clk"; 869 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 870 dma-names = "tx", "rx"; 871 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 872 resets = <&cpg 516>; 873 status = "disabled"; 874 }; 875 876 hsusb: usb@e6590000 { 877 compatible = "renesas,usbhs-r8a774e1", 878 "renesas,rcar-gen3-usbhs"; 879 reg = <0 0xe6590000 0 0x200>; 880 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 881 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 882 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 883 <&usb_dmac1 0>, <&usb_dmac1 1>; 884 dma-names = "ch0", "ch1", "ch2", "ch3"; 885 renesas,buswait = <11>; 886 phys = <&usb2_phy0 3>; 887 phy-names = "usb"; 888 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 889 resets = <&cpg 704>, <&cpg 703>; 890 status = "disabled"; 891 }; 892 893 usb_dmac0: dma-controller@e65a0000 { 894 compatible = "renesas,r8a774e1-usb-dmac", 895 "renesas,usb-dmac"; 896 reg = <0 0xe65a0000 0 0x100>; 897 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 899 interrupt-names = "ch0", "ch1"; 900 clocks = <&cpg CPG_MOD 330>; 901 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 902 resets = <&cpg 330>; 903 #dma-cells = <1>; 904 dma-channels = <2>; 905 }; 906 907 usb_dmac1: dma-controller@e65b0000 { 908 compatible = "renesas,r8a774e1-usb-dmac", 909 "renesas,usb-dmac"; 910 reg = <0 0xe65b0000 0 0x100>; 911 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 913 interrupt-names = "ch0", "ch1"; 914 clocks = <&cpg CPG_MOD 331>; 915 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 916 resets = <&cpg 331>; 917 #dma-cells = <1>; 918 dma-channels = <2>; 919 }; 920 921 usb3_phy0: usb-phy@e65ee000 { 922 compatible = "renesas,r8a774e1-usb3-phy", 923 "renesas,rcar-gen3-usb3-phy"; 924 reg = <0 0xe65ee000 0 0x90>; 925 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 926 <&usb_extal_clk>; 927 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 928 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 929 resets = <&cpg 328>; 930 #phy-cells = <0>; 931 status = "disabled"; 932 }; 933 934 dmac0: dma-controller@e6700000 { 935 compatible = "renesas,dmac-r8a774e1", 936 "renesas,rcar-dmac"; 937 reg = <0 0xe6700000 0 0x10000>; 938 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 955 interrupt-names = "error", 956 "ch0", "ch1", "ch2", "ch3", 957 "ch4", "ch5", "ch6", "ch7", 958 "ch8", "ch9", "ch10", "ch11", 959 "ch12", "ch13", "ch14", "ch15"; 960 clocks = <&cpg CPG_MOD 219>; 961 clock-names = "fck"; 962 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 963 resets = <&cpg 219>; 964 #dma-cells = <1>; 965 dma-channels = <16>; 966 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 967 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 968 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 969 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 970 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 971 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 972 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 973 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 974 }; 975 976 dmac1: dma-controller@e7300000 { 977 compatible = "renesas,dmac-r8a774e1", 978 "renesas,rcar-dmac"; 979 reg = <0 0xe7300000 0 0x10000>; 980 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 981 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 982 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 997 interrupt-names = "error", 998 "ch0", "ch1", "ch2", "ch3", 999 "ch4", "ch5", "ch6", "ch7", 1000 "ch8", "ch9", "ch10", "ch11", 1001 "ch12", "ch13", "ch14", "ch15"; 1002 clocks = <&cpg CPG_MOD 218>; 1003 clock-names = "fck"; 1004 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1005 resets = <&cpg 218>; 1006 #dma-cells = <1>; 1007 dma-channels = <16>; 1008 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 1009 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 1010 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 1011 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 1012 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 1013 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 1014 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 1015 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 1016 }; 1017 1018 dmac2: dma-controller@e7310000 { 1019 compatible = "renesas,dmac-r8a774e1", 1020 "renesas,rcar-dmac"; 1021 reg = <0 0xe7310000 0 0x10000>; 1022 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 1023 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 1024 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 1026 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 1033 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 1034 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 1035 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 1036 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 1037 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 1038 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 1039 interrupt-names = "error", 1040 "ch0", "ch1", "ch2", "ch3", 1041 "ch4", "ch5", "ch6", "ch7", 1042 "ch8", "ch9", "ch10", "ch11", 1043 "ch12", "ch13", "ch14", "ch15"; 1044 clocks = <&cpg CPG_MOD 217>; 1045 clock-names = "fck"; 1046 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1047 resets = <&cpg 217>; 1048 #dma-cells = <1>; 1049 dma-channels = <16>; 1050 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 1051 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 1052 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 1053 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 1054 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 1055 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 1056 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 1057 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 1058 }; 1059 1060 ipmmu_ds0: iommu@e6740000 { 1061 compatible = "renesas,ipmmu-r8a774e1"; 1062 reg = <0 0xe6740000 0 0x1000>; 1063 renesas,ipmmu-main = <&ipmmu_mm 0>; 1064 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1065 #iommu-cells = <1>; 1066 }; 1067 1068 ipmmu_ds1: iommu@e7740000 { 1069 compatible = "renesas,ipmmu-r8a774e1"; 1070 reg = <0 0xe7740000 0 0x1000>; 1071 renesas,ipmmu-main = <&ipmmu_mm 1>; 1072 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1073 #iommu-cells = <1>; 1074 }; 1075 1076 ipmmu_hc: iommu@e6570000 { 1077 compatible = "renesas,ipmmu-r8a774e1"; 1078 reg = <0 0xe6570000 0 0x1000>; 1079 renesas,ipmmu-main = <&ipmmu_mm 2>; 1080 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1081 #iommu-cells = <1>; 1082 }; 1083 1084 ipmmu_mm: iommu@e67b0000 { 1085 compatible = "renesas,ipmmu-r8a774e1"; 1086 reg = <0 0xe67b0000 0 0x1000>; 1087 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1089 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1090 #iommu-cells = <1>; 1091 }; 1092 1093 ipmmu_mp0: iommu@ec670000 { 1094 compatible = "renesas,ipmmu-r8a774e1"; 1095 reg = <0 0xec670000 0 0x1000>; 1096 renesas,ipmmu-main = <&ipmmu_mm 4>; 1097 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1098 #iommu-cells = <1>; 1099 }; 1100 1101 ipmmu_pv0: iommu@fd800000 { 1102 compatible = "renesas,ipmmu-r8a774e1"; 1103 reg = <0 0xfd800000 0 0x1000>; 1104 renesas,ipmmu-main = <&ipmmu_mm 6>; 1105 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1106 #iommu-cells = <1>; 1107 }; 1108 1109 ipmmu_pv1: iommu@fd950000 { 1110 compatible = "renesas,ipmmu-r8a774e1"; 1111 reg = <0 0xfd950000 0 0x1000>; 1112 renesas,ipmmu-main = <&ipmmu_mm 7>; 1113 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1114 #iommu-cells = <1>; 1115 }; 1116 1117 ipmmu_pv2: iommu@fd960000 { 1118 compatible = "renesas,ipmmu-r8a774e1"; 1119 reg = <0 0xfd960000 0 0x1000>; 1120 renesas,ipmmu-main = <&ipmmu_mm 8>; 1121 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1122 #iommu-cells = <1>; 1123 }; 1124 1125 ipmmu_pv3: iommu@fd970000 { 1126 compatible = "renesas,ipmmu-r8a774e1"; 1127 reg = <0 0xfd970000 0 0x1000>; 1128 renesas,ipmmu-main = <&ipmmu_mm 9>; 1129 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1130 #iommu-cells = <1>; 1131 }; 1132 1133 ipmmu_vc0: iommu@fe6b0000 { 1134 compatible = "renesas,ipmmu-r8a774e1"; 1135 reg = <0 0xfe6b0000 0 0x1000>; 1136 renesas,ipmmu-main = <&ipmmu_mm 12>; 1137 power-domains = <&sysc R8A774E1_PD_A3VC>; 1138 #iommu-cells = <1>; 1139 }; 1140 1141 ipmmu_vc1: iommu@fe6f0000 { 1142 compatible = "renesas,ipmmu-r8a774e1"; 1143 reg = <0 0xfe6f0000 0 0x1000>; 1144 renesas,ipmmu-main = <&ipmmu_mm 13>; 1145 power-domains = <&sysc R8A774E1_PD_A3VC>; 1146 #iommu-cells = <1>; 1147 }; 1148 1149 ipmmu_vi0: iommu@febd0000 { 1150 compatible = "renesas,ipmmu-r8a774e1"; 1151 reg = <0 0xfebd0000 0 0x1000>; 1152 renesas,ipmmu-main = <&ipmmu_mm 14>; 1153 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1154 #iommu-cells = <1>; 1155 }; 1156 1157 ipmmu_vi1: iommu@febe0000 { 1158 compatible = "renesas,ipmmu-r8a774e1"; 1159 reg = <0 0xfebe0000 0 0x1000>; 1160 renesas,ipmmu-main = <&ipmmu_mm 15>; 1161 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1162 #iommu-cells = <1>; 1163 }; 1164 1165 ipmmu_vp0: iommu@fe990000 { 1166 compatible = "renesas,ipmmu-r8a774e1"; 1167 reg = <0 0xfe990000 0 0x1000>; 1168 renesas,ipmmu-main = <&ipmmu_mm 16>; 1169 power-domains = <&sysc R8A774E1_PD_A3VP>; 1170 #iommu-cells = <1>; 1171 }; 1172 1173 ipmmu_vp1: iommu@fe980000 { 1174 compatible = "renesas,ipmmu-r8a774e1"; 1175 reg = <0 0xfe980000 0 0x1000>; 1176 renesas,ipmmu-main = <&ipmmu_mm 17>; 1177 power-domains = <&sysc R8A774E1_PD_A3VP>; 1178 #iommu-cells = <1>; 1179 }; 1180 1181 avb: ethernet@e6800000 { 1182 compatible = "renesas,etheravb-r8a774e1", 1183 "renesas,etheravb-rcar-gen3"; 1184 reg = <0 0xe6800000 0 0x800>; 1185 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1210 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1211 "ch4", "ch5", "ch6", "ch7", 1212 "ch8", "ch9", "ch10", "ch11", 1213 "ch12", "ch13", "ch14", "ch15", 1214 "ch16", "ch17", "ch18", "ch19", 1215 "ch20", "ch21", "ch22", "ch23", 1216 "ch24"; 1217 clocks = <&cpg CPG_MOD 812>; 1218 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1219 resets = <&cpg 812>; 1220 phy-mode = "rgmii"; 1221 iommus = <&ipmmu_ds0 16>; 1222 #address-cells = <1>; 1223 #size-cells = <0>; 1224 status = "disabled"; 1225 }; 1226 1227 can0: can@e6c30000 { 1228 compatible = "renesas,can-r8a774e1", 1229 "renesas,rcar-gen3-can"; 1230 reg = <0 0xe6c30000 0 0x1000>; 1231 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1232 clocks = <&cpg CPG_MOD 916>, 1233 <&cpg CPG_CORE R8A774E1_CLK_CANFD>, 1234 <&can_clk>; 1235 clock-names = "clkp1", "clkp2", "can_clk"; 1236 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; 1237 assigned-clock-rates = <40000000>; 1238 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1239 resets = <&cpg 916>; 1240 status = "disabled"; 1241 }; 1242 1243 can1: can@e6c38000 { 1244 compatible = "renesas,can-r8a774e1", 1245 "renesas,rcar-gen3-can"; 1246 reg = <0 0xe6c38000 0 0x1000>; 1247 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1248 clocks = <&cpg CPG_MOD 915>, 1249 <&cpg CPG_CORE R8A774E1_CLK_CANFD>, 1250 <&can_clk>; 1251 clock-names = "clkp1", "clkp2", "can_clk"; 1252 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; 1253 assigned-clock-rates = <40000000>; 1254 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1255 resets = <&cpg 915>; 1256 status = "disabled"; 1257 }; 1258 1259 canfd: can@e66c0000 { 1260 compatible = "renesas,r8a774e1-canfd", 1261 "renesas,rcar-gen3-canfd"; 1262 reg = <0 0xe66c0000 0 0x8000>; 1263 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1265 clocks = <&cpg CPG_MOD 914>, 1266 <&cpg CPG_CORE R8A774E1_CLK_CANFD>, 1267 <&can_clk>; 1268 clock-names = "fck", "canfd", "can_clk"; 1269 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; 1270 assigned-clock-rates = <40000000>; 1271 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1272 resets = <&cpg 914>; 1273 status = "disabled"; 1274 1275 channel0 { 1276 status = "disabled"; 1277 }; 1278 1279 channel1 { 1280 status = "disabled"; 1281 }; 1282 }; 1283 1284 pwm0: pwm@e6e30000 { 1285 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; 1286 reg = <0 0xe6e30000 0 0x8>; 1287 clocks = <&cpg CPG_MOD 523>; 1288 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1289 resets = <&cpg 523>; 1290 #pwm-cells = <2>; 1291 status = "disabled"; 1292 }; 1293 1294 pwm1: pwm@e6e31000 { 1295 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; 1296 reg = <0 0xe6e31000 0 0x8>; 1297 clocks = <&cpg CPG_MOD 523>; 1298 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1299 resets = <&cpg 523>; 1300 #pwm-cells = <2>; 1301 status = "disabled"; 1302 }; 1303 1304 pwm2: pwm@e6e32000 { 1305 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; 1306 reg = <0 0xe6e32000 0 0x8>; 1307 clocks = <&cpg CPG_MOD 523>; 1308 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1309 resets = <&cpg 523>; 1310 #pwm-cells = <2>; 1311 status = "disabled"; 1312 }; 1313 1314 pwm3: pwm@e6e33000 { 1315 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; 1316 reg = <0 0xe6e33000 0 0x8>; 1317 clocks = <&cpg CPG_MOD 523>; 1318 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1319 resets = <&cpg 523>; 1320 #pwm-cells = <2>; 1321 status = "disabled"; 1322 }; 1323 1324 pwm4: pwm@e6e34000 { 1325 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; 1326 reg = <0 0xe6e34000 0 0x8>; 1327 clocks = <&cpg CPG_MOD 523>; 1328 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1329 resets = <&cpg 523>; 1330 #pwm-cells = <2>; 1331 status = "disabled"; 1332 }; 1333 1334 pwm5: pwm@e6e35000 { 1335 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; 1336 reg = <0 0xe6e35000 0 0x8>; 1337 clocks = <&cpg CPG_MOD 523>; 1338 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1339 resets = <&cpg 523>; 1340 #pwm-cells = <2>; 1341 status = "disabled"; 1342 }; 1343 1344 pwm6: pwm@e6e36000 { 1345 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; 1346 reg = <0 0xe6e36000 0 0x8>; 1347 clocks = <&cpg CPG_MOD 523>; 1348 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1349 resets = <&cpg 523>; 1350 #pwm-cells = <2>; 1351 status = "disabled"; 1352 }; 1353 1354 scif0: serial@e6e60000 { 1355 compatible = "renesas,scif-r8a774e1", 1356 "renesas,rcar-gen3-scif", "renesas,scif"; 1357 reg = <0 0xe6e60000 0 0x40>; 1358 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1359 clocks = <&cpg CPG_MOD 207>, 1360 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1361 <&scif_clk>; 1362 clock-names = "fck", "brg_int", "scif_clk"; 1363 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1364 <&dmac2 0x51>, <&dmac2 0x50>; 1365 dma-names = "tx", "rx", "tx", "rx"; 1366 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1367 resets = <&cpg 207>; 1368 status = "disabled"; 1369 }; 1370 1371 scif1: serial@e6e68000 { 1372 compatible = "renesas,scif-r8a774e1", 1373 "renesas,rcar-gen3-scif", "renesas,scif"; 1374 reg = <0 0xe6e68000 0 0x40>; 1375 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1376 clocks = <&cpg CPG_MOD 206>, 1377 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1378 <&scif_clk>; 1379 clock-names = "fck", "brg_int", "scif_clk"; 1380 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1381 <&dmac2 0x53>, <&dmac2 0x52>; 1382 dma-names = "tx", "rx", "tx", "rx"; 1383 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1384 resets = <&cpg 206>; 1385 status = "disabled"; 1386 }; 1387 1388 scif2: serial@e6e88000 { 1389 compatible = "renesas,scif-r8a774e1", 1390 "renesas,rcar-gen3-scif", "renesas,scif"; 1391 reg = <0 0xe6e88000 0 0x40>; 1392 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1393 clocks = <&cpg CPG_MOD 310>, 1394 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1395 <&scif_clk>; 1396 clock-names = "fck", "brg_int", "scif_clk"; 1397 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1398 <&dmac2 0x13>, <&dmac2 0x12>; 1399 dma-names = "tx", "rx", "tx", "rx"; 1400 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1401 resets = <&cpg 310>; 1402 status = "disabled"; 1403 }; 1404 1405 scif3: serial@e6c50000 { 1406 compatible = "renesas,scif-r8a774e1", 1407 "renesas,rcar-gen3-scif", "renesas,scif"; 1408 reg = <0 0xe6c50000 0 0x40>; 1409 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1410 clocks = <&cpg CPG_MOD 204>, 1411 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1412 <&scif_clk>; 1413 clock-names = "fck", "brg_int", "scif_clk"; 1414 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1415 dma-names = "tx", "rx"; 1416 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1417 resets = <&cpg 204>; 1418 status = "disabled"; 1419 }; 1420 1421 scif4: serial@e6c40000 { 1422 compatible = "renesas,scif-r8a774e1", 1423 "renesas,rcar-gen3-scif", "renesas,scif"; 1424 reg = <0 0xe6c40000 0 0x40>; 1425 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1426 clocks = <&cpg CPG_MOD 203>, 1427 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1428 <&scif_clk>; 1429 clock-names = "fck", "brg_int", "scif_clk"; 1430 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1431 dma-names = "tx", "rx"; 1432 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1433 resets = <&cpg 203>; 1434 status = "disabled"; 1435 }; 1436 1437 scif5: serial@e6f30000 { 1438 compatible = "renesas,scif-r8a774e1", 1439 "renesas,rcar-gen3-scif", "renesas,scif"; 1440 reg = <0 0xe6f30000 0 0x40>; 1441 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1442 clocks = <&cpg CPG_MOD 202>, 1443 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1444 <&scif_clk>; 1445 clock-names = "fck", "brg_int", "scif_clk"; 1446 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1447 <&dmac2 0x5b>, <&dmac2 0x5a>; 1448 dma-names = "tx", "rx", "tx", "rx"; 1449 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1450 resets = <&cpg 202>; 1451 status = "disabled"; 1452 }; 1453 1454 msiof0: spi@e6e90000 { 1455 compatible = "renesas,msiof-r8a774e1", 1456 "renesas,rcar-gen3-msiof"; 1457 reg = <0 0xe6e90000 0 0x0064>; 1458 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1459 clocks = <&cpg CPG_MOD 211>; 1460 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1461 <&dmac2 0x41>, <&dmac2 0x40>; 1462 dma-names = "tx", "rx", "tx", "rx"; 1463 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1464 resets = <&cpg 211>; 1465 #address-cells = <1>; 1466 #size-cells = <0>; 1467 status = "disabled"; 1468 }; 1469 1470 msiof1: spi@e6ea0000 { 1471 compatible = "renesas,msiof-r8a774e1", 1472 "renesas,rcar-gen3-msiof"; 1473 reg = <0 0xe6ea0000 0 0x0064>; 1474 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1475 clocks = <&cpg CPG_MOD 210>; 1476 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1477 <&dmac2 0x43>, <&dmac2 0x42>; 1478 dma-names = "tx", "rx", "tx", "rx"; 1479 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1480 resets = <&cpg 210>; 1481 #address-cells = <1>; 1482 #size-cells = <0>; 1483 status = "disabled"; 1484 }; 1485 1486 msiof2: spi@e6c00000 { 1487 compatible = "renesas,msiof-r8a774e1", 1488 "renesas,rcar-gen3-msiof"; 1489 reg = <0 0xe6c00000 0 0x0064>; 1490 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1491 clocks = <&cpg CPG_MOD 209>; 1492 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1493 dma-names = "tx", "rx"; 1494 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1495 resets = <&cpg 209>; 1496 #address-cells = <1>; 1497 #size-cells = <0>; 1498 status = "disabled"; 1499 }; 1500 1501 msiof3: spi@e6c10000 { 1502 compatible = "renesas,msiof-r8a774e1", 1503 "renesas,rcar-gen3-msiof"; 1504 reg = <0 0xe6c10000 0 0x0064>; 1505 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1506 clocks = <&cpg CPG_MOD 208>; 1507 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1508 dma-names = "tx", "rx"; 1509 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1510 resets = <&cpg 208>; 1511 #address-cells = <1>; 1512 #size-cells = <0>; 1513 status = "disabled"; 1514 }; 1515 1516 vin0: video@e6ef0000 { 1517 compatible = "renesas,vin-r8a774e1"; 1518 reg = <0 0xe6ef0000 0 0x1000>; 1519 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1520 clocks = <&cpg CPG_MOD 811>; 1521 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1522 resets = <&cpg 811>; 1523 renesas,id = <0>; 1524 status = "disabled"; 1525 1526 ports { 1527 #address-cells = <1>; 1528 #size-cells = <0>; 1529 1530 port@1 { 1531 #address-cells = <1>; 1532 #size-cells = <0>; 1533 1534 reg = <1>; 1535 1536 vin0csi20: endpoint@0 { 1537 reg = <0>; 1538 remote-endpoint = <&csi20vin0>; 1539 }; 1540 vin0csi40: endpoint@2 { 1541 reg = <2>; 1542 remote-endpoint = <&csi40vin0>; 1543 }; 1544 }; 1545 }; 1546 }; 1547 1548 vin1: video@e6ef1000 { 1549 compatible = "renesas,vin-r8a774e1"; 1550 reg = <0 0xe6ef1000 0 0x1000>; 1551 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1552 clocks = <&cpg CPG_MOD 810>; 1553 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1554 resets = <&cpg 810>; 1555 renesas,id = <1>; 1556 status = "disabled"; 1557 1558 ports { 1559 #address-cells = <1>; 1560 #size-cells = <0>; 1561 1562 port@1 { 1563 #address-cells = <1>; 1564 #size-cells = <0>; 1565 1566 reg = <1>; 1567 1568 vin1csi20: endpoint@0 { 1569 reg = <0>; 1570 remote-endpoint = <&csi20vin1>; 1571 }; 1572 vin1csi40: endpoint@2 { 1573 reg = <2>; 1574 remote-endpoint = <&csi40vin1>; 1575 }; 1576 }; 1577 }; 1578 }; 1579 1580 vin2: video@e6ef2000 { 1581 compatible = "renesas,vin-r8a774e1"; 1582 reg = <0 0xe6ef2000 0 0x1000>; 1583 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1584 clocks = <&cpg CPG_MOD 809>; 1585 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1586 resets = <&cpg 809>; 1587 renesas,id = <2>; 1588 status = "disabled"; 1589 1590 ports { 1591 #address-cells = <1>; 1592 #size-cells = <0>; 1593 1594 port@1 { 1595 #address-cells = <1>; 1596 #size-cells = <0>; 1597 1598 reg = <1>; 1599 1600 vin2csi20: endpoint@0 { 1601 reg = <0>; 1602 remote-endpoint = <&csi20vin2>; 1603 }; 1604 vin2csi40: endpoint@2 { 1605 reg = <2>; 1606 remote-endpoint = <&csi40vin2>; 1607 }; 1608 }; 1609 }; 1610 }; 1611 1612 vin3: video@e6ef3000 { 1613 compatible = "renesas,vin-r8a774e1"; 1614 reg = <0 0xe6ef3000 0 0x1000>; 1615 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1616 clocks = <&cpg CPG_MOD 808>; 1617 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1618 resets = <&cpg 808>; 1619 renesas,id = <3>; 1620 status = "disabled"; 1621 1622 ports { 1623 #address-cells = <1>; 1624 #size-cells = <0>; 1625 1626 port@1 { 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 1630 reg = <1>; 1631 1632 vin3csi20: endpoint@0 { 1633 reg = <0>; 1634 remote-endpoint = <&csi20vin3>; 1635 }; 1636 vin3csi40: endpoint@2 { 1637 reg = <2>; 1638 remote-endpoint = <&csi40vin3>; 1639 }; 1640 }; 1641 }; 1642 }; 1643 1644 vin4: video@e6ef4000 { 1645 compatible = "renesas,vin-r8a774e1"; 1646 reg = <0 0xe6ef4000 0 0x1000>; 1647 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1648 clocks = <&cpg CPG_MOD 807>; 1649 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1650 resets = <&cpg 807>; 1651 renesas,id = <4>; 1652 status = "disabled"; 1653 1654 ports { 1655 #address-cells = <1>; 1656 #size-cells = <0>; 1657 1658 port@1 { 1659 #address-cells = <1>; 1660 #size-cells = <0>; 1661 1662 reg = <1>; 1663 1664 vin4csi20: endpoint@0 { 1665 reg = <0>; 1666 remote-endpoint = <&csi20vin4>; 1667 }; 1668 }; 1669 }; 1670 }; 1671 1672 vin5: video@e6ef5000 { 1673 compatible = "renesas,vin-r8a774e1"; 1674 reg = <0 0xe6ef5000 0 0x1000>; 1675 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1676 clocks = <&cpg CPG_MOD 806>; 1677 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1678 resets = <&cpg 806>; 1679 renesas,id = <5>; 1680 status = "disabled"; 1681 1682 ports { 1683 #address-cells = <1>; 1684 #size-cells = <0>; 1685 1686 port@1 { 1687 #address-cells = <1>; 1688 #size-cells = <0>; 1689 1690 reg = <1>; 1691 1692 vin5csi20: endpoint@0 { 1693 reg = <0>; 1694 remote-endpoint = <&csi20vin5>; 1695 }; 1696 }; 1697 }; 1698 }; 1699 1700 vin6: video@e6ef6000 { 1701 compatible = "renesas,vin-r8a774e1"; 1702 reg = <0 0xe6ef6000 0 0x1000>; 1703 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1704 clocks = <&cpg CPG_MOD 805>; 1705 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1706 resets = <&cpg 805>; 1707 renesas,id = <6>; 1708 status = "disabled"; 1709 1710 ports { 1711 #address-cells = <1>; 1712 #size-cells = <0>; 1713 1714 port@1 { 1715 #address-cells = <1>; 1716 #size-cells = <0>; 1717 1718 reg = <1>; 1719 1720 vin6csi20: endpoint@0 { 1721 reg = <0>; 1722 remote-endpoint = <&csi20vin6>; 1723 }; 1724 }; 1725 }; 1726 }; 1727 1728 vin7: video@e6ef7000 { 1729 compatible = "renesas,vin-r8a774e1"; 1730 reg = <0 0xe6ef7000 0 0x1000>; 1731 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 1732 clocks = <&cpg CPG_MOD 804>; 1733 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1734 resets = <&cpg 804>; 1735 renesas,id = <7>; 1736 status = "disabled"; 1737 1738 ports { 1739 #address-cells = <1>; 1740 #size-cells = <0>; 1741 1742 port@1 { 1743 #address-cells = <1>; 1744 #size-cells = <0>; 1745 1746 reg = <1>; 1747 1748 vin7csi20: endpoint@0 { 1749 reg = <0>; 1750 remote-endpoint = <&csi20vin7>; 1751 }; 1752 }; 1753 }; 1754 }; 1755 1756 rcar_sound: sound@ec500000 { 1757 /* 1758 * #sound-dai-cells is required 1759 * 1760 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1761 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1762 */ 1763 /* 1764 * #clock-cells is required for audio_clkout0/1/2/3 1765 * 1766 * clkout : #clock-cells = <0>; <&rcar_sound>; 1767 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1768 */ 1769 compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3"; 1770 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1771 <0 0xec5a0000 0 0x100>, /* ADG */ 1772 <0 0xec540000 0 0x1000>, /* SSIU */ 1773 <0 0xec541000 0 0x280>, /* SSI */ 1774 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1775 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1776 1777 clocks = <&cpg CPG_MOD 1005>, 1778 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1779 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1780 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1781 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1782 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1783 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1784 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1785 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1786 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1787 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1788 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1789 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1790 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1791 <&audio_clk_a>, <&audio_clk_b>, 1792 <&audio_clk_c>, 1793 <&cpg CPG_CORE R8A774E1_CLK_S0D4>; 1794 clock-names = "ssi-all", 1795 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1796 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1797 "ssi.1", "ssi.0", 1798 "src.9", "src.8", "src.7", "src.6", 1799 "src.5", "src.4", "src.3", "src.2", 1800 "src.1", "src.0", 1801 "mix.1", "mix.0", 1802 "ctu.1", "ctu.0", 1803 "dvc.0", "dvc.1", 1804 "clk_a", "clk_b", "clk_c", "clk_i"; 1805 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1806 resets = <&cpg 1005>, 1807 <&cpg 1006>, <&cpg 1007>, 1808 <&cpg 1008>, <&cpg 1009>, 1809 <&cpg 1010>, <&cpg 1011>, 1810 <&cpg 1012>, <&cpg 1013>, 1811 <&cpg 1014>, <&cpg 1015>; 1812 reset-names = "ssi-all", 1813 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1814 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1815 "ssi.1", "ssi.0"; 1816 status = "disabled"; 1817 1818 rcar_sound,dvc { 1819 dvc0: dvc-0 { 1820 dmas = <&audma1 0xbc>; 1821 dma-names = "tx"; 1822 }; 1823 dvc1: dvc-1 { 1824 dmas = <&audma1 0xbe>; 1825 dma-names = "tx"; 1826 }; 1827 }; 1828 1829 rcar_sound,mix { 1830 mix0: mix-0 { }; 1831 mix1: mix-1 { }; 1832 }; 1833 1834 rcar_sound,ctu { 1835 ctu00: ctu-0 { }; 1836 ctu01: ctu-1 { }; 1837 ctu02: ctu-2 { }; 1838 ctu03: ctu-3 { }; 1839 ctu10: ctu-4 { }; 1840 ctu11: ctu-5 { }; 1841 ctu12: ctu-6 { }; 1842 ctu13: ctu-7 { }; 1843 }; 1844 1845 rcar_sound,src { 1846 src0: src-0 { 1847 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1848 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1849 dma-names = "rx", "tx"; 1850 }; 1851 src1: src-1 { 1852 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1853 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1854 dma-names = "rx", "tx"; 1855 }; 1856 src2: src-2 { 1857 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1858 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1859 dma-names = "rx", "tx"; 1860 }; 1861 src3: src-3 { 1862 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1863 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1864 dma-names = "rx", "tx"; 1865 }; 1866 src4: src-4 { 1867 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1868 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1869 dma-names = "rx", "tx"; 1870 }; 1871 src5: src-5 { 1872 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1873 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1874 dma-names = "rx", "tx"; 1875 }; 1876 src6: src-6 { 1877 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1878 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1879 dma-names = "rx", "tx"; 1880 }; 1881 src7: src-7 { 1882 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1883 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1884 dma-names = "rx", "tx"; 1885 }; 1886 src8: src-8 { 1887 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1888 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1889 dma-names = "rx", "tx"; 1890 }; 1891 src9: src-9 { 1892 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1893 dmas = <&audma0 0x97>, <&audma1 0xba>; 1894 dma-names = "rx", "tx"; 1895 }; 1896 }; 1897 1898 rcar_sound,ssiu { 1899 ssiu00: ssiu-0 { 1900 dmas = <&audma0 0x15>, <&audma1 0x16>; 1901 dma-names = "rx", "tx"; 1902 }; 1903 ssiu01: ssiu-1 { 1904 dmas = <&audma0 0x35>, <&audma1 0x36>; 1905 dma-names = "rx", "tx"; 1906 }; 1907 ssiu02: ssiu-2 { 1908 dmas = <&audma0 0x37>, <&audma1 0x38>; 1909 dma-names = "rx", "tx"; 1910 }; 1911 ssiu03: ssiu-3 { 1912 dmas = <&audma0 0x47>, <&audma1 0x48>; 1913 dma-names = "rx", "tx"; 1914 }; 1915 ssiu04: ssiu-4 { 1916 dmas = <&audma0 0x3F>, <&audma1 0x40>; 1917 dma-names = "rx", "tx"; 1918 }; 1919 ssiu05: ssiu-5 { 1920 dmas = <&audma0 0x43>, <&audma1 0x44>; 1921 dma-names = "rx", "tx"; 1922 }; 1923 ssiu06: ssiu-6 { 1924 dmas = <&audma0 0x4F>, <&audma1 0x50>; 1925 dma-names = "rx", "tx"; 1926 }; 1927 ssiu07: ssiu-7 { 1928 dmas = <&audma0 0x53>, <&audma1 0x54>; 1929 dma-names = "rx", "tx"; 1930 }; 1931 ssiu10: ssiu-8 { 1932 dmas = <&audma0 0x49>, <&audma1 0x4a>; 1933 dma-names = "rx", "tx"; 1934 }; 1935 ssiu11: ssiu-9 { 1936 dmas = <&audma0 0x4B>, <&audma1 0x4C>; 1937 dma-names = "rx", "tx"; 1938 }; 1939 ssiu12: ssiu-10 { 1940 dmas = <&audma0 0x57>, <&audma1 0x58>; 1941 dma-names = "rx", "tx"; 1942 }; 1943 ssiu13: ssiu-11 { 1944 dmas = <&audma0 0x59>, <&audma1 0x5A>; 1945 dma-names = "rx", "tx"; 1946 }; 1947 ssiu14: ssiu-12 { 1948 dmas = <&audma0 0x5F>, <&audma1 0x60>; 1949 dma-names = "rx", "tx"; 1950 }; 1951 ssiu15: ssiu-13 { 1952 dmas = <&audma0 0xC3>, <&audma1 0xC4>; 1953 dma-names = "rx", "tx"; 1954 }; 1955 ssiu16: ssiu-14 { 1956 dmas = <&audma0 0xC7>, <&audma1 0xC8>; 1957 dma-names = "rx", "tx"; 1958 }; 1959 ssiu17: ssiu-15 { 1960 dmas = <&audma0 0xCB>, <&audma1 0xCC>; 1961 dma-names = "rx", "tx"; 1962 }; 1963 ssiu20: ssiu-16 { 1964 dmas = <&audma0 0x63>, <&audma1 0x64>; 1965 dma-names = "rx", "tx"; 1966 }; 1967 ssiu21: ssiu-17 { 1968 dmas = <&audma0 0x67>, <&audma1 0x68>; 1969 dma-names = "rx", "tx"; 1970 }; 1971 ssiu22: ssiu-18 { 1972 dmas = <&audma0 0x6B>, <&audma1 0x6C>; 1973 dma-names = "rx", "tx"; 1974 }; 1975 ssiu23: ssiu-19 { 1976 dmas = <&audma0 0x6D>, <&audma1 0x6E>; 1977 dma-names = "rx", "tx"; 1978 }; 1979 ssiu24: ssiu-20 { 1980 dmas = <&audma0 0xCF>, <&audma1 0xCE>; 1981 dma-names = "rx", "tx"; 1982 }; 1983 ssiu25: ssiu-21 { 1984 dmas = <&audma0 0xEB>, <&audma1 0xEC>; 1985 dma-names = "rx", "tx"; 1986 }; 1987 ssiu26: ssiu-22 { 1988 dmas = <&audma0 0xED>, <&audma1 0xEE>; 1989 dma-names = "rx", "tx"; 1990 }; 1991 ssiu27: ssiu-23 { 1992 dmas = <&audma0 0xEF>, <&audma1 0xF0>; 1993 dma-names = "rx", "tx"; 1994 }; 1995 ssiu30: ssiu-24 { 1996 dmas = <&audma0 0x6f>, <&audma1 0x70>; 1997 dma-names = "rx", "tx"; 1998 }; 1999 ssiu31: ssiu-25 { 2000 dmas = <&audma0 0x21>, <&audma1 0x22>; 2001 dma-names = "rx", "tx"; 2002 }; 2003 ssiu32: ssiu-26 { 2004 dmas = <&audma0 0x23>, <&audma1 0x24>; 2005 dma-names = "rx", "tx"; 2006 }; 2007 ssiu33: ssiu-27 { 2008 dmas = <&audma0 0x25>, <&audma1 0x26>; 2009 dma-names = "rx", "tx"; 2010 }; 2011 ssiu34: ssiu-28 { 2012 dmas = <&audma0 0x27>, <&audma1 0x28>; 2013 dma-names = "rx", "tx"; 2014 }; 2015 ssiu35: ssiu-29 { 2016 dmas = <&audma0 0x29>, <&audma1 0x2A>; 2017 dma-names = "rx", "tx"; 2018 }; 2019 ssiu36: ssiu-30 { 2020 dmas = <&audma0 0x2B>, <&audma1 0x2C>; 2021 dma-names = "rx", "tx"; 2022 }; 2023 ssiu37: ssiu-31 { 2024 dmas = <&audma0 0x2D>, <&audma1 0x2E>; 2025 dma-names = "rx", "tx"; 2026 }; 2027 ssiu40: ssiu-32 { 2028 dmas = <&audma0 0x71>, <&audma1 0x72>; 2029 dma-names = "rx", "tx"; 2030 }; 2031 ssiu41: ssiu-33 { 2032 dmas = <&audma0 0x17>, <&audma1 0x18>; 2033 dma-names = "rx", "tx"; 2034 }; 2035 ssiu42: ssiu-34 { 2036 dmas = <&audma0 0x19>, <&audma1 0x1A>; 2037 dma-names = "rx", "tx"; 2038 }; 2039 ssiu43: ssiu-35 { 2040 dmas = <&audma0 0x1B>, <&audma1 0x1C>; 2041 dma-names = "rx", "tx"; 2042 }; 2043 ssiu44: ssiu-36 { 2044 dmas = <&audma0 0x1D>, <&audma1 0x1E>; 2045 dma-names = "rx", "tx"; 2046 }; 2047 ssiu45: ssiu-37 { 2048 dmas = <&audma0 0x1F>, <&audma1 0x20>; 2049 dma-names = "rx", "tx"; 2050 }; 2051 ssiu46: ssiu-38 { 2052 dmas = <&audma0 0x31>, <&audma1 0x32>; 2053 dma-names = "rx", "tx"; 2054 }; 2055 ssiu47: ssiu-39 { 2056 dmas = <&audma0 0x33>, <&audma1 0x34>; 2057 dma-names = "rx", "tx"; 2058 }; 2059 ssiu50: ssiu-40 { 2060 dmas = <&audma0 0x73>, <&audma1 0x74>; 2061 dma-names = "rx", "tx"; 2062 }; 2063 ssiu60: ssiu-41 { 2064 dmas = <&audma0 0x75>, <&audma1 0x76>; 2065 dma-names = "rx", "tx"; 2066 }; 2067 ssiu70: ssiu-42 { 2068 dmas = <&audma0 0x79>, <&audma1 0x7a>; 2069 dma-names = "rx", "tx"; 2070 }; 2071 ssiu80: ssiu-43 { 2072 dmas = <&audma0 0x7b>, <&audma1 0x7c>; 2073 dma-names = "rx", "tx"; 2074 }; 2075 ssiu90: ssiu-44 { 2076 dmas = <&audma0 0x7d>, <&audma1 0x7e>; 2077 dma-names = "rx", "tx"; 2078 }; 2079 ssiu91: ssiu-45 { 2080 dmas = <&audma0 0x7F>, <&audma1 0x80>; 2081 dma-names = "rx", "tx"; 2082 }; 2083 ssiu92: ssiu-46 { 2084 dmas = <&audma0 0x81>, <&audma1 0x82>; 2085 dma-names = "rx", "tx"; 2086 }; 2087 ssiu93: ssiu-47 { 2088 dmas = <&audma0 0x83>, <&audma1 0x84>; 2089 dma-names = "rx", "tx"; 2090 }; 2091 ssiu94: ssiu-48 { 2092 dmas = <&audma0 0xA3>, <&audma1 0xA4>; 2093 dma-names = "rx", "tx"; 2094 }; 2095 ssiu95: ssiu-49 { 2096 dmas = <&audma0 0xA5>, <&audma1 0xA6>; 2097 dma-names = "rx", "tx"; 2098 }; 2099 ssiu96: ssiu-50 { 2100 dmas = <&audma0 0xA7>, <&audma1 0xA8>; 2101 dma-names = "rx", "tx"; 2102 }; 2103 ssiu97: ssiu-51 { 2104 dmas = <&audma0 0xA9>, <&audma1 0xAA>; 2105 dma-names = "rx", "tx"; 2106 }; 2107 }; 2108 2109 rcar_sound,ssi { 2110 ssi0: ssi-0 { 2111 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 2112 dmas = <&audma0 0x01>, <&audma1 0x02>; 2113 dma-names = "rx", "tx"; 2114 }; 2115 ssi1: ssi-1 { 2116 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 2117 dmas = <&audma0 0x03>, <&audma1 0x04>; 2118 dma-names = "rx", "tx"; 2119 }; 2120 ssi2: ssi-2 { 2121 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 2122 dmas = <&audma0 0x05>, <&audma1 0x06>; 2123 dma-names = "rx", "tx"; 2124 }; 2125 ssi3: ssi-3 { 2126 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2127 dmas = <&audma0 0x07>, <&audma1 0x08>; 2128 dma-names = "rx", "tx"; 2129 }; 2130 ssi4: ssi-4 { 2131 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 2132 dmas = <&audma0 0x09>, <&audma1 0x0a>; 2133 dma-names = "rx", "tx"; 2134 }; 2135 ssi5: ssi-5 { 2136 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 2137 dmas = <&audma0 0x0b>, <&audma1 0x0c>; 2138 dma-names = "rx", "tx"; 2139 }; 2140 ssi6: ssi-6 { 2141 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 2142 dmas = <&audma0 0x0d>, <&audma1 0x0e>; 2143 dma-names = "rx", "tx"; 2144 }; 2145 ssi7: ssi-7 { 2146 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 2147 dmas = <&audma0 0x0f>, <&audma1 0x10>; 2148 dma-names = "rx", "tx"; 2149 }; 2150 ssi8: ssi-8 { 2151 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 2152 dmas = <&audma0 0x11>, <&audma1 0x12>; 2153 dma-names = "rx", "tx"; 2154 }; 2155 ssi9: ssi-9 { 2156 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 2157 dmas = <&audma0 0x13>, <&audma1 0x14>; 2158 dma-names = "rx", "tx"; 2159 }; 2160 }; 2161 }; 2162 2163 audma0: dma-controller@ec700000 { 2164 compatible = "renesas,dmac-r8a774e1", 2165 "renesas,rcar-dmac"; 2166 reg = <0 0xec700000 0 0x10000>; 2167 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 2168 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2169 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2170 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2171 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2172 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2173 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2174 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2175 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2176 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2177 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2178 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2179 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2180 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2181 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2182 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2183 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 2184 interrupt-names = "error", 2185 "ch0", "ch1", "ch2", "ch3", 2186 "ch4", "ch5", "ch6", "ch7", 2187 "ch8", "ch9", "ch10", "ch11", 2188 "ch12", "ch13", "ch14", "ch15"; 2189 clocks = <&cpg CPG_MOD 502>; 2190 clock-names = "fck"; 2191 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2192 resets = <&cpg 502>; 2193 #dma-cells = <1>; 2194 dma-channels = <16>; 2195 iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, 2196 <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, 2197 <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, 2198 <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, 2199 <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, 2200 <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, 2201 <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, 2202 <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; 2203 }; 2204 2205 audma1: dma-controller@ec720000 { 2206 compatible = "renesas,dmac-r8a774e1", 2207 "renesas,rcar-dmac"; 2208 reg = <0 0xec720000 0 0x10000>; 2209 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 2210 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2211 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2212 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2213 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2214 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2215 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2216 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2217 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2218 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2219 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2220 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 2221 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2222 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 2223 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 2224 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 2225 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 2226 interrupt-names = "error", 2227 "ch0", "ch1", "ch2", "ch3", 2228 "ch4", "ch5", "ch6", "ch7", 2229 "ch8", "ch9", "ch10", "ch11", 2230 "ch12", "ch13", "ch14", "ch15"; 2231 clocks = <&cpg CPG_MOD 501>; 2232 clock-names = "fck"; 2233 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2234 resets = <&cpg 501>; 2235 #dma-cells = <1>; 2236 dma-channels = <16>; 2237 iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, 2238 <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, 2239 <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, 2240 <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, 2241 <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, 2242 <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, 2243 <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, 2244 <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; 2245 }; 2246 2247 xhci0: usb@ee000000 { 2248 compatible = "renesas,xhci-r8a774e1", 2249 "renesas,rcar-gen3-xhci"; 2250 reg = <0 0xee000000 0 0xc00>; 2251 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2252 clocks = <&cpg CPG_MOD 328>; 2253 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2254 resets = <&cpg 328>; 2255 status = "disabled"; 2256 }; 2257 2258 usb3_peri0: usb@ee020000 { 2259 compatible = "renesas,r8a774e1-usb3-peri", 2260 "renesas,rcar-gen3-usb3-peri"; 2261 reg = <0 0xee020000 0 0x400>; 2262 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2263 clocks = <&cpg CPG_MOD 328>; 2264 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2265 resets = <&cpg 328>; 2266 status = "disabled"; 2267 }; 2268 2269 ohci0: usb@ee080000 { 2270 compatible = "generic-ohci"; 2271 reg = <0 0xee080000 0 0x100>; 2272 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2273 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2274 phys = <&usb2_phy0 1>; 2275 phy-names = "usb"; 2276 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2277 resets = <&cpg 703>, <&cpg 704>; 2278 status = "disabled"; 2279 }; 2280 2281 ohci1: usb@ee0a0000 { 2282 compatible = "generic-ohci"; 2283 reg = <0 0xee0a0000 0 0x100>; 2284 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2285 clocks = <&cpg CPG_MOD 702>; 2286 phys = <&usb2_phy1 1>; 2287 phy-names = "usb"; 2288 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2289 resets = <&cpg 702>; 2290 status = "disabled"; 2291 }; 2292 2293 ehci0: usb@ee080100 { 2294 compatible = "generic-ehci"; 2295 reg = <0 0xee080100 0 0x100>; 2296 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2297 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2298 phys = <&usb2_phy0 2>; 2299 phy-names = "usb"; 2300 companion = <&ohci0>; 2301 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2302 resets = <&cpg 703>, <&cpg 704>; 2303 status = "disabled"; 2304 }; 2305 2306 ehci1: usb@ee0a0100 { 2307 compatible = "generic-ehci"; 2308 reg = <0 0xee0a0100 0 0x100>; 2309 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2310 clocks = <&cpg CPG_MOD 702>; 2311 phys = <&usb2_phy1 2>; 2312 phy-names = "usb"; 2313 companion = <&ohci1>; 2314 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2315 resets = <&cpg 702>; 2316 status = "disabled"; 2317 }; 2318 2319 usb2_phy0: usb-phy@ee080200 { 2320 compatible = "renesas,usb2-phy-r8a774e1", 2321 "renesas,rcar-gen3-usb2-phy"; 2322 reg = <0 0xee080200 0 0x700>; 2323 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2324 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2325 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2326 resets = <&cpg 703>, <&cpg 704>; 2327 #phy-cells = <1>; 2328 status = "disabled"; 2329 }; 2330 2331 usb2_phy1: usb-phy@ee0a0200 { 2332 compatible = "renesas,usb2-phy-r8a774e1", 2333 "renesas,rcar-gen3-usb2-phy"; 2334 reg = <0 0xee0a0200 0 0x700>; 2335 clocks = <&cpg CPG_MOD 702>; 2336 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2337 resets = <&cpg 702>; 2338 #phy-cells = <1>; 2339 status = "disabled"; 2340 }; 2341 2342 sdhi0: mmc@ee100000 { 2343 compatible = "renesas,sdhi-r8a774e1", 2344 "renesas,rcar-gen3-sdhi"; 2345 reg = <0 0xee100000 0 0x2000>; 2346 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 2347 clocks = <&cpg CPG_MOD 314>; 2348 max-frequency = <200000000>; 2349 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2350 resets = <&cpg 314>; 2351 iommus = <&ipmmu_ds1 32>; 2352 status = "disabled"; 2353 }; 2354 2355 sdhi1: mmc@ee120000 { 2356 compatible = "renesas,sdhi-r8a774e1", 2357 "renesas,rcar-gen3-sdhi"; 2358 reg = <0 0xee120000 0 0x2000>; 2359 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 2360 clocks = <&cpg CPG_MOD 313>; 2361 max-frequency = <200000000>; 2362 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2363 resets = <&cpg 313>; 2364 iommus = <&ipmmu_ds1 33>; 2365 status = "disabled"; 2366 }; 2367 2368 sdhi2: mmc@ee140000 { 2369 compatible = "renesas,sdhi-r8a774e1", 2370 "renesas,rcar-gen3-sdhi"; 2371 reg = <0 0xee140000 0 0x2000>; 2372 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 2373 clocks = <&cpg CPG_MOD 312>; 2374 max-frequency = <200000000>; 2375 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2376 resets = <&cpg 312>; 2377 iommus = <&ipmmu_ds1 34>; 2378 status = "disabled"; 2379 }; 2380 2381 sdhi3: mmc@ee160000 { 2382 compatible = "renesas,sdhi-r8a774e1", 2383 "renesas,rcar-gen3-sdhi"; 2384 reg = <0 0xee160000 0 0x2000>; 2385 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 2386 clocks = <&cpg CPG_MOD 311>; 2387 max-frequency = <200000000>; 2388 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2389 resets = <&cpg 311>; 2390 iommus = <&ipmmu_ds1 35>; 2391 status = "disabled"; 2392 }; 2393 2394 sata: sata@ee300000 { 2395 compatible = "renesas,sata-r8a774e1", 2396 "renesas,rcar-gen3-sata"; 2397 reg = <0 0xee300000 0 0x200000>; 2398 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2399 clocks = <&cpg CPG_MOD 815>; 2400 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2401 resets = <&cpg 815>; 2402 iommus = <&ipmmu_hc 2>; 2403 status = "disabled"; 2404 }; 2405 2406 gic: interrupt-controller@f1010000 { 2407 compatible = "arm,gic-400"; 2408 #interrupt-cells = <3>; 2409 #address-cells = <0>; 2410 interrupt-controller; 2411 reg = <0x0 0xf1010000 0 0x1000>, 2412 <0x0 0xf1020000 0 0x20000>, 2413 <0x0 0xf1040000 0 0x20000>, 2414 <0x0 0xf1060000 0 0x20000>; 2415 interrupts = <GIC_PPI 9 2416 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2417 clocks = <&cpg CPG_MOD 408>; 2418 clock-names = "clk"; 2419 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2420 resets = <&cpg 408>; 2421 }; 2422 2423 pciec0: pcie@fe000000 { 2424 compatible = "renesas,pcie-r8a774e1", 2425 "renesas,pcie-rcar-gen3"; 2426 reg = <0 0xfe000000 0 0x80000>; 2427 #address-cells = <3>; 2428 #size-cells = <2>; 2429 bus-range = <0x00 0xff>; 2430 device_type = "pci"; 2431 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 2432 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 2433 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 2434 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 2435 /* Map all possible DDR as inbound ranges */ 2436 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2437 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2438 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2439 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2440 #interrupt-cells = <1>; 2441 interrupt-map-mask = <0 0 0 0>; 2442 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2443 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 2444 clock-names = "pcie", "pcie_bus"; 2445 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2446 resets = <&cpg 319>; 2447 status = "disabled"; 2448 }; 2449 2450 pciec1: pcie@ee800000 { 2451 compatible = "renesas,pcie-r8a774e1", 2452 "renesas,pcie-rcar-gen3"; 2453 reg = <0 0xee800000 0 0x80000>; 2454 #address-cells = <3>; 2455 #size-cells = <2>; 2456 bus-range = <0x00 0xff>; 2457 device_type = "pci"; 2458 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, 2459 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, 2460 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, 2461 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 2462 /* Map all possible DDR as inbound ranges */ 2463 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2464 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2465 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2466 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2467 #interrupt-cells = <1>; 2468 interrupt-map-mask = <0 0 0 0>; 2469 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2470 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 2471 clock-names = "pcie", "pcie_bus"; 2472 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2473 resets = <&cpg 318>; 2474 status = "disabled"; 2475 }; 2476 2477 pciec0_ep: pcie-ep@fe000000 { 2478 compatible = "renesas,r8a774e1-pcie-ep", 2479 "renesas,rcar-gen3-pcie-ep"; 2480 reg = <0x0 0xfe000000 0 0x80000>, 2481 <0x0 0xfe100000 0 0x100000>, 2482 <0x0 0xfe200000 0 0x200000>, 2483 <0x0 0x30000000 0 0x8000000>, 2484 <0x0 0x38000000 0 0x8000000>; 2485 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; 2486 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2487 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2488 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2489 clocks = <&cpg CPG_MOD 319>; 2490 clock-names = "pcie"; 2491 resets = <&cpg 319>; 2492 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2493 status = "disabled"; 2494 }; 2495 2496 pciec1_ep: pcie-ep@ee800000 { 2497 compatible = "renesas,r8a774e1-pcie-ep", 2498 "renesas,rcar-gen3-pcie-ep"; 2499 reg = <0x0 0xee800000 0 0x80000>, 2500 <0x0 0xee900000 0 0x100000>, 2501 <0x0 0xeea00000 0 0x200000>, 2502 <0x0 0xc0000000 0 0x8000000>, 2503 <0x0 0xc8000000 0 0x8000000>; 2504 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; 2505 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2506 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2507 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2508 clocks = <&cpg CPG_MOD 318>; 2509 clock-names = "pcie"; 2510 resets = <&cpg 318>; 2511 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2512 status = "disabled"; 2513 }; 2514 2515 vspbc: vsp@fe920000 { 2516 compatible = "renesas,vsp2"; 2517 reg = <0 0xfe920000 0 0x8000>; 2518 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 2519 clocks = <&cpg CPG_MOD 624>; 2520 power-domains = <&sysc R8A774E1_PD_A3VP>; 2521 resets = <&cpg 624>; 2522 2523 renesas,fcp = <&fcpvb1>; 2524 }; 2525 2526 vspbd: vsp@fe960000 { 2527 compatible = "renesas,vsp2"; 2528 reg = <0 0xfe960000 0 0x8000>; 2529 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 2530 clocks = <&cpg CPG_MOD 626>; 2531 power-domains = <&sysc R8A774E1_PD_A3VP>; 2532 resets = <&cpg 626>; 2533 2534 renesas,fcp = <&fcpvb0>; 2535 }; 2536 2537 vspd0: vsp@fea20000 { 2538 compatible = "renesas,vsp2"; 2539 reg = <0 0xfea20000 0 0x5000>; 2540 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 2541 clocks = <&cpg CPG_MOD 623>; 2542 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2543 resets = <&cpg 623>; 2544 2545 renesas,fcp = <&fcpvd0>; 2546 }; 2547 2548 vspd1: vsp@fea28000 { 2549 compatible = "renesas,vsp2"; 2550 reg = <0 0xfea28000 0 0x5000>; 2551 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 2552 clocks = <&cpg CPG_MOD 622>; 2553 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2554 resets = <&cpg 622>; 2555 2556 renesas,fcp = <&fcpvd1>; 2557 }; 2558 2559 vspi0: vsp@fe9a0000 { 2560 compatible = "renesas,vsp2"; 2561 reg = <0 0xfe9a0000 0 0x8000>; 2562 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 2563 clocks = <&cpg CPG_MOD 631>; 2564 power-domains = <&sysc R8A774E1_PD_A3VP>; 2565 resets = <&cpg 631>; 2566 2567 renesas,fcp = <&fcpvi0>; 2568 }; 2569 2570 vspi1: vsp@fe9b0000 { 2571 compatible = "renesas,vsp2"; 2572 reg = <0 0xfe9b0000 0 0x8000>; 2573 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 2574 clocks = <&cpg CPG_MOD 630>; 2575 power-domains = <&sysc R8A774E1_PD_A3VP>; 2576 resets = <&cpg 630>; 2577 2578 renesas,fcp = <&fcpvi1>; 2579 }; 2580 2581 fdp1@fe940000 { 2582 compatible = "renesas,fdp1"; 2583 reg = <0 0xfe940000 0 0x2400>; 2584 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 2585 clocks = <&cpg CPG_MOD 119>; 2586 power-domains = <&sysc R8A774E1_PD_A3VP>; 2587 resets = <&cpg 119>; 2588 renesas,fcp = <&fcpf0>; 2589 }; 2590 2591 fdp1@fe944000 { 2592 compatible = "renesas,fdp1"; 2593 reg = <0 0xfe944000 0 0x2400>; 2594 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 2595 clocks = <&cpg CPG_MOD 118>; 2596 power-domains = <&sysc R8A774E1_PD_A3VP>; 2597 resets = <&cpg 118>; 2598 renesas,fcp = <&fcpf1>; 2599 }; 2600 2601 fcpf0: fcp@fe950000 { 2602 compatible = "renesas,fcpf"; 2603 reg = <0 0xfe950000 0 0x200>; 2604 clocks = <&cpg CPG_MOD 615>; 2605 power-domains = <&sysc R8A774E1_PD_A3VP>; 2606 resets = <&cpg 615>; 2607 }; 2608 2609 fcpf1: fcp@fe951000 { 2610 compatible = "renesas,fcpf"; 2611 reg = <0 0xfe951000 0 0x200>; 2612 clocks = <&cpg CPG_MOD 614>; 2613 power-domains = <&sysc R8A774E1_PD_A3VP>; 2614 resets = <&cpg 614>; 2615 }; 2616 2617 fcpvb0: fcp@fe96f000 { 2618 compatible = "renesas,fcpv"; 2619 reg = <0 0xfe96f000 0 0x200>; 2620 clocks = <&cpg CPG_MOD 607>; 2621 power-domains = <&sysc R8A774E1_PD_A3VP>; 2622 resets = <&cpg 607>; 2623 }; 2624 2625 fcpvb1: fcp@fe92f000 { 2626 compatible = "renesas,fcpv"; 2627 reg = <0 0xfe92f000 0 0x200>; 2628 clocks = <&cpg CPG_MOD 606>; 2629 power-domains = <&sysc R8A774E1_PD_A3VP>; 2630 resets = <&cpg 606>; 2631 }; 2632 2633 fcpvi0: fcp@fe9af000 { 2634 compatible = "renesas,fcpv"; 2635 reg = <0 0xfe9af000 0 0x200>; 2636 clocks = <&cpg CPG_MOD 611>; 2637 power-domains = <&sysc R8A774E1_PD_A3VP>; 2638 resets = <&cpg 611>; 2639 }; 2640 2641 fcpvi1: fcp@fe9bf000 { 2642 compatible = "renesas,fcpv"; 2643 reg = <0 0xfe9bf000 0 0x200>; 2644 clocks = <&cpg CPG_MOD 610>; 2645 power-domains = <&sysc R8A774E1_PD_A3VP>; 2646 resets = <&cpg 610>; 2647 }; 2648 2649 fcpvd0: fcp@fea27000 { 2650 compatible = "renesas,fcpv"; 2651 reg = <0 0xfea27000 0 0x200>; 2652 clocks = <&cpg CPG_MOD 603>; 2653 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2654 resets = <&cpg 603>; 2655 }; 2656 2657 fcpvd1: fcp@fea2f000 { 2658 compatible = "renesas,fcpv"; 2659 reg = <0 0xfea2f000 0 0x200>; 2660 clocks = <&cpg CPG_MOD 602>; 2661 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2662 resets = <&cpg 602>; 2663 }; 2664 2665 csi20: csi2@fea80000 { 2666 compatible = "renesas,r8a774e1-csi2"; 2667 reg = <0 0xfea80000 0 0x10000>; 2668 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2669 clocks = <&cpg CPG_MOD 714>; 2670 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2671 resets = <&cpg 714>; 2672 status = "disabled"; 2673 2674 ports { 2675 #address-cells = <1>; 2676 #size-cells = <0>; 2677 2678 port@1 { 2679 #address-cells = <1>; 2680 #size-cells = <0>; 2681 2682 reg = <1>; 2683 2684 csi20vin0: endpoint@0 { 2685 reg = <0>; 2686 remote-endpoint = <&vin0csi20>; 2687 }; 2688 csi20vin1: endpoint@1 { 2689 reg = <1>; 2690 remote-endpoint = <&vin1csi20>; 2691 }; 2692 csi20vin2: endpoint@2 { 2693 reg = <2>; 2694 remote-endpoint = <&vin2csi20>; 2695 }; 2696 csi20vin3: endpoint@3 { 2697 reg = <3>; 2698 remote-endpoint = <&vin3csi20>; 2699 }; 2700 csi20vin4: endpoint@4 { 2701 reg = <4>; 2702 remote-endpoint = <&vin4csi20>; 2703 }; 2704 csi20vin5: endpoint@5 { 2705 reg = <5>; 2706 remote-endpoint = <&vin5csi20>; 2707 }; 2708 csi20vin6: endpoint@6 { 2709 reg = <6>; 2710 remote-endpoint = <&vin6csi20>; 2711 }; 2712 csi20vin7: endpoint@7 { 2713 reg = <7>; 2714 remote-endpoint = <&vin7csi20>; 2715 }; 2716 }; 2717 }; 2718 }; 2719 2720 csi40: csi2@feaa0000 { 2721 compatible = "renesas,r8a774e1-csi2"; 2722 reg = <0 0xfeaa0000 0 0x10000>; 2723 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2724 clocks = <&cpg CPG_MOD 716>; 2725 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2726 resets = <&cpg 716>; 2727 status = "disabled"; 2728 2729 ports { 2730 #address-cells = <1>; 2731 #size-cells = <0>; 2732 2733 port@1 { 2734 #address-cells = <1>; 2735 #size-cells = <0>; 2736 2737 reg = <1>; 2738 2739 csi40vin0: endpoint@0 { 2740 reg = <0>; 2741 remote-endpoint = <&vin0csi40>; 2742 }; 2743 csi40vin1: endpoint@1 { 2744 reg = <1>; 2745 remote-endpoint = <&vin1csi40>; 2746 }; 2747 csi40vin2: endpoint@2 { 2748 reg = <2>; 2749 remote-endpoint = <&vin2csi40>; 2750 }; 2751 csi40vin3: endpoint@3 { 2752 reg = <3>; 2753 remote-endpoint = <&vin3csi40>; 2754 }; 2755 }; 2756 }; 2757 }; 2758 2759 hdmi0: hdmi@fead0000 { 2760 compatible = "renesas,r8a774e1-hdmi", 2761 "renesas,rcar-gen3-hdmi"; 2762 reg = <0 0xfead0000 0 0x10000>; 2763 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 2764 clocks = <&cpg CPG_MOD 729>, 2765 <&cpg CPG_CORE R8A774E1_CLK_HDMI>; 2766 clock-names = "iahb", "isfr"; 2767 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2768 resets = <&cpg 729>; 2769 status = "disabled"; 2770 2771 ports { 2772 #address-cells = <1>; 2773 #size-cells = <0>; 2774 2775 port@0 { 2776 reg = <0>; 2777 dw_hdmi0_in: endpoint { 2778 remote-endpoint = <&du_out_hdmi0>; 2779 }; 2780 }; 2781 port@1 { 2782 reg = <1>; 2783 }; 2784 port@2 { 2785 /* HDMI sound */ 2786 reg = <2>; 2787 }; 2788 }; 2789 }; 2790 2791 du: display@feb00000 { 2792 compatible = "renesas,du-r8a774e1"; 2793 reg = <0 0xfeb00000 0 0x80000>; 2794 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2795 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2796 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; 2797 clocks = <&cpg CPG_MOD 724>, 2798 <&cpg CPG_MOD 723>, 2799 <&cpg CPG_MOD 721>; 2800 clock-names = "du.0", "du.1", "du.3"; 2801 resets = <&cpg 724>, <&cpg 722>; 2802 reset-names = "du.0", "du.3"; 2803 status = "disabled"; 2804 2805 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; 2806 2807 ports { 2808 #address-cells = <1>; 2809 #size-cells = <0>; 2810 2811 port@0 { 2812 reg = <0>; 2813 du_out_rgb: endpoint { 2814 }; 2815 }; 2816 port@1 { 2817 reg = <1>; 2818 du_out_hdmi0: endpoint { 2819 remote-endpoint = <&dw_hdmi0_in>; 2820 }; 2821 }; 2822 port@2 { 2823 reg = <2>; 2824 du_out_lvds0: endpoint { 2825 remote-endpoint = <&lvds0_in>; 2826 }; 2827 }; 2828 }; 2829 }; 2830 2831 lvds0: lvds@feb90000 { 2832 compatible = "renesas,r8a774e1-lvds"; 2833 reg = <0 0xfeb90000 0 0x14>; 2834 clocks = <&cpg CPG_MOD 727>; 2835 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2836 resets = <&cpg 727>; 2837 status = "disabled"; 2838 2839 ports { 2840 #address-cells = <1>; 2841 #size-cells = <0>; 2842 2843 port@0 { 2844 reg = <0>; 2845 lvds0_in: endpoint { 2846 remote-endpoint = <&du_out_lvds0>; 2847 }; 2848 }; 2849 port@1 { 2850 reg = <1>; 2851 lvds0_out: endpoint { 2852 }; 2853 }; 2854 }; 2855 }; 2856 2857 prr: chipid@fff00044 { 2858 compatible = "renesas,prr"; 2859 reg = <0 0xfff00044 0 4>; 2860 }; 2861 }; 2862 2863 thermal-zones { 2864 sensor_thermal1: sensor-thermal1 { 2865 polling-delay-passive = <250>; 2866 polling-delay = <1000>; 2867 thermal-sensors = <&tsc 0>; 2868 sustainable-power = <6313>; 2869 2870 trips { 2871 sensor1_crit: sensor1-crit { 2872 temperature = <120000>; 2873 hysteresis = <1000>; 2874 type = "critical"; 2875 }; 2876 }; 2877 }; 2878 2879 sensor_thermal2: sensor-thermal2 { 2880 polling-delay-passive = <250>; 2881 polling-delay = <1000>; 2882 thermal-sensors = <&tsc 1>; 2883 sustainable-power = <6313>; 2884 2885 trips { 2886 sensor2_crit: sensor2-crit { 2887 temperature = <120000>; 2888 hysteresis = <1000>; 2889 type = "critical"; 2890 }; 2891 }; 2892 }; 2893 2894 sensor_thermal3: sensor-thermal3 { 2895 polling-delay-passive = <250>; 2896 polling-delay = <1000>; 2897 thermal-sensors = <&tsc 2>; 2898 sustainable-power = <6313>; 2899 2900 trips { 2901 target: trip-point1 { 2902 temperature = <100000>; 2903 hysteresis = <1000>; 2904 type = "passive"; 2905 }; 2906 2907 sensor3_crit: sensor3-crit { 2908 temperature = <120000>; 2909 hysteresis = <1000>; 2910 type = "critical"; 2911 }; 2912 }; 2913 2914 cooling-maps { 2915 map0 { 2916 trip = <&target>; 2917 cooling-device = <&a57_0 0 2>; 2918 contribution = <1024>; 2919 }; 2920 2921 map1 { 2922 trip = <&target>; 2923 cooling-device = <&a53_0 0 2>; 2924 contribution = <1024>; 2925 }; 2926 }; 2927 }; 2928 }; 2929 2930 timer { 2931 compatible = "arm,armv8-timer"; 2932 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2933 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2934 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2935 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2936 }; 2937 2938 /* External USB clocks - can be overridden by the board */ 2939 usb3s0_clk: usb3s0 { 2940 compatible = "fixed-clock"; 2941 #clock-cells = <0>; 2942 clock-frequency = <0>; 2943 }; 2944 2945 usb_extal_clk: usb_extal { 2946 compatible = "fixed-clock"; 2947 #clock-cells = <0>; 2948 clock-frequency = <0>; 2949 }; 2950}; 2951