1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774e1 SoC 4 * 5 * Copyright (C) 2020 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r8a774e1-cpg-mssr.h> 11#include <dt-bindings/power/r8a774e1-sysc.h> 12 13#define CPG_AUDIO_CLK_I R8A774E1_CLK_S0D4 14 15/ { 16 compatible = "renesas,r8a774e1"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 /* 21 * The external audio clocks are configured as 0 Hz fixed frequency 22 * clocks by default. 23 * Boards that provide audio clocks should override them. 24 */ 25 audio_clk_a: audio_clk_a { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <0>; 29 }; 30 31 audio_clk_c: audio_clk_c { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 cluster0_opp: opp_table0 { 38 compatible = "operating-points-v2"; 39 opp-shared; 40 41 opp-500000000 { 42 opp-hz = /bits/ 64 <500000000>; 43 opp-microvolt = <820000>; 44 clock-latency-ns = <300000>; 45 }; 46 opp-1000000000 { 47 opp-hz = /bits/ 64 <1000000000>; 48 opp-microvolt = <820000>; 49 clock-latency-ns = <300000>; 50 }; 51 opp-1500000000 { 52 opp-hz = /bits/ 64 <1500000000>; 53 opp-microvolt = <820000>; 54 clock-latency-ns = <300000>; 55 opp-suspend; 56 }; 57 }; 58 59 cluster1_opp: opp_table1 { 60 compatible = "operating-points-v2"; 61 opp-shared; 62 63 opp-800000000 { 64 opp-hz = /bits/ 64 <800000000>; 65 opp-microvolt = <820000>; 66 clock-latency-ns = <300000>; 67 }; 68 opp-1000000000 { 69 opp-hz = /bits/ 64 <1000000000>; 70 opp-microvolt = <820000>; 71 clock-latency-ns = <300000>; 72 }; 73 opp-1200000000 { 74 opp-hz = /bits/ 64 <1200000000>; 75 opp-microvolt = <820000>; 76 clock-latency-ns = <300000>; 77 }; 78 }; 79 80 cpus { 81 #address-cells = <1>; 82 #size-cells = <0>; 83 84 cpu-map { 85 cluster0 { 86 core0 { 87 cpu = <&a57_0>; 88 }; 89 core1 { 90 cpu = <&a57_1>; 91 }; 92 core2 { 93 cpu = <&a57_2>; 94 }; 95 core3 { 96 cpu = <&a57_3>; 97 }; 98 }; 99 100 cluster1 { 101 core0 { 102 cpu = <&a53_0>; 103 }; 104 core1 { 105 cpu = <&a53_1>; 106 }; 107 core2 { 108 cpu = <&a53_2>; 109 }; 110 core3 { 111 cpu = <&a53_3>; 112 }; 113 }; 114 }; 115 116 a57_0: cpu@0 { 117 compatible = "arm,cortex-a57"; 118 reg = <0x0>; 119 device_type = "cpu"; 120 power-domains = <&sysc R8A774E1_PD_CA57_CPU0>; 121 next-level-cache = <&L2_CA57>; 122 enable-method = "psci"; 123 dynamic-power-coefficient = <854>; 124 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 125 operating-points-v2 = <&cluster0_opp>; 126 capacity-dmips-mhz = <1024>; 127 #cooling-cells = <2>; 128 }; 129 130 a57_1: cpu@1 { 131 compatible = "arm,cortex-a57"; 132 reg = <0x1>; 133 device_type = "cpu"; 134 power-domains = <&sysc R8A774E1_PD_CA57_CPU1>; 135 next-level-cache = <&L2_CA57>; 136 enable-method = "psci"; 137 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 138 operating-points-v2 = <&cluster0_opp>; 139 capacity-dmips-mhz = <1024>; 140 #cooling-cells = <2>; 141 }; 142 143 a57_2: cpu@2 { 144 compatible = "arm,cortex-a57"; 145 reg = <0x2>; 146 device_type = "cpu"; 147 power-domains = <&sysc R8A774E1_PD_CA57_CPU2>; 148 next-level-cache = <&L2_CA57>; 149 enable-method = "psci"; 150 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 151 operating-points-v2 = <&cluster0_opp>; 152 capacity-dmips-mhz = <1024>; 153 #cooling-cells = <2>; 154 }; 155 156 a57_3: cpu@3 { 157 compatible = "arm,cortex-a57"; 158 reg = <0x3>; 159 device_type = "cpu"; 160 power-domains = <&sysc R8A774E1_PD_CA57_CPU3>; 161 next-level-cache = <&L2_CA57>; 162 enable-method = "psci"; 163 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 164 operating-points-v2 = <&cluster0_opp>; 165 capacity-dmips-mhz = <1024>; 166 #cooling-cells = <2>; 167 }; 168 169 a53_0: cpu@100 { 170 compatible = "arm,cortex-a53"; 171 reg = <0x100>; 172 device_type = "cpu"; 173 power-domains = <&sysc R8A774E1_PD_CA53_CPU0>; 174 next-level-cache = <&L2_CA53>; 175 enable-method = "psci"; 176 #cooling-cells = <2>; 177 dynamic-power-coefficient = <277>; 178 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 179 operating-points-v2 = <&cluster1_opp>; 180 capacity-dmips-mhz = <535>; 181 }; 182 183 a53_1: cpu@101 { 184 compatible = "arm,cortex-a53"; 185 reg = <0x101>; 186 device_type = "cpu"; 187 power-domains = <&sysc R8A774E1_PD_CA53_CPU1>; 188 next-level-cache = <&L2_CA53>; 189 enable-method = "psci"; 190 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 191 operating-points-v2 = <&cluster1_opp>; 192 capacity-dmips-mhz = <535>; 193 }; 194 195 a53_2: cpu@102 { 196 compatible = "arm,cortex-a53"; 197 reg = <0x102>; 198 device_type = "cpu"; 199 power-domains = <&sysc R8A774E1_PD_CA53_CPU2>; 200 next-level-cache = <&L2_CA53>; 201 enable-method = "psci"; 202 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 203 operating-points-v2 = <&cluster1_opp>; 204 capacity-dmips-mhz = <535>; 205 }; 206 207 a53_3: cpu@103 { 208 compatible = "arm,cortex-a53"; 209 reg = <0x103>; 210 device_type = "cpu"; 211 power-domains = <&sysc R8A774E1_PD_CA53_CPU3>; 212 next-level-cache = <&L2_CA53>; 213 enable-method = "psci"; 214 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 215 operating-points-v2 = <&cluster1_opp>; 216 capacity-dmips-mhz = <535>; 217 }; 218 219 L2_CA57: cache-controller-0 { 220 compatible = "cache"; 221 power-domains = <&sysc R8A774E1_PD_CA57_SCU>; 222 cache-unified; 223 cache-level = <2>; 224 }; 225 226 L2_CA53: cache-controller-1 { 227 compatible = "cache"; 228 power-domains = <&sysc R8A774E1_PD_CA53_SCU>; 229 cache-unified; 230 cache-level = <2>; 231 }; 232 }; 233 234 extal_clk: extal { 235 compatible = "fixed-clock"; 236 #clock-cells = <0>; 237 /* This value must be overridden by the board */ 238 clock-frequency = <0>; 239 }; 240 241 extalr_clk: extalr { 242 compatible = "fixed-clock"; 243 #clock-cells = <0>; 244 /* This value must be overridden by the board */ 245 clock-frequency = <0>; 246 }; 247 248 /* External PCIe clock - can be overridden by the board */ 249 pcie_bus_clk: pcie_bus { 250 compatible = "fixed-clock"; 251 #clock-cells = <0>; 252 clock-frequency = <0>; 253 }; 254 255 pmu_a53 { 256 compatible = "arm,cortex-a53-pmu"; 257 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 258 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 259 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 260 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 261 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 262 }; 263 264 pmu_a57 { 265 compatible = "arm,cortex-a57-pmu"; 266 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 267 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 268 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 269 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 270 interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>; 271 }; 272 273 psci { 274 compatible = "arm,psci-1.0", "arm,psci-0.2"; 275 method = "smc"; 276 }; 277 278 /* External SCIF clock - to be overridden by boards that provide it */ 279 scif_clk: scif { 280 compatible = "fixed-clock"; 281 #clock-cells = <0>; 282 clock-frequency = <0>; 283 }; 284 285 soc { 286 compatible = "simple-bus"; 287 interrupt-parent = <&gic>; 288 #address-cells = <2>; 289 #size-cells = <2>; 290 ranges; 291 292 rwdt: watchdog@e6020000 { 293 reg = <0 0xe6020000 0 0x0c>; 294 status = "disabled"; 295 296 /* placeholder */ 297 }; 298 299 gpio0: gpio@e6050000 { 300 compatible = "renesas,gpio-r8a774e1", 301 "renesas,rcar-gen3-gpio"; 302 reg = <0 0xe6050000 0 0x50>; 303 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 304 #gpio-cells = <2>; 305 gpio-controller; 306 gpio-ranges = <&pfc 0 0 16>; 307 #interrupt-cells = <2>; 308 interrupt-controller; 309 clocks = <&cpg CPG_MOD 912>; 310 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 311 resets = <&cpg 912>; 312 }; 313 314 gpio1: gpio@e6051000 { 315 compatible = "renesas,gpio-r8a774e1", 316 "renesas,rcar-gen3-gpio"; 317 reg = <0 0xe6051000 0 0x50>; 318 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 319 #gpio-cells = <2>; 320 gpio-controller; 321 gpio-ranges = <&pfc 0 32 29>; 322 #interrupt-cells = <2>; 323 interrupt-controller; 324 clocks = <&cpg CPG_MOD 911>; 325 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 326 resets = <&cpg 911>; 327 }; 328 329 gpio2: gpio@e6052000 { 330 compatible = "renesas,gpio-r8a774e1", 331 "renesas,rcar-gen3-gpio"; 332 reg = <0 0xe6052000 0 0x50>; 333 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 334 #gpio-cells = <2>; 335 gpio-controller; 336 gpio-ranges = <&pfc 0 64 15>; 337 #interrupt-cells = <2>; 338 interrupt-controller; 339 clocks = <&cpg CPG_MOD 910>; 340 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 341 resets = <&cpg 910>; 342 }; 343 344 gpio3: gpio@e6053000 { 345 compatible = "renesas,gpio-r8a774e1", 346 "renesas,rcar-gen3-gpio"; 347 reg = <0 0xe6053000 0 0x50>; 348 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 349 #gpio-cells = <2>; 350 gpio-controller; 351 gpio-ranges = <&pfc 0 96 16>; 352 #interrupt-cells = <2>; 353 interrupt-controller; 354 clocks = <&cpg CPG_MOD 909>; 355 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 356 resets = <&cpg 909>; 357 }; 358 359 gpio4: gpio@e6054000 { 360 compatible = "renesas,gpio-r8a774e1", 361 "renesas,rcar-gen3-gpio"; 362 reg = <0 0xe6054000 0 0x50>; 363 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 364 #gpio-cells = <2>; 365 gpio-controller; 366 gpio-ranges = <&pfc 0 128 18>; 367 #interrupt-cells = <2>; 368 interrupt-controller; 369 clocks = <&cpg CPG_MOD 908>; 370 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 371 resets = <&cpg 908>; 372 }; 373 374 gpio5: gpio@e6055000 { 375 compatible = "renesas,gpio-r8a774e1", 376 "renesas,rcar-gen3-gpio"; 377 reg = <0 0xe6055000 0 0x50>; 378 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 379 #gpio-cells = <2>; 380 gpio-controller; 381 gpio-ranges = <&pfc 0 160 26>; 382 #interrupt-cells = <2>; 383 interrupt-controller; 384 clocks = <&cpg CPG_MOD 907>; 385 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 386 resets = <&cpg 907>; 387 }; 388 389 gpio6: gpio@e6055400 { 390 compatible = "renesas,gpio-r8a774e1", 391 "renesas,rcar-gen3-gpio"; 392 reg = <0 0xe6055400 0 0x50>; 393 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 394 #gpio-cells = <2>; 395 gpio-controller; 396 gpio-ranges = <&pfc 0 192 32>; 397 #interrupt-cells = <2>; 398 interrupt-controller; 399 clocks = <&cpg CPG_MOD 906>; 400 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 401 resets = <&cpg 906>; 402 }; 403 404 gpio7: gpio@e6055800 { 405 compatible = "renesas,gpio-r8a774e1", 406 "renesas,rcar-gen3-gpio"; 407 reg = <0 0xe6055800 0 0x50>; 408 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 409 #gpio-cells = <2>; 410 gpio-controller; 411 gpio-ranges = <&pfc 0 224 4>; 412 #interrupt-cells = <2>; 413 interrupt-controller; 414 clocks = <&cpg CPG_MOD 905>; 415 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 416 resets = <&cpg 905>; 417 }; 418 419 pfc: pin-controller@e6060000 { 420 compatible = "renesas,pfc-r8a774e1"; 421 reg = <0 0xe6060000 0 0x50c>; 422 }; 423 424 cmt0: timer@e60f0000 { 425 compatible = "renesas,r8a774e1-cmt0", 426 "renesas,rcar-gen3-cmt0"; 427 reg = <0 0xe60f0000 0 0x1004>; 428 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&cpg CPG_MOD 303>; 431 clock-names = "fck"; 432 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 433 resets = <&cpg 303>; 434 status = "disabled"; 435 }; 436 437 cmt1: timer@e6130000 { 438 compatible = "renesas,r8a774e1-cmt1", 439 "renesas,rcar-gen3-cmt1"; 440 reg = <0 0xe6130000 0 0x1004>; 441 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&cpg CPG_MOD 302>; 450 clock-names = "fck"; 451 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 452 resets = <&cpg 302>; 453 status = "disabled"; 454 }; 455 456 cmt2: timer@e6140000 { 457 compatible = "renesas,r8a774e1-cmt1", 458 "renesas,rcar-gen3-cmt1"; 459 reg = <0 0xe6140000 0 0x1004>; 460 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 468 clocks = <&cpg CPG_MOD 301>; 469 clock-names = "fck"; 470 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 471 resets = <&cpg 301>; 472 status = "disabled"; 473 }; 474 475 cmt3: timer@e6148000 { 476 compatible = "renesas,r8a774e1-cmt1", 477 "renesas,rcar-gen3-cmt1"; 478 reg = <0 0xe6148000 0 0x1004>; 479 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&cpg CPG_MOD 300>; 488 clock-names = "fck"; 489 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 490 resets = <&cpg 300>; 491 status = "disabled"; 492 }; 493 494 cpg: clock-controller@e6150000 { 495 compatible = "renesas,r8a774e1-cpg-mssr"; 496 reg = <0 0xe6150000 0 0x1000>; 497 clocks = <&extal_clk>, <&extalr_clk>; 498 clock-names = "extal", "extalr"; 499 #clock-cells = <2>; 500 #power-domain-cells = <0>; 501 #reset-cells = <1>; 502 }; 503 504 rst: reset-controller@e6160000 { 505 compatible = "renesas,r8a774e1-rst"; 506 reg = <0 0xe6160000 0 0x0200>; 507 }; 508 509 sysc: system-controller@e6180000 { 510 compatible = "renesas,r8a774e1-sysc"; 511 reg = <0 0xe6180000 0 0x0400>; 512 #power-domain-cells = <1>; 513 }; 514 515 tsc: thermal@e6198000 { 516 compatible = "renesas,r8a774e1-thermal"; 517 reg = <0 0xe6198000 0 0x100>, 518 <0 0xe61a0000 0 0x100>, 519 <0 0xe61a8000 0 0x100>; 520 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&cpg CPG_MOD 522>; 524 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 525 resets = <&cpg 522>; 526 #thermal-sensor-cells = <1>; 527 }; 528 529 intc_ex: interrupt-controller@e61c0000 { 530 compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc"; 531 #interrupt-cells = <2>; 532 interrupt-controller; 533 reg = <0 0xe61c0000 0 0x200>; 534 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&cpg CPG_MOD 407>; 541 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 542 resets = <&cpg 407>; 543 }; 544 545 tmu0: timer@e61e0000 { 546 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 547 reg = <0 0xe61e0000 0 0x30>; 548 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&cpg CPG_MOD 125>; 552 clock-names = "fck"; 553 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 554 resets = <&cpg 125>; 555 status = "disabled"; 556 }; 557 558 tmu1: timer@e6fc0000 { 559 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 560 reg = <0 0xe6fc0000 0 0x30>; 561 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&cpg CPG_MOD 124>; 565 clock-names = "fck"; 566 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 567 resets = <&cpg 124>; 568 status = "disabled"; 569 }; 570 571 tmu2: timer@e6fd0000 { 572 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 573 reg = <0 0xe6fd0000 0 0x30>; 574 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 577 clocks = <&cpg CPG_MOD 123>; 578 clock-names = "fck"; 579 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 580 resets = <&cpg 123>; 581 status = "disabled"; 582 }; 583 584 tmu3: timer@e6fe0000 { 585 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 586 reg = <0 0xe6fe0000 0 0x30>; 587 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 590 clocks = <&cpg CPG_MOD 122>; 591 clock-names = "fck"; 592 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 593 resets = <&cpg 122>; 594 status = "disabled"; 595 }; 596 597 tmu4: timer@ffc00000 { 598 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 599 reg = <0 0xffc00000 0 0x30>; 600 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 603 clocks = <&cpg CPG_MOD 121>; 604 clock-names = "fck"; 605 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 606 resets = <&cpg 121>; 607 status = "disabled"; 608 }; 609 610 i2c2: i2c@e6510000 { 611 reg = <0 0xe6510000 0 0x40>; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 status = "disabled"; 615 616 /* placeholder */ 617 }; 618 619 i2c4: i2c@e66d8000 { 620 #address-cells = <1>; 621 #size-cells = <0>; 622 reg = <0 0xe66d8000 0 0x40>; 623 status = "disabled"; 624 625 /* placeholder */ 626 }; 627 628 hscif0: serial@e6540000 { 629 compatible = "renesas,hscif-r8a774e1", 630 "renesas,rcar-gen3-hscif", 631 "renesas,hscif"; 632 reg = <0 0xe6540000 0 0x60>; 633 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&cpg CPG_MOD 520>, 635 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 636 <&scif_clk>; 637 clock-names = "fck", "brg_int", "scif_clk"; 638 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 639 <&dmac2 0x31>, <&dmac2 0x30>; 640 dma-names = "tx", "rx", "tx", "rx"; 641 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 642 resets = <&cpg 520>; 643 status = "disabled"; 644 }; 645 646 hscif1: serial@e6550000 { 647 compatible = "renesas,hscif-r8a774e1", 648 "renesas,rcar-gen3-hscif", 649 "renesas,hscif"; 650 reg = <0 0xe6550000 0 0x60>; 651 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 652 clocks = <&cpg CPG_MOD 519>, 653 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 654 <&scif_clk>; 655 clock-names = "fck", "brg_int", "scif_clk"; 656 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 657 <&dmac2 0x33>, <&dmac2 0x32>; 658 dma-names = "tx", "rx", "tx", "rx"; 659 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 660 resets = <&cpg 519>; 661 status = "disabled"; 662 }; 663 664 hscif2: serial@e6560000 { 665 compatible = "renesas,hscif-r8a774e1", 666 "renesas,rcar-gen3-hscif", 667 "renesas,hscif"; 668 reg = <0 0xe6560000 0 0x60>; 669 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 670 clocks = <&cpg CPG_MOD 518>, 671 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 672 <&scif_clk>; 673 clock-names = "fck", "brg_int", "scif_clk"; 674 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 675 <&dmac2 0x35>, <&dmac2 0x34>; 676 dma-names = "tx", "rx", "tx", "rx"; 677 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 678 resets = <&cpg 518>; 679 status = "disabled"; 680 }; 681 682 hscif3: serial@e66a0000 { 683 compatible = "renesas,hscif-r8a774e1", 684 "renesas,rcar-gen3-hscif", 685 "renesas,hscif"; 686 reg = <0 0xe66a0000 0 0x60>; 687 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&cpg CPG_MOD 517>, 689 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 690 <&scif_clk>; 691 clock-names = "fck", "brg_int", "scif_clk"; 692 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 693 dma-names = "tx", "rx"; 694 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 695 resets = <&cpg 517>; 696 status = "disabled"; 697 }; 698 699 hscif4: serial@e66b0000 { 700 compatible = "renesas,hscif-r8a774e1", 701 "renesas,rcar-gen3-hscif", 702 "renesas,hscif"; 703 reg = <0 0xe66b0000 0 0x60>; 704 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 705 clocks = <&cpg CPG_MOD 516>, 706 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 707 <&scif_clk>; 708 clock-names = "fck", "brg_int", "scif_clk"; 709 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 710 dma-names = "tx", "rx"; 711 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 712 resets = <&cpg 516>; 713 status = "disabled"; 714 }; 715 716 hsusb: usb@e6590000 { 717 reg = <0 0xe6590000 0 0x200>; 718 status = "disabled"; 719 720 /* placeholder */ 721 }; 722 723 usb3_phy0: usb-phy@e65ee000 { 724 reg = <0 0xe65ee000 0 0x90>; 725 #phy-cells = <0>; 726 status = "disabled"; 727 728 /* placeholder */ 729 }; 730 731 dmac0: dma-controller@e6700000 { 732 compatible = "renesas,dmac-r8a774e1", 733 "renesas,rcar-dmac"; 734 reg = <0 0xe6700000 0 0x10000>; 735 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 752 interrupt-names = "error", 753 "ch0", "ch1", "ch2", "ch3", 754 "ch4", "ch5", "ch6", "ch7", 755 "ch8", "ch9", "ch10", "ch11", 756 "ch12", "ch13", "ch14", "ch15"; 757 clocks = <&cpg CPG_MOD 219>; 758 clock-names = "fck"; 759 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 760 resets = <&cpg 219>; 761 #dma-cells = <1>; 762 dma-channels = <16>; 763 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 764 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 765 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 766 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 767 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 768 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 769 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 770 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 771 }; 772 773 dmac1: dma-controller@e7300000 { 774 compatible = "renesas,dmac-r8a774e1", 775 "renesas,rcar-dmac"; 776 reg = <0 0xe7300000 0 0x10000>; 777 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 794 interrupt-names = "error", 795 "ch0", "ch1", "ch2", "ch3", 796 "ch4", "ch5", "ch6", "ch7", 797 "ch8", "ch9", "ch10", "ch11", 798 "ch12", "ch13", "ch14", "ch15"; 799 clocks = <&cpg CPG_MOD 218>; 800 clock-names = "fck"; 801 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 802 resets = <&cpg 218>; 803 #dma-cells = <1>; 804 dma-channels = <16>; 805 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 806 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 807 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 808 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 809 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 810 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 811 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 812 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 813 }; 814 815 dmac2: dma-controller@e7310000 { 816 compatible = "renesas,dmac-r8a774e1", 817 "renesas,rcar-dmac"; 818 reg = <0 0xe7310000 0 0x10000>; 819 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 828 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 830 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 836 interrupt-names = "error", 837 "ch0", "ch1", "ch2", "ch3", 838 "ch4", "ch5", "ch6", "ch7", 839 "ch8", "ch9", "ch10", "ch11", 840 "ch12", "ch13", "ch14", "ch15"; 841 clocks = <&cpg CPG_MOD 217>; 842 clock-names = "fck"; 843 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 844 resets = <&cpg 217>; 845 #dma-cells = <1>; 846 dma-channels = <16>; 847 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 848 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 849 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 850 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 851 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 852 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 853 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 854 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 855 }; 856 857 ipmmu_ds0: iommu@e6740000 { 858 compatible = "renesas,ipmmu-r8a774e1"; 859 reg = <0 0xe6740000 0 0x1000>; 860 renesas,ipmmu-main = <&ipmmu_mm 0>; 861 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 862 #iommu-cells = <1>; 863 }; 864 865 ipmmu_ds1: iommu@e7740000 { 866 compatible = "renesas,ipmmu-r8a774e1"; 867 reg = <0 0xe7740000 0 0x1000>; 868 renesas,ipmmu-main = <&ipmmu_mm 1>; 869 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 870 #iommu-cells = <1>; 871 }; 872 873 ipmmu_hc: iommu@e6570000 { 874 compatible = "renesas,ipmmu-r8a774e1"; 875 reg = <0 0xe6570000 0 0x1000>; 876 renesas,ipmmu-main = <&ipmmu_mm 2>; 877 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 878 #iommu-cells = <1>; 879 }; 880 881 ipmmu_mm: iommu@e67b0000 { 882 compatible = "renesas,ipmmu-r8a774e1"; 883 reg = <0 0xe67b0000 0 0x1000>; 884 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 886 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 887 #iommu-cells = <1>; 888 }; 889 890 ipmmu_mp0: iommu@ec670000 { 891 compatible = "renesas,ipmmu-r8a774e1"; 892 reg = <0 0xec670000 0 0x1000>; 893 renesas,ipmmu-main = <&ipmmu_mm 4>; 894 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 895 #iommu-cells = <1>; 896 }; 897 898 ipmmu_pv0: iommu@fd800000 { 899 compatible = "renesas,ipmmu-r8a774e1"; 900 reg = <0 0xfd800000 0 0x1000>; 901 renesas,ipmmu-main = <&ipmmu_mm 6>; 902 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 903 #iommu-cells = <1>; 904 }; 905 906 ipmmu_pv1: iommu@fd950000 { 907 compatible = "renesas,ipmmu-r8a774e1"; 908 reg = <0 0xfd950000 0 0x1000>; 909 renesas,ipmmu-main = <&ipmmu_mm 7>; 910 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 911 #iommu-cells = <1>; 912 }; 913 914 ipmmu_pv2: iommu@fd960000 { 915 compatible = "renesas,ipmmu-r8a774e1"; 916 reg = <0 0xfd960000 0 0x1000>; 917 renesas,ipmmu-main = <&ipmmu_mm 8>; 918 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 919 #iommu-cells = <1>; 920 }; 921 922 ipmmu_pv3: iommu@fd970000 { 923 compatible = "renesas,ipmmu-r8a774e1"; 924 reg = <0 0xfd970000 0 0x1000>; 925 renesas,ipmmu-main = <&ipmmu_mm 9>; 926 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 927 #iommu-cells = <1>; 928 }; 929 930 ipmmu_vc0: iommu@fe6b0000 { 931 compatible = "renesas,ipmmu-r8a774e1"; 932 reg = <0 0xfe6b0000 0 0x1000>; 933 renesas,ipmmu-main = <&ipmmu_mm 12>; 934 power-domains = <&sysc R8A774E1_PD_A3VC>; 935 #iommu-cells = <1>; 936 }; 937 938 ipmmu_vc1: iommu@fe6f0000 { 939 compatible = "renesas,ipmmu-r8a774e1"; 940 reg = <0 0xfe6f0000 0 0x1000>; 941 renesas,ipmmu-main = <&ipmmu_mm 13>; 942 power-domains = <&sysc R8A774E1_PD_A3VC>; 943 #iommu-cells = <1>; 944 }; 945 946 ipmmu_vi0: iommu@febd0000 { 947 compatible = "renesas,ipmmu-r8a774e1"; 948 reg = <0 0xfebd0000 0 0x1000>; 949 renesas,ipmmu-main = <&ipmmu_mm 14>; 950 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 951 #iommu-cells = <1>; 952 }; 953 954 ipmmu_vi1: iommu@febe0000 { 955 compatible = "renesas,ipmmu-r8a774e1"; 956 reg = <0 0xfebe0000 0 0x1000>; 957 renesas,ipmmu-main = <&ipmmu_mm 15>; 958 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 959 #iommu-cells = <1>; 960 }; 961 962 ipmmu_vp0: iommu@fe990000 { 963 compatible = "renesas,ipmmu-r8a774e1"; 964 reg = <0 0xfe990000 0 0x1000>; 965 renesas,ipmmu-main = <&ipmmu_mm 16>; 966 power-domains = <&sysc R8A774E1_PD_A3VP>; 967 #iommu-cells = <1>; 968 }; 969 970 ipmmu_vp1: iommu@fe980000 { 971 compatible = "renesas,ipmmu-r8a774e1"; 972 reg = <0 0xfe980000 0 0x1000>; 973 renesas,ipmmu-main = <&ipmmu_mm 17>; 974 power-domains = <&sysc R8A774E1_PD_A3VP>; 975 #iommu-cells = <1>; 976 }; 977 978 avb: ethernet@e6800000 { 979 compatible = "renesas,etheravb-r8a774e1", 980 "renesas,etheravb-rcar-gen3"; 981 reg = <0 0xe6800000 0 0x800>; 982 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1001 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1002 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1003 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1004 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1005 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1006 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1007 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1008 "ch4", "ch5", "ch6", "ch7", 1009 "ch8", "ch9", "ch10", "ch11", 1010 "ch12", "ch13", "ch14", "ch15", 1011 "ch16", "ch17", "ch18", "ch19", 1012 "ch20", "ch21", "ch22", "ch23", 1013 "ch24"; 1014 clocks = <&cpg CPG_MOD 812>; 1015 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1016 resets = <&cpg 812>; 1017 phy-mode = "rgmii"; 1018 iommus = <&ipmmu_ds0 16>; 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 status = "disabled"; 1022 }; 1023 1024 can0: can@e6c30000 { 1025 reg = <0 0xe6c30000 0 0x1000>; 1026 status = "disabled"; 1027 1028 /* placeholder */ 1029 }; 1030 1031 can1: can@e6c38000 { 1032 reg = <0 0xe6c38000 0 0x1000>; 1033 status = "disabled"; 1034 1035 /* placeholder */ 1036 }; 1037 1038 pwm0: pwm@e6e30000 { 1039 reg = <0 0xe6e30000 0 0x8>; 1040 #pwm-cells = <2>; 1041 status = "disabled"; 1042 1043 /* placeholder */ 1044 }; 1045 1046 scif0: serial@e6e60000 { 1047 compatible = "renesas,scif-r8a774e1", 1048 "renesas,rcar-gen3-scif", "renesas,scif"; 1049 reg = <0 0xe6e60000 0 0x40>; 1050 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1051 clocks = <&cpg CPG_MOD 207>, 1052 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1053 <&scif_clk>; 1054 clock-names = "fck", "brg_int", "scif_clk"; 1055 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1056 <&dmac2 0x51>, <&dmac2 0x50>; 1057 dma-names = "tx", "rx", "tx", "rx"; 1058 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1059 resets = <&cpg 207>; 1060 status = "disabled"; 1061 }; 1062 1063 scif1: serial@e6e68000 { 1064 compatible = "renesas,scif-r8a774e1", 1065 "renesas,rcar-gen3-scif", "renesas,scif"; 1066 reg = <0 0xe6e68000 0 0x40>; 1067 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1068 clocks = <&cpg CPG_MOD 206>, 1069 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1070 <&scif_clk>; 1071 clock-names = "fck", "brg_int", "scif_clk"; 1072 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1073 <&dmac2 0x53>, <&dmac2 0x52>; 1074 dma-names = "tx", "rx", "tx", "rx"; 1075 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1076 resets = <&cpg 206>; 1077 status = "disabled"; 1078 }; 1079 1080 scif2: serial@e6e88000 { 1081 compatible = "renesas,scif-r8a774e1", 1082 "renesas,rcar-gen3-scif", "renesas,scif"; 1083 reg = <0 0xe6e88000 0 0x40>; 1084 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1085 clocks = <&cpg CPG_MOD 310>, 1086 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1087 <&scif_clk>; 1088 clock-names = "fck", "brg_int", "scif_clk"; 1089 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1090 <&dmac2 0x13>, <&dmac2 0x12>; 1091 dma-names = "tx", "rx", "tx", "rx"; 1092 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1093 resets = <&cpg 310>; 1094 status = "disabled"; 1095 }; 1096 1097 scif3: serial@e6c50000 { 1098 compatible = "renesas,scif-r8a774e1", 1099 "renesas,rcar-gen3-scif", "renesas,scif"; 1100 reg = <0 0xe6c50000 0 0x40>; 1101 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1102 clocks = <&cpg CPG_MOD 204>, 1103 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1104 <&scif_clk>; 1105 clock-names = "fck", "brg_int", "scif_clk"; 1106 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1107 dma-names = "tx", "rx"; 1108 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1109 resets = <&cpg 204>; 1110 status = "disabled"; 1111 }; 1112 1113 scif4: serial@e6c40000 { 1114 compatible = "renesas,scif-r8a774e1", 1115 "renesas,rcar-gen3-scif", "renesas,scif"; 1116 reg = <0 0xe6c40000 0 0x40>; 1117 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1118 clocks = <&cpg CPG_MOD 203>, 1119 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1120 <&scif_clk>; 1121 clock-names = "fck", "brg_int", "scif_clk"; 1122 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1123 dma-names = "tx", "rx"; 1124 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1125 resets = <&cpg 203>; 1126 status = "disabled"; 1127 }; 1128 1129 scif5: serial@e6f30000 { 1130 compatible = "renesas,scif-r8a774e1", 1131 "renesas,rcar-gen3-scif", "renesas,scif"; 1132 reg = <0 0xe6f30000 0 0x40>; 1133 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1134 clocks = <&cpg CPG_MOD 202>, 1135 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1136 <&scif_clk>; 1137 clock-names = "fck", "brg_int", "scif_clk"; 1138 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1139 <&dmac2 0x5b>, <&dmac2 0x5a>; 1140 dma-names = "tx", "rx", "tx", "rx"; 1141 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1142 resets = <&cpg 202>; 1143 status = "disabled"; 1144 }; 1145 1146 rcar_sound: sound@ec500000 { 1147 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1148 <0 0xec5a0000 0 0x100>, /* ADG */ 1149 <0 0xec540000 0 0x1000>, /* SSIU */ 1150 <0 0xec541000 0 0x280>, /* SSI */ 1151 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1152 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1153 1154 status = "disabled"; 1155 1156 /* placeholder */ 1157 1158 rcar_sound,ssi { 1159 ssi2: ssi-2 { 1160 /* placeholder */ 1161 }; 1162 }; 1163 }; 1164 1165 xhci0: usb@ee000000 { 1166 reg = <0 0xee000000 0 0xc00>; 1167 status = "disabled"; 1168 1169 /* placeholder */ 1170 }; 1171 1172 usb3_peri0: usb@ee020000 { 1173 reg = <0 0xee020000 0 0x400>; 1174 status = "disabled"; 1175 1176 /* placeholder */ 1177 }; 1178 1179 ohci0: usb@ee080000 { 1180 reg = <0 0xee080000 0 0x100>; 1181 status = "disabled"; 1182 1183 /* placeholder */ 1184 }; 1185 1186 ohci1: usb@ee0a0000 { 1187 reg = <0 0xee0a0000 0 0x100>; 1188 status = "disabled"; 1189 1190 /* placeholder */ 1191 }; 1192 1193 ehci0: usb@ee080100 { 1194 reg = <0 0xee080100 0 0x100>; 1195 status = "disabled"; 1196 1197 /* placeholder */ 1198 }; 1199 1200 ehci1: usb@ee0a0100 { 1201 reg = <0 0xee0a0100 0 0x100>; 1202 status = "disabled"; 1203 1204 /* placeholder */ 1205 }; 1206 1207 usb2_phy0: usb-phy@ee080200 { 1208 reg = <0 0xee080200 0 0x700>; 1209 status = "disabled"; 1210 1211 /* placeholder */ 1212 }; 1213 1214 usb2_phy1: usb-phy@ee0a0200 { 1215 reg = <0 0xee0a0200 0 0x700>; 1216 status = "disabled"; 1217 1218 /* placeholder */ 1219 }; 1220 1221 sdhi0: mmc@ee100000 { 1222 reg = <0 0xee100000 0 0x2000>; 1223 status = "disabled"; 1224 1225 /* placeholder */ 1226 }; 1227 1228 sdhi2: mmc@ee140000 { 1229 reg = <0 0xee140000 0 0x2000>; 1230 status = "disabled"; 1231 1232 /* placeholder */ 1233 }; 1234 1235 sdhi3: mmc@ee160000 { 1236 compatible = "renesas,sdhi-r8a774e1", 1237 "renesas,rcar-gen3-sdhi"; 1238 reg = <0 0xee160000 0 0x2000>; 1239 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1240 clocks = <&cpg CPG_MOD 311>; 1241 max-frequency = <200000000>; 1242 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1243 resets = <&cpg 311>; 1244 status = "disabled"; 1245 }; 1246 1247 gic: interrupt-controller@f1010000 { 1248 compatible = "arm,gic-400"; 1249 #interrupt-cells = <3>; 1250 #address-cells = <0>; 1251 interrupt-controller; 1252 reg = <0x0 0xf1010000 0 0x1000>, 1253 <0x0 0xf1020000 0 0x20000>, 1254 <0x0 0xf1040000 0 0x20000>, 1255 <0x0 0xf1060000 0 0x20000>; 1256 interrupts = <GIC_PPI 9 1257 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1258 clocks = <&cpg CPG_MOD 408>; 1259 clock-names = "clk"; 1260 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1261 resets = <&cpg 408>; 1262 }; 1263 1264 pciec0: pcie@fe000000 { 1265 reg = <0 0xfe000000 0 0x80000>; 1266 #address-cells = <3>; 1267 #size-cells = <2>; 1268 status = "disabled"; 1269 1270 /* placeholder */ 1271 }; 1272 1273 hdmi0: hdmi@fead0000 { 1274 reg = <0 0xfead0000 0 0x10000>; 1275 status = "disabled"; 1276 1277 /* placeholder */ 1278 1279 ports { 1280 #address-cells = <1>; 1281 #size-cells = <0>; 1282 1283 port@0 { 1284 reg = <0>; 1285 }; 1286 port@1 { 1287 reg = <1>; 1288 }; 1289 port@2 { 1290 reg = <2>; 1291 }; 1292 }; 1293 }; 1294 1295 du: display@feb00000 { 1296 reg = <0 0xfeb00000 0 0x80000>; 1297 status = "disabled"; 1298 1299 /* placeholder */ 1300 ports { 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 1304 port@0 { 1305 reg = <0>; 1306 }; 1307 port@1 { 1308 reg = <1>; 1309 }; 1310 port@2 { 1311 reg = <2>; 1312 }; 1313 }; 1314 }; 1315 1316 prr: chipid@fff00044 { 1317 compatible = "renesas,prr"; 1318 reg = <0 0xfff00044 0 4>; 1319 }; 1320 }; 1321 1322 thermal-zones { 1323 sensor_thermal1: sensor-thermal1 { 1324 polling-delay-passive = <250>; 1325 polling-delay = <1000>; 1326 thermal-sensors = <&tsc 0>; 1327 sustainable-power = <6313>; 1328 1329 trips { 1330 sensor1_crit: sensor1-crit { 1331 temperature = <120000>; 1332 hysteresis = <1000>; 1333 type = "critical"; 1334 }; 1335 }; 1336 }; 1337 1338 sensor_thermal2: sensor-thermal2 { 1339 polling-delay-passive = <250>; 1340 polling-delay = <1000>; 1341 thermal-sensors = <&tsc 1>; 1342 sustainable-power = <6313>; 1343 1344 trips { 1345 sensor2_crit: sensor2-crit { 1346 temperature = <120000>; 1347 hysteresis = <1000>; 1348 type = "critical"; 1349 }; 1350 }; 1351 }; 1352 1353 sensor_thermal3: sensor-thermal3 { 1354 polling-delay-passive = <250>; 1355 polling-delay = <1000>; 1356 thermal-sensors = <&tsc 2>; 1357 sustainable-power = <6313>; 1358 1359 trips { 1360 target: trip-point1 { 1361 temperature = <100000>; 1362 hysteresis = <1000>; 1363 type = "passive"; 1364 }; 1365 1366 sensor3_crit: sensor3-crit { 1367 temperature = <120000>; 1368 hysteresis = <1000>; 1369 type = "critical"; 1370 }; 1371 }; 1372 1373 cooling-maps { 1374 map0 { 1375 trip = <&target>; 1376 cooling-device = <&a57_0 0 2>; 1377 contribution = <1024>; 1378 }; 1379 1380 map1 { 1381 trip = <&target>; 1382 cooling-device = <&a53_0 0 2>; 1383 contribution = <1024>; 1384 }; 1385 }; 1386 }; 1387 }; 1388 1389 timer { 1390 compatible = "arm,armv8-timer"; 1391 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1392 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1393 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1394 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1395 }; 1396 1397 /* External USB clocks - can be overridden by the board */ 1398 usb3s0_clk: usb3s0 { 1399 compatible = "fixed-clock"; 1400 #clock-cells = <0>; 1401 clock-frequency = <0>; 1402 }; 1403 1404 usb_extal_clk: usb_extal { 1405 compatible = "fixed-clock"; 1406 #clock-cells = <0>; 1407 clock-frequency = <0>; 1408 }; 1409}; 1410